Abstract: Disclosed is a semiconductor light emitting device, including: a body, which has a bottom part with at least one hole formed therein, a side wall, and a cavity defined by the bottom part and the side wall; a semiconductor light emitting chip, which is placed in each hole and includes plural semiconductor layers adapted to generate light by electron-hole recombination and electrodes electrically connected to the plural semiconductor layers; and an encapsulating member provided at least to the cavity to cover the semiconductor light emitting chip, in which the electrodes of the semiconductor light emitting chip are exposed towards the lower face of the bottom part of the body.

Abstract: The present invention relates to a method of manufacturing a capacitive micro-machined transducer (100), in particular a CMUT, the method comprising depositing a first electrode layer (10) on a substrate (1), depositing a first dielectric film (20) on the first electrode layer (10), depositing a sacrificial layer (30) on the first dielectric film (20), the sacrificial layer (30) being removable for forming a cavity (35) of the transducer, depositing a second dielectric film (40) on the sacrificial layer (30), and depositing a second electrode layer (50) on the second dielectric film (40), wherein the first dielectric film (20) and/or the second dielectric film (40) comprises a first layer comprising an oxide, a second layer comprising a high-k material, and a third layer comprising an oxide, and wherein the depositing steps are performed by Atomic Layer Deposition. The present invention further relates to a capacitive micro-machined transducer (100), in particular a CMUT, manufactured by such method.

Abstract: A method for forming a semiconductor structure includes providing a semiconductor substrate having a metal gate structure formed on the semiconductor substrate; forming a first dielectric layer covering a side surface of the metal gate structure on the semiconductor substrate; forming a cap layer on the metal gate structure; etching a top portion of the first dielectric layer using the cap layer as an etching mask; forming a protective sidewall spacer on a side surface of the cap layer and a side surface of a portion of the first dielectric layer under the cap layer; forming a second dielectric layer to cover the cap layer, the protective sidewall spacer and a top surface of the etched first dielectric layer; forming at least a first through-hole in the second dielectric layer; and forming a first conductive via in the first through-hole.

Abstract: In a general aspect, a power semiconductor device can include a silicon carbide (SiC) substrate and a SiC epi-layer disposed on the SiC substrate. The device can also include a first well region, a second well region disposed in the SiC epi-layer, a first source region disposed in the first well region, and a second source region disposed in the second well region. The device can further include a gate structure disposed on the SiC epi-layer and extending between the first source region and the second source region. The gate structure can include a hybrid gate dielectric. The hybrid gate dielectric can include a first high-k dielectric material and a second high-k dielectric material. The device can also include a conductive gate electrode disposed on the hybrid gate dielectric.

Abstract: An electrostatic discharge (ESD) protection circuit (FIG. 3C) is disclosed. The circuit includes a bipolar transistor (304) having a base, collector, and emitter. Each of a plurality of diodes (308-316) has a first terminal coupled to the base and a second terminal coupled to the collector. The collector is connected to a first terminal (V+). The emitter is connected to a first power supply terminal (V?).

Abstract: An advanced metal conductor structure is described. An integrated circuit device including a substrate with a patterned dielectric layer. The pattern includes a set of features in the dielectric for a set of metal conductor structures. An adhesion promoting layer disposed over the set of features in the patterned dielectric and a ruthenium layer is disposed over the adhesion promoting layer. A cobalt layer is disposed over the ruthenium layer filling the set of features, wherein the cobalt layer is formed using a physical vapor deposition process.

Abstract: The invention provides an electrostatic discharge (ESD) protection device formed by a Schottky diode. An exemplary embodiment of an ESD protection device comprises a semiconductor substrate having an active region. A first well region having a first conductive type is formed in the active region. A first heavily doped region having the first conductive type is formed in the first well region. A first metal contact is disposed on the first doped region. A second metal contact is disposed on the active region, connecting to the first well region without through any heavily doped region being located therebetween, wherein the first metal contact and the second metal contact are separated by a polysilicon pattern disposed on the first well region.

Abstract: A semiconductor light-emitting element comprises: a semiconductor structure layer including a first semiconductor layer having a first conductivity type, a light-emitting layer and a second semiconductor layer having a second conductivity type opposite to the first conductivity type being laminated in sequence; a first electrode including a first electrode layer formed on the first semiconductor layer and a first contact electrode connected to the first electrode layer at a position displaced from a center of the first electrode layer in an intra-layer direction of the first electrode layer; and a second electrode extending through the first electrode layer, the first semiconductor layer and the light-emitting layer and being connected to the second semiconductor layer.

Abstract: A method for fabricating a fully depleted silicon on insulator (FDSOI) device is described. A charge trapping layer in a buried oxide layer is provided on a semiconductor substrate. A backgate well in the semiconductor substrate is provided under the charge trapping layer. A device structure including a gate structure, source and drain regions is disposed over the buried oxide layer. A charge is trapped in the charge trapping layer. The threshold voltage of the device is partially established by the charge trapped in the charge trapping layer. Different aspects of the invention include the structure of the FDSOI device and a method of tuning the charge trapped in the charge trapping layer of the FDSOI device.

Abstract: An advanced metal conductor structure and a method for constructing the structure are described. A pattern is provided in a dielectric layer. The pattern includes a set of features in the dielectric for a set of metal conductor structures. An adhesion promoting layer is created over the patterned dielectric. A ruthenium layer disposed over the adhesion promoting layer is deposited. A nitridation process is performed on the ruthenium layer to produce a nitridized ruthenium layer. Using a physical vapor deposition process, a cobalt layer is deposited disposed over the nitridized ruthenium layer. A thermal anneal is performed which reflows the cobalt layer to fill the set of features to form a set of metal conductor structures. In another aspect of the invention, an integrated circuit device is formed using the method.

Abstract: An advanced metal conductor structure is described. An integrated circuit device including a substrate having a dielectric layer is patterned. The pattern includes a set of features in the dielectric for a set of metal conductor structures. An adhesion promoting layer is disposed over the set of features in the patterned dielectric. A nitridized ruthenium layer is disposed over the adhesion promoting layer. A cobalt layer disposed over the nitridized ruthenium layer filling the set of features, wherein the cobalt layer is formed using a physical vapor deposition process.

Abstract: A display device is provided including a display region arranged with a plurality of pixels, and a first sealing region arranged in an exterior periphery part of the display region, the display region includes an individual pixel electrode arranged in each of the plurality of pixels, a common pixel electrode arranged in upper layer of the individual pixel electrode and in succession to the plurality of pixels, and a light emitting layer arranged between the individual pixel electrode and the common pixel electrode, and the first sealing region includes a sealing layer arranged on a lower layer than the common pixel electrode and a region stacked with the common pixel electrode extending from the display region, the stacked region being enclosed by the display region.

Abstract: A semiconductor device has a semiconductor chip having a first surface with metallized terminals and a parallel second surface. A frame of insulating material adheres to at the sidewalls of the chip. The frame has a first surface planar with the first chip surface and a parallel second surface planar with the second chip surface. The first frame surface includes one or more embedded metallic fiducials extending from the first surface to the insulating material. At least one film of sputtered metal extends from the terminals across the surface of the polymeric layer to the fiducials. The film is patterned to form extended contact pads over the frame and rerouting traces between the chip terminals and the extended contact pads. The film adheres to the surfaces.

Abstract: The present disclosure relates to a semiconductor device with vertically integrated pseudomorphic high electron mobility transistors (pHEMTs). The disclosed semiconductor device includes a substrate, a lower pHEMT structure with a lower pHEMT, an isolation layer, and an upper pHEMT structure with an upper pHEMT. The lower pHEMT structure is formed over the substrate and has a first region and a second region that is laterally disposed with the first region. The lower pHEMT is formed in or on the second region. The isolation layer resides over the first region. The upper pHEMT structure is formed over the isolation layer and does not extend over the second region. Herein, the isolation layer separates the lower pHEMT structure from the upper pHEMT structure such that the lower pHEMT and the upper pHEMT operate independently from each other.

Abstract: According to one embodiment, a thin-film transistor and a method of manufacturing the same achieve size reduction of the thin-film transistor while using an oxide semiconductor layer. The oxide semiconductor layer includes a channel region, a source region, and a drain region. A gate electrode is arranged at a position spaced from the channel region of the oxide semiconductor layer so as to face the channel region. A source electrode is electrically connected to the source region of the oxide semiconductor layer. A drain electrode is electrically connected to the drain region of the oxide semiconductor layer. An undercoat layer adjoins the source region and the drain region of the oxide semiconductor layer. A hydrogen blocking layer has a hydrogen concentration lower than that in the undercoat layer and separates the undercoat layer and the channel region of the oxide semiconductor layer.

Abstract: An electrostatic discharge (ESD) protection circuit (FIG. 3C) is disclosed. The circuit includes a bipolar transistor (304) having a base, collector, and emitter. Each of a plurality of diodes (308-316) has a first terminal coupled to the base and a second terminal coupled to the collector. The collector is connected to a first terminal (V+). The emitter is connected to a first power supply terminal (V?).

Abstract: A semiconductor device includes a device isolation region defining an active region in a substrate, and gate structures buried in the active region of the substrate. At least one of the gate structures includes a gate trench, a gate insulating layer conformally formed on an inner wall of the gate trench, a gate barrier pattern conformally formed on the gate insulating layer disposed on a lower portion of the gate trench, a gate electrode pattern formed on the gate barrier pattern and filling the lower portion of the gate trench, an electrode protection layer conformally formed on the gate insulating layer disposed on an upper portion of the gate trench to be in contact with the gate barrier pattern and the gate electrode pattern, a buffer oxide layer conformally formed on the electrode protection layer, and a gate capping insulating layer formed on the buffer oxide layer to fill the upper portion of the gate trench.

Abstract: The invention provides an electrostatic discharge (ESD) protection device. The ESD protection device includes a semiconductor substrate having an active region, a first well region having a first conductive type formed in the active region, a first doped region having the first conductive type formed in the first well region, a first metal contact disposed on the first doped region, and a second metal contact disposed on the active region, connecting to the first well region, wherein no doped region is formed between the second metal contact and the first well region.

Abstract: The invention relates to a method for dividing a composite into a plurality of semiconductor chips along a dividing pattern. A composite, which comprises a substrate, a semiconductor layer sequence, and a functional layer, is provided. Separating trenches are formed in the substrate along the dividing pattern. The functional layer is cut through along the dividing pattern by means of coherent radiation. Each divided semiconductor chip has part of the semiconductor layer sequence, part of the substrate, and part of the functional layer. The invention further relates to a semiconductor chip.

Abstract: A manufacturing method of an array substrate comprises: forming a source and a drain of a thin film transistor on a base; forming a first insulation layer; forming an active layer of the thin film transistor; forming a second insulation layer; forming a first via hole and a second via hole in the first insulation layer and the second insulation layer above the source and the drain, by etching, and forming a third via hole and a fourth via hole in the second insulation layer above the active layer, by etching; forming a first connection line connecting the source with the active layer through the first via hole and the third via hole, a second connection line connecting the drain with the active layer and the pixel electrode through the second via hole and the fourth via hole and a pixel electrode.