Patents Examined by Whitney Moore
  • Patent number: 10374105
    Abstract: An optoelectronic device includes an etched body comprising a buried metal contact layer on a top surface of a semiconductor structure, which comprises one or more semiconductor layers. The buried metal contact layer includes an arrangement of holes therein. A plurality of nanopillar structures protrude from the top surface of the semiconductor structure and pass through the arrangement of holes. Each nanopillar structure is surrounded at a base thereof by a portion of the buried metal contact layer. When the etched body is exposed to incident radiation having a wavelength in the range from about 300 nm to about 10 microns, at least about 50% of the incident radiation is transmitted through the etched body at a peak transmission wavelength ?max.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: August 6, 2019
    Assignee: The Board of Trustees of the University of Illinois
    Inventors: Xiuling Li, Daniel M. Wasserman, Xiang Zhao
  • Patent number: 10371512
    Abstract: A method for multiple 3D sensor calibration for a passenger conveyance system, the process including a computing a centroid location from spatial measurements for each of a pair of 3D sensors that form a common field of view via a moving object mathematical model; computing translation parameters from the locations of each centroid location; and correcting one of the pair of 3D sensors to a common world coordinate system from the translation parameters.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: August 6, 2019
    Assignee: Otis Elevator Company
    Inventors: Zhen Jia, Yanzhi Chen, Hui Fang, Arthur Hsu, Alan Matthew Finn
  • Patent number: 10366928
    Abstract: A semiconductor device having a uniform height across different fin densities includes a semiconductor substrate having fins etched therein and including dense fin regions and isolation regions without fins. One or more dielectric layers are formed at a base of the fins and the isolation regions and have a uniform height across the fins and the isolation regions. The uniform height includes a less than 2 nanometer difference across the one or more dielectric layers.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: July 30, 2019
    Assignee: International Business Machines Corporation
    Inventors: Zhenxing Bi, Donald F. Canaperi, Thamarai S. Devarajan, Sivananda K. Kanakasabapathy, Fee Li Lie, Peng Xu
  • Patent number: 10343196
    Abstract: Methods, systems, and computer program products for in-pipeline maintenance, delivery and management of sensors are provided herein. A multi-component, in-pipeline sensor management system includes a self-propelled sensor explorer component comprising (i) one or more communication sub-components and (ii) one or more navigation assistance sub-components, wherein the self-propelled sensor explorer component is configured to move through a liquid within a pipeline; a sensor coupling unit comprising one or more attachment structures, wherein the one or more attachment structures enable the system to attach to one or more sensors within the pipeline; and a sensor maintenance unit comprising (i) a cleansing unit, wherein the cleansing unit comprises (a) an inlet valve for one or more cleaning liquids and (b) an outlet valve for one or more waste liquids, (ii) a cleaning liquid storage component coupled to the inlet valve, and (iii) a waste liquid collector coupled to the outlet valve.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: July 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Sukanya Randhawa, Ninad D. Sathaye, Ashwin Srinivas
  • Patent number: 10342994
    Abstract: One example method for generating a dose estimation model for radiotherapy treatment planning may include obtaining training data that includes multiple treatment plans associated with respective multiple past patients. The method may also include processing the training data to determine, from each of the multiple treatment plans, first data that includes one or more features associated with a particular past patient, second data associated with treatment planning trade-off selected for the particular past patient and third data associated with radiation dose for delivery to the particular past patient. The method may further include generating the dose estimation model by training, based on the first data, second data and third data from the multiple treatment plans, the dose estimation model to estimate a relationship that transforms the first data and second data to the third data.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: July 9, 2019
    Assignee: VARIAN MEDICAL SYSTEMS INTERNATIONAL AG
    Inventors: Esa Kuusela, Lauri Halko, María Cordero Marcos
  • Patent number: 10346593
    Abstract: Example methods for radiotherapy treatment planning are provided. One example method may include obtaining training data that includes multiple treatment plans associated with respective multiple past patients; and processing the training data to determine, from each of the multiple treatment plans, at least one of the following: first data associated with a particular past patient or a radiotherapy system for delivering radiotherapy treatment to the particular past patient, second data associated with treatment planning trade-off selected for the particular past patient and third data associated with radiation dose for delivery to the particular past patient. The method may also comprise: based on at least one of the first data, the second data and the third data, identifying one or more sub-optimal characteristics associated with the training data, obtaining improved training data and generating a dose estimation model based on the improved training data.
    Type: Grant
    Filed: October 16, 2017
    Date of Patent: July 9, 2019
    Assignee: VARIAN MEDICAL SYSTEMS INTERNATIONAL AG
    Inventors: Esa Kuusela, Hannu Laaksonen, María Cordero Marcos
  • Patent number: 10326000
    Abstract: A method of fabricating a finFET semiconductor device, the method including forming a self-aligned silicide contact above and in direct contact with exposed portions of semiconductor fins not covered by a gate electrode, wherein an upper surface of the self-aligned silicide contact is substantially flush with an upper surface of an adjacent isolation region, patterning a blanket metal layer to form a source-drain contact on the upper surface of the self-aligned silicide contact, the self-aligned silicide contact provides an electrical path from the semiconductor fins to the source-drain contact, and recessing a portion of the self-aligned silicide contact without recessing the isolation region, the self-aligned silicide contact is recessed selective to a mask used to pattern the source-drain contact.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: June 18, 2019
    Assignee: International Business Machines Corporation
    Inventors: Emre Alptekin, Veeraraghavan S. Basker, Sivananda K. Kanakasabapathy
  • Patent number: 10325852
    Abstract: A metallization scheme for vertical field effect transistors (FETs) is provided. By forming lower-level local interconnects connecting source regions located at bottom portions of semiconductor fins, and upper-level interconnects connecting adjacent metal gates located along sidewalls of channel regions of the semiconductor fins, electrical connections to the source regions and the metal gates can be provided through the lower-level local interconnects and the upper-level local interconnects, respectively. As a result, gate, source and drain contact structures are formed on the same side of vertical FETs.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: June 18, 2019
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 10324436
    Abstract: A system of hardware configuration of a programmable control instrument, test and measure that includes an integrated FPGA is disclosed. The FPGA includes a static section comprising at least one static logic FPGA preset; a dynamic section comprising at least one dynamic logic FPGA programmable by a user; and a logical interface that connects the static section and dynamic section.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: June 18, 2019
    Assignee: Keysight Technologies Singapore (Sales) Pte. Ltd.
    Inventors: Nestor Hugo Oliverio, Marc Almendros Parra
  • Patent number: 10319816
    Abstract: A fin field effect transistor includes a Si fin including a central portion between end portions of the fin, and a SiGe channel region disposed on the central portion of the fin. The SiGe channel region includes a facet free SiGe region having Ge atoms diffused into the Si fin and includes a same shape as the Si fin outside the central portion.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: June 11, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, STMICROELECTRONICS, INC.
    Inventors: Hong He, Nicolas Loubet, Junli Wang
  • Patent number: 10319840
    Abstract: A method of forming a fin field effect transistor (finFET), including forming a temporary gate structure having a sacrificial gate layer and a dummy gate layer on the sacrificial gate layer, forming a gate spacer layer on each sidewall of the temporary gate structure, forming a source/drain spacer layer on the outward-facing sidewall of each gate spacer layer, removing the dummy gate layer to expose the sacrificial gate layer, removing the sacrificial gate layer to form a plurality of recessed cavities, and forming a gate structure, where the gate structure occupies at least a portion of the plurality of recessed cavities.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: June 11, 2019
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita, Chun-Chen Yeh
  • Patent number: 10312250
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a plurality of isolation structures, a charge storage layer, and a conductive layer. The substrate has a memory region and a logic region. The substrate in the memory region has a plurality of semiconductor fins. The isolation structures are disposed in the substrate to isolate the semiconductor fins. The semiconductor fins are protruded beyond the isolation structures. The charge storage layer covers the semiconductor fins. The conductive layer is disposed across the semiconductor fins and the isolation structures such that the charge storage layer is disposed between the conductive layer and the semiconductor fins.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: June 4, 2019
    Assignee: United Microelectronics Corp.
    Inventors: Hsuan-Chun Tseng, Hsueh-Chun Hsiao, Tzu-Yun Chang, Chi-Cheng Huang, Ping-Chia Shih
  • Patent number: 10304987
    Abstract: The present disclosure relates to optical receiver systems. An example optical receiver system includes a first substrate with a plurality of photodetectors and a bias circuit. The bias circuit is electrically coupled to each photodetector of the plurality of photodetectors. The bias circuit is configured to provide a bias voltage to each photodetector. The optical receiver system also includes a plurality of capacitors. Each capacitor of the plurality of capacitors is electrically-coupled to a respective photodetector of the plurality of photodetectors. The optical receiver system also includes a second substrate with a read-out circuit having a plurality of channels. Each channel of the plurality of channels is capacitively-coupled to a respective photodetector via the respective capacitor.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: May 28, 2019
    Assignee: Waymo LLC
    Inventors: Pierre-Yves Droz, Caner Onal
  • Patent number: 10297543
    Abstract: A vertical semiconductor device including a plurality of interlayer insulating layer patterns spaced apart from each other on a substrate and stacked in a vertical direction; a plurality of conductive layer patterns arranged between the interlayer insulating layer patterns and each having a rounded end, wherein at least one of the conductive layer patterns is configured to extend from one side wall of each of the interlayer insulating layer patterns and include a pad region, and the pad region includes a raised pad portion configured to protrude from a surface of the at least one conductive layer pattern; an upper interlayer insulating layer to cover the interlayer insulating layer patterns and the conductive layer patterns; and a contact plug configured to penetrate the upper interlayer insulating layer to be in contact with the raised pad portion of the at least one conductive layer pattern.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: May 21, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jo-young Park, Chang-seok Kang, Chang-sup Lee, Se-mee Jang
  • Patent number: 10289143
    Abstract: A system for predicting power and loads over a single, relatively short time horizon. More specifically, a system comprising a Storage Agent (S-agent) Cohort within a grid control society, wherein the system expands G and L intra-cohort protocols to allow the S-cohort to participate in power management of the grid by scheduling storage components in source or load roles as determined by the time-varying state of the power imbalance and by the risk-adjusting capacity margin relationship between the G and L cohorts.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: May 14, 2019
    Assignee: Michigan Technological University
    Inventor: Steven Goldsmith
  • Patent number: 10288653
    Abstract: A method for identifying frequently occurring waveform patterns in time series comprises segmenting each of one or more time series into a plurality of subsequences. Further, a subsequence matrix comprising each of the plurality of subsequences is generated. Further, the subsequence matrix is processed to obtain a candidate subsequence matrix comprising a plurality of non-trivial subsequences. Further, the plurality of non-trivial subsequences is clustered into a plurality of spherical clusters of a predetermined diameter. Further, a plurality of sub-clusters for each of one or more spherical clusters is obtained based on a mean of each of the plurality of non-trivial subsequences present in the spherical cluster. Further, one or more frequent waveform clusters, depicting frequently occurring waveform patterns, are ascertained from amongst the one or more spherical clusters based on a number of non-trivial subsequences present in each of the plurality of sub-clusters of the spherical cluster.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: May 14, 2019
    Assignee: TATA CONSULTANCY SERVICES LIMITED
    Inventors: Puneet Agarwal, Gautam Shroff, Rishabh Gupta
  • Patent number: 10291024
    Abstract: A control method performed in a microgrid. The microgrid includes at least one electrical power source and/or configured for injecting electrical power into the microgrid, a first point of common coupling (PCC) configured for allowing a first power flow between the microgrid and a first power grid, and a second PCC configured for allowing a second power flow between the microgrid and a second power grid. The method includes obtaining information about a change in the first power flow, and controlling the second power flow based on the obtained information.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: May 14, 2019
    Assignee: ABB Schweiz AG
    Inventors: Ritwik Majumder, Joydeep Mukherjee, Eyke Liegmann
  • Patent number: 10287681
    Abstract: The present invention relates to a copper metal film to be used as a seed layer for electrodeposition for forming a copper interconnect for a semiconductor device, a method for preparing the same, and a method for forming a copper interconnect for a semiconductor device using the copper metal film.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: May 14, 2019
    Assignee: UP Chemical Co., Ltd.
    Inventors: Won-Jun Lee, Jae-Min Park
  • Patent number: 10283588
    Abstract: An integrated circuit may include an SOI substrate having a buried insulating layer, and a semiconductor film above the buried insulating layer. The semiconductor film may have first patterns in a first zone defining gate regions of first MOS transistors and also first dummy gate regions. The first zone may include two domains having a space therebetween, and the space may be filled by at least one insulating material and be situated between two dummy gate regions above a region of the supporting substrate without any insulating trench.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: May 7, 2019
    Assignee: STMICROELECTRONICS (CROLLES 2) SAS
    Inventor: Emmanuel Perrin
  • Patent number: 10275717
    Abstract: Methods, systems, and apparatus for training quantum evolutions using sub-logical controls. In one aspect, a method includes the actions of accessing quantum hardware, wherein the quantum hardware includes a quantum system comprising one or more multi-level quantum subsystems; one or more control devices that operate on the one or more multi-level quantum subsystems according to one or more respective control parameters that relate to a parameter of a physical environment in which the multi-level quantum subsystems are located; initializing the quantum system in an initial quantum state, wherein an initial set of control parameters form a parameterization that defines the initial quantum state; obtaining one or more quantum system observables and one or more target quantum states; and iteratively training until an occurrence of a completion event.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: April 30, 2019
    Assignee: Google LLC
    Inventors: Ryan Babbush, Hartmut Neven