Patents Examined by William A. Powell
  • Patent number: 7097775
    Abstract: A microfluidic delivery system substrate is coated with ultra-nanocrystalline diamond (UNCD) or with a thin ceramic film, such as alumina or zirconia, that is applied by ion-beam assisted deposition; assuring that the device is impermeably sealed, to prevent the substrate from being dissolved by hostile environments and to protect the molecules from premature release or undesired reaction with hostile environments. The UNCD coating may be selectively patterned by doping to create electrically conductive areas that can be used as an electrically activated release mechanism for drug delivery. The UNCD coating provides a conformal coating, of approximately uniform thickness, around sharp corners and on high aspect-ratio parts, assuring impermeability and strength despite the need to coat difficult shapes. The microfluidic delivery system is suitable for use as an iontophoresis device, for transport of molecule, having a substrate, a reservoir in the substrate for containing the molecules.
    Type: Grant
    Filed: March 11, 2002
    Date of Patent: August 29, 2006
    Assignee: Second Sight Medical Products, Inc.
    Inventors: Robert J. Greenberg, Brian V. Mech
  • Patent number: 6866791
    Abstract: The process of derivatization and patterning of surfaces, and more particularly to the formation of self-assembled molecular monolayers on metal oxide surfaces using microcontact printing and the derivative articles produced thereby.
    Type: Grant
    Filed: May 2, 2000
    Date of Patent: March 15, 2005
    Assignee: International Business Machines Corporation
    Inventors: Tricia L. Breen, Peter M. Fryer, Robert L. Wisnieff, John Christopher Flake
  • Patent number: 6773614
    Abstract: Electrically conductive film, used for electroluminescent displays and electroplated films, treated by printing with ink on the surface of the film, the ink causing activation of the film wherever printing occurs.
    Type: Grant
    Filed: April 16, 2002
    Date of Patent: August 10, 2004
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Marshall Field
  • Patent number: 6750152
    Abstract: A semiconductor wafer is etched to create an array of MEMS devices and at the same time, test sites having geometry which represent critical geometry of the MEMS devices. Probe contacts are provided in the test sites to permit measurement of resistance and capacitance between test site geometry as a way of determining the effectiveness of the etch. One test site comprises a ladder of semiconductor structures separated by gaps of graded width. Another test site comprises finger structures formed over a cavity and the probe contacts are located so as to detect inter-finger capacitance and resistance (or continuity) as well as intra-finger resistance.
    Type: Grant
    Filed: October 1, 1999
    Date of Patent: June 15, 2004
    Assignee: Delphi Technologies, Inc.
    Inventors: John Carl Christenson, Steven Edward Staller, John Emmett Freeman, Troy Allan Chase, Robert Lawrence Healton
  • Patent number: 6734104
    Abstract: Over a plug, a stopper insulating film made of an organic film is formed, followed by successive formation of an insulating film and a hard mask. In the presence of a patterned resist film, the hard mask is dry etched, whereby an interconnection groove pattern is transferred thereto. By ashing with oxygen plasma, the resist film is removed to form the interconnection-groove-pattern-transferred hard mask. At this time, the organic film constituting the stopper insulating film has been covered with the insulating film. Then, the insulating film, stopper insulating film and hard mask are removed to form the groove pattern of interconnection. Hydrogen annealing may be conducted after formation of the plug, or the stopper insulating film may be formed over the plug via an adhesion layer.
    Type: Grant
    Filed: November 19, 2002
    Date of Patent: May 11, 2004
    Assignee: Renesas Technology Corporation
    Inventors: Kazusato Hara, Keisuke Funatsu, Toshinori Imai, Junji Noguchi, Naohumi Ohashi
  • Patent number: 6727186
    Abstract: A method of fabricating an SON structure semiconductor device is described. There is formed, on a silicon substrate, a stack of layers comprising first and second successive combinations. Each successive combination has a bottom silicon-germanium alloy (Site) layer and a top silicon layer. In a conventional way, a gate dielectric layer, a gate, spacers, source and drain regions, and an external passivating layer are formed by ionic implantation. A vertical hole is formed in the gate as far as the bottom Site layer to etch a part of the Site layers to form tunnels. The walls of the hole and the tunnels are then internally passivated so that the tunnels can remain empty or be filled.
    Type: Grant
    Filed: April 15, 2002
    Date of Patent: April 27, 2004
    Assignee: France Télécom
    Inventors: Thomas Skotnicki, Malgorzata Jurczak
  • Patent number: 6726848
    Abstract: In a method for treating a semiconductor substrate, a single substrate is positioned in a single-substrate process chamber and subjected to wet etching, cleaning and/or drying steps. The single substrate may be exposed to etch or clean chemistry in the single-substrate processing chamber as turbulence is induced in the etch or clean chemistry to thin the boundary layer of fluid attached to the substrate. Megasonic energy and/or disturbances in the chamber surfaces may provide the turbulence for boundary layer thinning. According to another aspect of a method according to the present invention, megasonic energy may be directed into a region within the single-substrate process chamber to create a zone of boundary layer thinning across the substrate surface, and a single substrate may be translated through the zone during a rinsing or cleaning process within the chamber to optimize cleaning/rinsing performance within the zone.
    Type: Grant
    Filed: December 7, 2001
    Date of Patent: April 27, 2004
    Assignee: SCP Global Technologies, Inc.
    Inventors: Eric Hansen, Victor Mimken, Martin Bleck, M. Rao Yalamanchili, John Rosato
  • Patent number: 6713401
    Abstract: Disclosed is a method for manufacturing a semiconductor device which efficiently carries out a process on a semiconductor substrate, such as dry etching, and cleaning for removing a foreign matter after the process. The method includes a step of removing a foreign matter by using both an electric action of a plasma generated by plasma generation means and a physical action caused by a frictional stress of a fast gas stream formed by a pad structure which is arranged close to a wafer surface.
    Type: Grant
    Filed: August 28, 2001
    Date of Patent: March 30, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Kenetsu Yokogawa, Yoshinori Momonoi, Kazunori Tsujimoto, Shinichi Tachi
  • Patent number: 6706203
    Abstract: An adjustable nanopore is fabricated by placing the surfaces of two planar substrates in contact, wherein each substrate contains a hole having sharp corners and edges. A corner is brought into proximity with an edge to define a triangular aperture of variable area. Ionic current in a liquid solution and through the aperture is monitored as the area of the aperture is adjusted by moving one planar substrate with respect to the other along two directional axes and a rotational axis. Piezoelectric positioners can provide subnanometer repeatability in the adjustment process. The invention is useful for characterizing, cleaving, and capturing molecules, molecular complexes, and supramolecular complexes which pass through the nanopore, and provides an improvement over previous devices in which the hole size of nanopores fabricated by etching and/or redeposition is fixed after fabrication.
    Type: Grant
    Filed: October 30, 2001
    Date of Patent: March 16, 2004
    Assignee: Agilent Technologies, Inc.
    Inventors: Philip W. Barth, Daniel B. Roitman, Joel Myerson
  • Patent number: 6706204
    Abstract: A method of fabricating nanosized holes with controlled geometries employs tools and methods developed in the microelectronics industry. The method exploits the fact that epitaxially grown film thicknesses can be controlled within a few atomic monolayers and that by using etching techniques, trenches and channels can be created that are only a few nanometers wide. The method involves bonding two shallow channels at an angle such that a nanopore is defined by the intersection. Thus, a nanopore-defining device includes a nanopore with dimensions that are determined by the dimensions and orientations of the intersecting channels, with the dimensions being accurately controlled within a few monolayers.
    Type: Grant
    Filed: December 19, 2001
    Date of Patent: March 16, 2004
    Assignee: Agilent Technologies, Inc.
    Inventors: Daniel B. Roitman, Dietrich W. Vook, Theodore I. Kamins
  • Patent number: 6693034
    Abstract: A method of manufacturing semiconductor devices using an improved planarization process for the planarization of the surfaces of the wafer on which the semiconductor devices are formed. The improved planarization process includes the formation of a flat planar surface from a deformable coating on the surface of the wafer using a fixed flexible planar interface material contacting the deformable material.
    Type: Grant
    Filed: August 27, 2002
    Date of Patent: February 17, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Guy T. Blalock, Hugh E. Stroupe, Brian F. Gordon
  • Patent number: 6693045
    Abstract: A gradational etching method for high density wafer production. The gradational etching method acts on a substrate having a first passivation layer and a second passivation layer on a top surface and a bottom surface, respectively, of the substrate. A first etching process is performed to simultaneously etch the substrate and the first passivation layer to remove the first passivation layer. Finally, a second etching process is performed to etch the substrate to a designated depth that is used to control the thickness of the wafer after the second etching process.
    Type: Grant
    Filed: February 4, 2002
    Date of Patent: February 17, 2004
    Assignee: BenQ Corporation
    Inventors: Tsung-Ping Hsu, In-Yao Lee, Hung-Sheng Hu, Chung-Cheng Chou, Wei-Lin Chen
  • Patent number: 6686284
    Abstract: A chemical mechanical polishing apparatus that is equipped with a chilled retaining ring and a method for using the apparatus are described. The retaining ring is mounted therein a heat transfer means such as a metal tube and flowing therethrough a heat exchanging fluid for carrying away heat from the wafer mounted in the retaining ring, resulting in a temperature reduction in the slurry solution that contacts the wafer. The present invention apparatus and method therefore reduces the delamination problem for low k dielectric materials during polishing and the wafer scratching problem.
    Type: Grant
    Filed: February 6, 2002
    Date of Patent: February 3, 2004
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd
    Inventors: Chi-Wei Chung, Tung-Ching Tseng, Tsu Shih, Syun-Ming Jang
  • Patent number: 6683004
    Abstract: There is described prevention of an increase in the thickness of an oxide film of a silicon wafer, which would otherwise be caused by eruption of gas from a CVD oxide film of another wafer during the course of a high-temperature annealing operation. A semiconductor device, which has a silicon substrate and trench isolation structures for isolating a plurality of active regions from one another, is manufactured by the steps as follows. A first and a second dielectric films are formed on the silicon substrate of one of the conductivity types. The dielectric films are removed from the areas of the silicon substrate where the trench structures are to be formed. The trench structures are formed in the uncovered areas of the silicon substrate to a predetermined depth. An oxide film is deposited into the respective trench structures by means of CVD after the oxide film has been deposited on the interior surface of the respective trench structure.
    Type: Grant
    Filed: July 11, 2000
    Date of Patent: January 27, 2004
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Masao Inoue, Akinobu Teramoto, Hiroshi Umeda
  • Patent number: 6683009
    Abstract: A method is described for local etching of surfaces. The method includes the steps of providing a surface, providing an etchant, and providing a device for supplying and extracting the etchant. The device contains two cylindrical lines of different cross-sectional areas, of which the cylindrical line with the smaller cross-sectional area is guided inside the cylindrical line with the larger cross-sectional area. An etchant is fed through the inner line to the region of the semiconductor wafer that is to be etched, and the etchant that spreads out beyond the region of the surface that is to be etched is extracted through the outer line. The cross-sectional area of the outer line is less than or equal to the area of the region of the surface which is to be etched.
    Type: Grant
    Filed: October 26, 2001
    Date of Patent: January 27, 2004
    Assignee: Infineon Technologies AG
    Inventors: Frank Adler, Guido Angenendt
  • Patent number: 6683003
    Abstract: An apparatus for performing a global planarization of a surface of a deformable layer of a wafer on a production scale. The apparatus includes a chamber having a pressing surface and containing a rigid plate and a flexible pressing member or “puck” disposed between the rigid plate and the pressing surface. A wafer having a deformable outermost layer is placed on the flexible pressing member so the deformable layer of the wafer is directly opposite and substantially parallel to the pressing surface. Force is applied to the rigid plate which propagates through the flexible pressing member to press the deformable layer of the wafer against the pressing surface. Preferably, a bellows arrangement is used to ensure a uniformly applied force to the rigid plate. The flexible puck serves to provide a self adjusting mode of uniformly distributing the applied force to the wafer, ensuring the formation of a high quality planar surface.
    Type: Grant
    Filed: April 23, 2001
    Date of Patent: January 27, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Guy Blalock
  • Patent number: 6679998
    Abstract: A method of forming a pattern in a layer of material on a substrate, comprising providing a plurality of spheres, covering the layer on the substrate with the plurality of spheres to form a mask, reducing the diameter of at least one sphere of the plurality of spheres, etching the layer on the substrate using at least one sphere having a reduced diameter as a mask, and etching the substrate.
    Type: Grant
    Filed: August 23, 2002
    Date of Patent: January 20, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Eric J. Knappenberger, Aaron R. Wilson
  • Patent number: 6677239
    Abstract: Methods and apparatus are provided for planarizing substrate surfaces with selective removal rates and low dishing. One aspect of the method provides for processing a substrate including providing a substrate to a polishing platen having polishing media disposed thereon, providing an abrasive free polishing composition comprising one or more surfactants to the substrate surface to modify the removal rates of the at least the first dielectric material and the second dielectric material, polishing the substrate surface, and removing the second material at a higher removal rate than the first material from a substrate surface. One aspect of the apparatus provides a system for processing substrates including a platen adapted for polishing the substrate with polishing media and a computer based controller configured to perform one aspect of the method.
    Type: Grant
    Filed: August 24, 2001
    Date of Patent: January 13, 2004
    Assignee: Applied Materials Inc.
    Inventors: Wei-Yung Hsu, Gopalakrishna B. Prabhu, Lizhong Sun, Daniel A. Carl
  • Patent number: 6677248
    Abstract: Disclosed is a coaxial type signal line that solves problems associated with signal interference and the connection of signal lines that are generated in a radio frequency (RF) electrical system. A method for manufacturing the coaxial type signal line includes the steps of forming a groove on a substrate, forming a first ground line on a surface of the groove and a plain surface of the substrate, forming a first dielectric layer including dielectric material on the first ground line formed on the surface of the groove, forming a signal line on the first dielectric layer the signal line for transmitting signals, forming a second dielectric layer including dielectric material on the signal line and the first dielectric layer, and forming a second ground line on the first ground line and the second dielectric layer.
    Type: Grant
    Filed: November 8, 2001
    Date of Patent: January 13, 2004
    Assignee: Dynamic Solutions International, Inc.
    Inventors: Young-Se Kwon, In-Ho Jeong
  • Patent number: 6677247
    Abstract: A method of forming a contact in an integrated circuit between a first metalization layer and a silicon substrate. In one embodiment the method comprises forming a premetal dielectric layer over the silicon substrate, etching a contact hole through the premetal dielectric layer and then forming a thin silicon nitride layer on an outer surface of the contact hole. The silicon nitride layer reduces overetching that may otherwise occur when oxidation build-up is removed from the silicon interface within the contact hole by a preclean process. After the preclean process, the contact hole is then filled with one or more conductive materials. In various embodiments the silicon nitride layer is formed by exposing the contact hole to a nitrogen plasma, depositing the layer by a chemical vapor deposition process and depositing the layer by an atomic layer deposition process. In other embodiments, the method is applicable to the formation of vias through intermetal dielectric layers.
    Type: Grant
    Filed: January 7, 2002
    Date of Patent: January 13, 2004
    Assignee: Applied Materials Inc.
    Inventors: Zheng Yuan, Steve Ghanayem, Randhir P. S. Thakur