Abstract: The present invention relates to a method of etching tungsten or tungsten nitride in semiconductor structures. We have discovered a method of etching tungsten or tungsten nitride which permits precise etch profile control while providing a rapid etch rate. In particular, the method employs the use of a plasma source gas where the chemically functional etchant species are generated from a combination of sulfur hexafluoride (SF6) and nitrogen (N2), where the sulfur hexafluoride and nitrogen are provided in a volumetric flow rate ratio within the range of about 1:2.5 to about 6:1.
Abstract: A method for forming an isolation region on a semiconductor substrate with a high yield, comprising partially covering the surface of a semiconductor substrate with an oxidation inhibitor film, depositing a material for side-wall parts on the oxidation inhibitor film and also on an exposed region of the surface, which is revealed through an opening of the oxidation inhibitor film, to form side-wall parts at the edge portions of the oxidation inhibitor film, then, removing by a plasma etching process the unnecessary portions of said side-wall material deposited on the oxidation inhibitor film and on the exposed region of the substrate and leaving intact the side-wall parts at the edge portions of the oxidation inhibitor film, and cleaning the exposed region on the surface of the semiconductor substrate, revealed through the opening of the oxidation inhibitor film, before subsequent heat treatment to generate a field oxide film.
Abstract: Fixtures and methods for clamping workpieces in a workplace to enable the optimized exposure thereof to a stream or flow of a supercritical fluid. Provided is a rotatably indexable chuck or locator mounting the workpiece and enabling orientating the latter in specific static pitch position within a high pressure vessel in order to subject the workpiece to a full frontal exposure to the supercritical fluid stream within the vessel. This mounting arrangement facilitates an optimum positioning of the workpiece being processed in the flow path of the supercritical fluid stream while oriented in selectively indexed rotational positions.
Type:
Grant
Filed:
July 12, 2001
Date of Patent:
June 17, 2003
Assignee:
International Business Machines Corporation
Inventors:
John Michael Cotte, Matteo Flotta, Kenneth John McCullough, Wayne Martin Moreau, John P. Simons, Charles J. Taft
Abstract: A method and apparatus for planarizing a microelectronic substrate. In one embodiment, the microelectronic substrate is engaged with a planarizing medium that includes a planarizing pad and a planarizing liquid, at least one of which includes a chemical agent that removes a corrosion-inhibiting agent from discrete elements (such as abrasive particles) of the planarizing medium and/or impedes the corrosion-inhibiting agent from coupling to the discrete elements. The chemical agent can act directly on the corrosion-inhibiting agent or can first react with a constituent of the planarizing liquid to form an altered chemical agent, which then interacts with the corrosion-inhibiting agent. Alternatively, the altered chemical agent can control other aspects of the manner by which material is removed from the microelectronic substrate, for example, the material removal rate.
Abstract: A sheet including lead regions with conductors and a main region surrounding the lead regions is formed on the front surface of a microelectronic element such as a wafer, or assembled thereto, so that the conductors are connected to contacts on the microelectronic element. After the sheet is in place, the sheet is eroded to form gaps partially bounding the lead regions, leaving tip ends of the lead regions moveable with respect to the main region. The tip ends of the lead regions, or the main region, is lifted away from the microelectronic element, thus bending the tip ends away from the main region. Because the gaps are not formed until after the conductors are connected to the contacts, the connecting step is simplified.
Abstract: A dry etching apparatus and method which can uniformly and stably generate a high-density plasma over a wide range, and can cope with increase of wafer diameter and making the pattern finer in etch processing of the fine pattern of a semiconductor device. The apparatus and method enables a magnitude of a magnetic field to be cyclically modulated when a substrate to be treated is etch processed. The cyclical modulation may be effected by cyclically modulating a coil current flowing to a solenoid coil.
Abstract: A new method to prevent oxide erosion in a metal plug process by employing a silicon nitride layer over the oxide is described. An oxide layer is deposited overlying a semiconductor substrate. A silicon nitride layer is deposited overlying the oxide layer. An opening is etched through the silicon nitride layer and into the oxide layer. A barrier metal layer is deposited overlying the silicon nitride layer and into the opening. A metal layer is deposited overlying the barrier metal layer. The metal layer and barrier metal layer are polished away using chemical mechanical polishing (CMP) with a polish stop at the silicon nitride layer. The metal layer forms a metal plug. The silicon nitride layer prevents erosion of the oxide layer during the polishing step to complete formation of a metal plug in the fabrication of an integrated circuit device.
Abstract: A method of improving plasma processing of a semiconductor wafer by exposing the wafer or the plasma to photons while the wafer is being processed. One embodiment of the method comprises the steps of etching an aluminum layer and, during the etching, exposing the semiconductor wafer containing the aluminum layer to photons that photodesorb copper chloride from the surface of the layer thus improving the etch process performance.
Type:
Grant
Filed:
February 17, 2000
Date of Patent:
May 27, 2003
Assignee:
Applied Materials, Inc.
Inventors:
Peter K. Loewenhardt, John M. Yamartino, Hui Chen, Diana Xiaobing Ma
Abstract: Method for fabricating a structure. According to an exemplary embodiment, a structure is made by forming a layer of removable material with a first surface spaced a part from a second surface. The first surface is formed along a first region from which the material is removable. The first surface is altered by removal of material from the layer. Removed material from the first surface is monitored to detect fluctuations in a variable of composition in the layer, and removal of material from the first surface is terminated when the composition of monitored material meets a predetermined criterion. In an alternate embodiment a variable characteristic is imparted to a layer of material as a function of layer thickness and an operation is performed on the layer resulting in removal of material. Samples of removed material are monitored for variation in the characteristic and the operation is modified when a variation conforms with a criterion.
Type:
Grant
Filed:
August 31, 2000
Date of Patent:
May 27, 2003
Assignee:
Agere Systems Guardian Corp
Inventors:
Erik Cho Houge, Isik C. Kizilyalli, John Martin McIntosh, Fred Anthony Stevie, Catherine Vartuli
Abstract: Molded products may be made by a process comprising preparing a structure comprising a block copolymer or a graft copolymer having two or more phases, wherein each phase is comprised of polymer chains, decomposing the polymer chains of at least one phase of the structure, and cleaning the structure with a supercritical fluid or a sub-critical fluid, thereby removing the decomposed polymer chains from the structure. Molded products made by this method have very low levels of residual solvents, can be manufactured at a relatively low temperature in a short period of time without using large amounts of organic solvents, and without discharging large amounts of liquid waste.
Type:
Grant
Filed:
August 13, 2001
Date of Patent:
May 20, 2003
Assignee:
Kabushiki Kaisha Toshiba
Inventors:
Toshiro Hiraoka, Koji Asakawa, Yasuyuki Hotta
Abstract: A method and apparatus for dry etching changes at least one of the effective pumping speed of a vacuum chamber and the gas flow rate to alter the processing of an etching pattern side wall of a sample between first and second conditions. The first and second conditions include the presence or absence of a deposit film, or the presence, absence or shape of a taper angle. Various parameters for controlling the first and second conditions are contemplated.
Abstract: A resist mark for measuring the accuracy of overlay of a photomask disposed on a semiconductor wafer, includes a first measurement mark having a first opening, formed on the substrate, an intermediate layer formed on the first measurement mark and in the first opening, a frame-shaped second measurement mark formed on the intermediate layer, and a third measurement mark that is spaced from the second measurement mark toward the outside, formed on the intermediate layer. The second measurement mark has a width which is short enough not to be influenced by a deformation caused by the thermal flow phenomenon.
Abstract: Within a dual damascene method for forming a dual damascene aperture within a microelectronic fabrication there is employed a first etch stop layer formed of a first material and a second etch stop layer formed of a second material. One of the first material and the second material is a non-nitrogenated silicon carbide material and the other of the first material and the second material is a nitrogenated silicon carbide material. By employing the first material and the second material, there may be etched completely through the first etch stop layer to reach a contact region formed there beneath while not etching completely through the second etch stop layer to reach a first dielectric layer formed there beneath.
Abstract: A method for the fabrication of electrical contacts using metal forming, masking, etching, and soldering techniques is presented. The method produces a plurality of specialized electrical contacts, capable of use in an interposer, or other device, including non-permanent or permanent electrical connections providing contact wipe, soft spring rates, durability, and significant amounts of travel.
Abstract: The present invention provides a method of manufacturing a MOS transistor of an embedded memory. The method of the present invention involves first defining a memory array area and a periphery circuit region on the surface of the semiconductor wafer and to deposit a gate oxide layer, an undoped polysilicon layer and a dielectric layer, respectively. Next, the undoped polysilicon layer in the memory array area is implanted to form a doped polysilicon layer followed by the removal of the dielectric layer in the memory array area. Thereafter, a metallic silicide layer and a passivation layer are formed, respectively, on the surface of the semiconductor wafer. The passivation layer, the metallic silicide layer and the doped polysilicon layer are then etched to form a plurality of gates in the memory array area. Next, the passivation layer, the metallic silicide layer and the dielectric layer in the periphery circuit region are removed.
Abstract: A wafer handling wand allows the efficient loading and unloading of semiconductor wafers to and from a CMP apparatus. The wand includes identical work piece gripping, alignment, and loading/unloading mechanisms on the top and bottom sides. A processed wafer can be unloaded from the apparatus onto one side of the wand and an unprocessed wafer can be loaded into the apparatus from the second side. The gripping mechanism includes a support area and a spaced apart moveable gripping finger. Wafer loading is facilitated by a cam attached to the support area that rotates when the cam contacts the apparatus. Upon rotation, the cam provides a surface for directing the work piece into the apparatus. The surface of the cam also includes an alignment aid that can be brought into contact with a reference surface on the apparatus to insure proper alignment between the wand and the apparatus.
Type:
Grant
Filed:
September 7, 2001
Date of Patent:
May 6, 2003
Assignee:
Speedfam-IPEC Corporation
Inventors:
Daniel S. Mallery, Doug Kreager, Chris E. Barns
Abstract: A resist mark for measuring the accuracy of overlay of a photomask disposed on a semiconductor wafer, includes a first measurement mark having a first opening, formed on the substrate, an intermediate layer formed on the first measurement mark and in the first opening, a frame-shaped second measurement mark formed on the intermediate layer, and a third measurement mark that is spaced from the second measurement mark toward the outside, formed on the intermediate layer. The second measurement mark has a width which is short enough not to be influenced by a deformation caused by the thermal flow phenomenon.
Abstract: A method of manufacturing a fluidic channel through a substrate includes etching an exposed section on a first surface of the substrate, and coating the etched section of the substrate. The etching and the coating are alternatingly repeated until the fluidic channel is formed.
Type:
Grant
Filed:
July 31, 2001
Date of Patent:
April 29, 2003
Assignee:
Hewlett-Packard Development Company, L.P.
Inventors:
Donald J Milligan, Tim R Koch, Martha A Truninger, Diane W Lai, Timothy R Emery, J. Daniel Smith
Abstract: Silicon carbide is used for a hardmask for the isolation dielectric etch and also serves as an etch stop for chemical-mechanical polishing. Alternatively, silicon carbonitride or silicon carboxide can be used.
Type:
Grant
Filed:
December 21, 1998
Date of Patent:
April 29, 2003
Assignee:
Texas Instruments Incorporated
Inventors:
Leif C. Olsen, Leland S. Swanson, Henry L. Edwards
Abstract: A method of using a finishing element having an abrasive finishing surface including organic lubricant for finishing semiconductor wafers is described. The organic lubricants with preferred in situ control can improve control of the coefficient of friction and help reduce unwanted defects. The method uses finishing control subsystem having a multiplicity of operative process sensors along with tracked information to improve in situ control of finishing. Differential lubricating film methods are described to differentially finish semiconductor wafers. Planarization and localized finishing can be improved using differential lubricating boundary layer methods of finishing with improved real time control.