Abstract: A method of integrating a chip with a topside active optical chip is described. The topside active optical chip has at least one optical laser device, having an active side including an optically active region, a laser cavity having a height, an optically inactive region, a bonding side opposite the active side, and a device thickness. The method involves bonding the optical chip to the electronic chip; applying a substrate to the active side, the substrate having a substrate thickness over the active region in the range of between a first amount and a second amount, and applying an anti-reflection without a special patterning or distinguishing between the at least one optical laser device and any other device. A hybrid electro-optical chip is also described as having an electronic chip; and a topside active optical chip. The hybrid electro-optical chip having been created by one of the methods herein. A module is also described.

Abstract: Methods for transferring a layer of material from a source substrate having a zone of weakness onto a support substrate to fabricate a composite substrate are described. An implementation includes forming at least one recess in at least one of the source and support substrates, depositing material onto at least one of a front face of the source substrate and a front face of the support substrate, pressing the front faces of the source and support substrates together to bond the substrates, and detaching a transfer layer from the source substrate along the zone of weakness. When the front faces are pressed together, any excess material is received by the recess. The recess may advantageously include an opening in the front face of at least one of the source substrate and the support substrate.

Abstract: A P channel vertical conduction Rad Hard MOSFET has a plurality of closely spaced base strips which have respective sources to form invertible surface channels with the opposite sides of each of the stripes. A non-DMOS late gate oxide and overlying conductive polysilicon gate are formed after the source and base regions have been diffused. The base stripes are spaced by about 0.6 microns, and the polysilicon gate stripes are about 3.2 microns wide. A P type enhancement region is implanted through spaced narrow windows early in the process and are located in the JFET common conduction region which is later formed by and between the spaced base stripes. The device is a high voltage (greater than 25 volts) P channel device with very low gate capacitance and very low on resistance.

Abstract: A thin film transistor array substrate includes a substrate, a gate wire with a gate line and a gate electrode formed on the substrate, a gate insulating layer covering the gate wire, and a semiconductor pattern formed on the gate insulating layer. A data wire is formed on the gate insulating layer and the semiconductor pattern with a data line, and a source electrode and a drain electrode. The data wire bears a multiple-layered structure having a metallic layer and an intermetallic compound layer. A protective layer is formed on the data wire and the semiconductor pattern. A pixel electrode is formed on the protective layer while contacting the drain electrode through a contact hole.

Abstract: Structures and methods involve dynamic enhancement mode p-channel flash memories with ultrathin tunnel oxide thicknesses. Both write and erase operations are performed by tunneling. The p-channel flash memory cell with thin tunnel oxides will operate on a dynamic basis. The stored data can be refreshed every few seconds as necessary. However, the write and erase operations will now be orders of magnitude faster than traditional p-channel flash memory. Structures and methods for p-channel floating gate transistors are provided that avoid p-channel threshold voltage shifts and achieve source side tunneling erase. The p-channel memory cell structure includes a floating gate separated from a channel region by an oxide layer of less than 50 Angstroms. The methods further include reading the p-channel memory cell by applying a potential to a control gate of the p-channel memory cell of less than 1.0 Volt.

Abstract: Switching times of a thyristor-based semiconductor device are improved by enhancing carrier drainage from a buried thyristor-emitter region. According to an example embodiment of the present invention, a conductive contact extends to a doped well region buried in a substrate and is adapted to drain carriers therefrom. The device includes a thyristor body having at least one doped emitter region buried in the doped well region. A conductive thyristor control port is adapted to capacitively couple to the thyristor body and to control current flow therein. With this approach, the thyristor can be rapidly switched between resistance states, which has been found to be particularly useful in high-speed data latching implementations including but not limited to memory cell applications.

Abstract: A semiconductor device includes a semiconductor chip carrying a plurality of contact electrodes on a principal surface thereof, wherein the contact electrodes are arranged symmetrically about an axis of symmetry according to the types of the contact electrodes.

Abstract: A semiconductor device comprises a semiconductor substrate having a first insulator, and a semiconductor channel region formed on the first insulator, wherein the semiconductor channel region comprising at least two first regions both having the first conductivity type, a second region of the conductivity type opposite to the first conductivity type, the second region being provided between the two first regions, a second insulator formed on the second region, a gate electrode formed on the second insulator, a third region having the same conductivity type as that of the second region, the third region being electrically conductive to the second region, a third insulator formed on the third region, the third insulator having a width narrower than the widths of an isolation region for isolating the semiconductor formation region, and a fourth region of the same conductivity type as that of the third region, the fourth region being electrically conductive to the third region.

Abstract: A method for aligning existing layers formed prior to a new layer and the new layer in forming the new layer on a wafer 4, wherein a microscope 6 as a first measurement condition and a microscope 7 as a second measurement condition are used, and marks 4a and 4b formed in each of said existing layers are measured by switching the first and second conditions, and said existing layers and said new layer are aligned based on measurement of mark position of each of said existing layers, and the microscope 7 has a plurality of measurement conditions as optical characteristics, and the measurement conditions are switched.

Abstract: In a liquid crystal display device, a recessed portion is formed in a portion of a periphery of a lower frame, a columnar member is provided to the recessed portion, the columnar member is allowed to pass through a hole formed in a projecting portion which is provided on an optical sheet, and a side surface of a liquid crystal panel is brought into contact with the columnar member. The columnar member provided on the lower frame not only determines the position of the liquid crystal panel with respect to the lower frame, but also determines the position of the optical sheet with respect to the lower frame and firmly holds the optical sheet onto the lower frame, thus preventing the disengagement of the optical sheet from the lower frame.

Abstract: An alignment mark structure (22) for aligning a mask with prior formed features of in a circuit region when an opaque material layer (88) covers the alignment mark structure (22) is provided. The features of the alignment mark structure (22) are formed in an alignment mark region (20) concurrently while features for a circuit region having vertical gate transistors are being formed. There are no extra or added processing steps added for forming the alignment mark structure (22) because it is formed concurrently while forming features in the circuit region. The resulting alignment mark structure (22) has step features (62) so that the step features (62) can be seen after the opaque material layer (88) covers the alignment mark structure (22).

Abstract: Integrated circuits having multi-level wiring layouts designed to inhibit the capacitive-resistance effect, and a method for fabricating such integrated circuits, is described. The integrated circuits have at least two planes of wiring adjacent to each other and extending in the same direction. One embodiment may further include a larger than normal insulator material between planes of wiring extending in one direction and at least one plane of wiring extending in a second direction transverse to the first direction. Each of the wiring channels in a wiring plane may be offset relative to a respective wiring channel in the next adjacent wiring plane which extends in the same direction.

Abstract: A cholesteric liquid crystal (CLC) color filter substrate for reflective liquid crystal display devices comprises an alignment layer on a black substrate, a cholesteric liquid crystal (CLC) color filter on the alignment layer, the cholesteric liquid crystal (CLC) color filter including sub-color-filters red (R), green (G), and blue (B), and black matrices on boundaries of each of the sub-color filters R, G, and B. In addition, a cholesteric liquid crystal (CLC) color filter substrate for a reflective liquid crystal display devices comprises an alignment layer on a black substrate, a cholesteric liquid crystal (CLC) color filter on the alignment layer, the cholesteric liquid crystal (CLC) color filter including sub-color-filters R, G, and B, and boundaries of each of the sub-color filters R, G and B that reflect incident light having a long wavelength.

Abstract: In an aspect, an apparatus is provided that sets and reprograms the state of programmable devices. In an aspect, a method is provided such that an opening is formed through a dielectric exposing a contact formed on a substrate. The resistivity of the contact is modified by at least one of implanting ions into the contact, depositing a material on the contact, and treating the contact with plasma. In an aspect, a spacer is formed within the opening and programmable material is formed within the opening and on the modified contact. A conductor is formed on the programmable material and the contact transmits to a signal line.

Abstract: A method of integrating a chip with a topside active optical chip is described. The topside active optical chip has at least one optical laser device, having an active side including an optically active region, a laser cavity having a height, an optically inactive region, a bonding side opposite the active side, and a device thickness. The method involves bonding the optical chip to the electronic chip; applying a substrate to the active side, the substrate having a substrate thickness over the active region in the range of between a first amount and a second amount, and applying an anti-reflection without a special patterning or distinguishing between the at least one optical laser device and any other device. A hybrid electro-optical chip is also described as having an electronic chip; and a topside active optical chip. The hybrid electro-optical chip having been created by one of the methods herein. A module is also described.

Abstract: A method of making a micromechanical device including forming recesses (28) using two sacrificial layers (22 and 27). A first sacrificial layer (22) is formed over an input signal line (16) and an output signal line (17). A portion of the first sacrificial layer (22) is removed to form openings (26) over the input signal line (16) and the output signal line (17). A second sacrificial layer (27) is formed over the first sacrificial layer (22) and openings (26) to form recesses (28) over the openings (26). A conductive layer (32) is formed over the second sacrificial layer (27) and the recesses (28). The conductive layer (32) serves as a shorting bar of a cantilever beam structure that couples input signal line (16) to output signal line (17) during operation.

Abstract: A fluorine-containing organic film having a relative dielectric constant of 4 or less is deposited on a semiconductor substrate using a material gas containing fluorocarbon as a main component in a reactor chamber of a plasma processing apparatus. During the deposition of the fluorine-containing organic film, a scavenger gas for scavenging fluorine constituting the fluorocarbon is mixed in the material gas. The proportion of the mixed scavenger gas in the material gas is changed to adjust the mechanical strength and relative dielectric constant of the fluorine-containing organic film.

Abstract: A wafer supporting a semiconductor structure having a material gain function that would preferentially support an Fabry-Perot laser mode at an unwanted wavelength &lgr;2 is provided with a second-order dielectric grating located sufficiently remotely from the high intensity optical field of the quantum well and the waveguide layers to receive just enough transverse mode energy to provide feedback to reduce the gain at &lgr;2 and support oscillation at a desired wavelength &lgr;1. More particularly, by locating the grating in an unpumped area not requiring epitaxial overgrowth and so as to provide a gain discrimination factor &Dgr;g≈0.1 cm−1 at the desired wavelength &lgr;1, the fraction of power lost to transverse mode radiation can be held to about 1% which is sufficient to provide stabilizing feedback without sapping too much energy from the longitudinal beam.

Abstract: In order to fill in an isolation trench formed on a semiconductor substrate, the isolation trench is filled up to a predetermined middle position with a coating film first, and then an insulating film formed by a CVD method is deposited thereon. Additionally, the insulating film is polished by a CMP method, for example, so as to be ground. Thus, the isolation trench is filled with stacked films of the coating film and the insulating film. Further, an electrode pattern and a dummy pattern are formed on the semiconductor substrate, and the trench formed between these patterns is filled up to a predetermined middle position in its depth direction with the coating film. Then, a remaining depth portion of the trench is filled with the insulating film formed by a CVD method.

Abstract: There is provided a light emitting device including a TFT having a high driving capacity (on current) and high reliability in a driver circuit and a TFT in which an off current is reduced in a pixel portion. In manufacturing the TFTs, after the TFT having an LDD region is formed, a part of a gate electrode is etched to form the TFT having GOLD region. Thus, the TFTs having required functions can be easily formed in the driver circuit and the pixel portion, respectively, on the same substrate.