Abstract: A phase change memory (PCM) cell with a low deviation contact area between a heater and a phase change element is provided. The PCM cell comprises a bottom electrode, a dielectric layer, a heater, a phase change element, and a top electrode. The dielectric layer overlies the bottom electrode. The heater extends upward from the bottom electrode, through the dielectric layer. Further, the heater has a top surface that is substantially planar and that is spaced below a top surface of the dielectric layer. The phase change element overlies the dielectric layer and protrudes into the dielectric layer to contact with the top surface of the heater. Also provided is a method for manufacturing the PCM cell.

Abstract: A monolithically integrated multi-sensor (MIMS) is disclosed. A MIMs integrated circuit comprises a plurality of sensors. For example, the integrated circuit can comprise three or more sensors where each sensor measures a different parameter. The three or more sensors can share one or more layers to form each sensor structure. In one embodiment, the three or more sensors can comprise MEMs sensor structures. Examples of the sensors that can be formed on a MIMs integrated circuit are an inertial sensor, a pressure sensor, a tactile sensor, a humidity sensor, a temperature sensor, a microphone, a force sensor, a load sensor, a magnetic sensor, a flow sensor, a light sensor, an electric field sensor, an electrical impedance sensor, a galvanic skin response sensor, a chemical sensor, a gas sensor, a liquid sensor, a solids sensor, and a biological sensor.

Abstract: A quantum dot including a seed including a first semiconductor nanocrystal including a first Group II-VI compound, a quantum well surrounding the seed, the quantum well including a second semiconductor nanocrystal including a Group IIIA metal except aluminum and a Group V element, and a shell disposed on the quantum well, the shell including a third semiconductor nanocrystal including a second Group II-VI compound, wherein the quantum dot does not include cadmium, an energy bandgap of the second semiconductor nanocrystal is smaller than an energy bandgap of the first semiconductor nanocrystal and an energy bandgap of the third semiconductor nanocrystal, and an ultraviolet-visible (UV-Vis) absorption spectrum curve of the quantum dot does not have an inflection point within a wavelength range of about 450 nanometers (nm) to about 600 nm, and a quantum dot composite and a device including the same.

Abstract: A first semiconductor die includes first semiconductor devices located over a first substrate, first interconnect-level dielectric material layers embedding first metal interconnect structures and located on the first semiconductor devices, and a first pad-level dielectric layer located on the first interconnect-level dielectric material layers and embedding first bonding pads. Each of the first bonding pads includes a first proximal horizontal surface and at least one first distal horizontal surface that is more distal from the first substrate than the first proximal horizontal surface is from the first substrate and has a lesser total area than a total area of the first proximal horizontal surface. A second semiconductor die including second bonding pads that are embedded in a second pad-level dielectric layer can be bonded to a respective distal surface of the first bonding pads.

Abstract: A MTJ stack is deposited on a bottom electrode. A top electrode layer and hard mask are deposited on the MTJ stack. The top electrode layer not covered by the hard mask is etched. Thereafter, a first spacer layer is deposited over the patterned top electrode layer and the hard mask. The first spacer layer is etched away on horizontal surfaces leaving first spacers on sidewalls of the patterned top electrode layer. The free layer not covered by the hard mask and first spacers is etched. Thereafter, the steps of depositing a subsequent spacer layer over patterned previous layers, etching away the subsequent spacer layer on horizontal surfaces leaving subsequent spacers on sidewalls of the patterned previous layers, and thereafter etching a next layer not covered by the hard mask and subsequent spacers are repeated until all layers of the MTJ stack have been etched to complete the MTJ structure.

Abstract: A semiconductor package includes an integrated circuit formed on a semiconductor substrate. A stress buffer layer is provided on the integrated circuit. Further, a mold compound is provided on a surface of the stress buffer layer opposite the integrated circuit. The mold compound comprises a resin. The resin includes filler particles. The filler particles have multiple sizes with the largest of the particles having a size between 5 microns and 32 microns.

Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate and a plurality of memory decks stacked above the substrate. Each of the memory decks includes a gate electrode, a blocking layer on the gate electrode, a plurality of charge trapping layers on the blocking layer, a tunneling layer on the plurality of charge trapping layers, a channel layer on the tunneling layer, and an inter-deck dielectric layer on the channel layer. The plurality of charge trapping layers are discrete and disposed at different levels. A top surface of the inter-deck dielectric layer is nominally flat. The gate electrode of another one of the memory decks immediately above the memory deck is disposed on the top surface of the inter-deck dielectric layer.

Abstract: A 3D semiconductor device, the device including: a first level including first single crystal transistors; and a second level including second single crystal transistors, where the first level is overlaid by the second level, where a vertical distance from the first single crystal transistors to the second single crystal transistors is less than four microns, where the first level includes a plurality of processors, and where the second level includes a plurality of memory cells.

Abstract: A display apparatus includes: a thin-film transistor including a source electrode, a drain electrode, and a gate electrode; a data line in a layer different from the source electrode, the drain electrode, and the gate electrode, wherein the data line is configured to transmit a data signal; and a shield layer between the data line and a component of the thin-film transistor.

Abstract: Multi-station process chamber lids comprising a plurality of station openings are described. A station separation purge channel is around the station openings. A plurality of angular purge channels separate station openings from adjacent station openings. A lid support beam can compensate for deflection of the chamber lid body.

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers comprising memory-block regions having channel-material strings therein. Conductor-material contacts are directly against the channel material of individual of the channel-material strings. First insulator material is formed directly above the conductor-material contacts. The first insulator material comprises at least one of (a) and (b), where (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide. Second insulator material is formed directly above the first insulator material and the conductor-material contacts. The second insulator material is devoid of each of the (a) and (b). Third insulator material is formed directly above the second insulator material, the first insulator material, and the conductor-material contacts. The third insulator material comprises at least one of the (a) and (b).

Abstract: A semiconductor device of an embodiment includes a semiconductor layer having a first plane, a second plane, and a through hole penetrating from the first plane to the second plane; an insulating layer on a side of the second plane of the semiconductor layer; a first conductive layer in the insulating layer; a silicon oxide layer on a side of the first plane and in the through hole; a silicon nitride layer provided on the side of the first plane and in the through hole, the silicon oxide layer being interposed between the silicon nitride layer and the semiconductor layer; and a second conductive layer on the side of the first plane and in the through hole, the silicon oxide layer and the silicon nitride layer being interposed between the second conductive layer and the semiconductor layer, and the second conductive layer electrically connected to the first conductive layer.

Abstract: A method for forming a gate structure of a 3D memory device is provided. The method comprises forming an array wafer including a periphery region and a staircase and array region. A process of forming an array wafer comprises forming an alternating dielectric etch stop structure on a first substrate in the periphery region, forming an array device on the first substrate in the staircase and array region, and forming at least one first vertical through contact in the periphery region and in contact with the alternating dielectric etch stop structure. The method further comprises forming a CMOS wafer and bonding the array wafer and the CMOS wafer. The method further comprises forming at least one through substrate contact penetrating the first substrate and the alternating dielectric etch stop structure, and in contact with the at least one first vertical through contact.

Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes an isolation structure disposed in a semiconductor substrate, where an inner perimeter of the isolation structure demarcates a device region of the semiconductor substrate. A gate is disposed over the device region, where an outer perimeter of the gate is disposed within the inner perimeter of the isolation structure. A first source/drain region is disposed in the device region and on a first side of the gate. A second source/drain region is disposed in the device region and on a second side of the gate opposite the first side. A silicide blocking structure partially covers the gate, partially covers the first source/drain region, and partially covers the isolation structure, where a first sidewall of the silicide blocking structure is disposed between first opposite sidewalls of the gate.

Abstract: A device includes a fin over a substrate, the fin including a first end and a second end, wherein the first end of the fin has a convex profile, an isolation region adjacent the fin, a gate structure along sidewalls of the fin and over the top surface of the fin, a gate spacer laterally adjacent the gate structure, and an epitaxial region adjacent the first end of the fin.

Abstract: A misregistration metrology system useful in manufacturing semiconductor device wafers including an optical misregistration metrology tool configured to measure misregistration at at least one target between two layers of a semiconductor device which is selected from a batch of semiconductor device wafers which are intended to be identical, an electron beam misregistration metrology tool configured to measure misregistration at the at least one target between two layers of a semiconductor device which is selected from the batch and a combiner operative to combine outputs of the optical misregistration metrology tool and the electron beam misregistration metrology tool to provide a combined misregistration metric.

Abstract: A texture recognition assembly, a method of manufacturing the same, and a display apparatus are disclosed. The texture recognition assembly includes a photosensitive sensing layer, a texture contact layer, and a filter film layer disposed at a side of the photosensitive sensing layer proximate to the texture contact layer. The filter film layer is configured to filter visible light with a wavelength greater than or equal to ?. A value of ? is greater than or equal to 600 nm.

Abstract: There is provided a method of manufacturing a device, which comprises: a preparation step of preparing a workpiece having a recess formed therein; a burying step of burying a sacrificial material composed of a thermally decomposable organic material in the recess; a lamination step of laminating a preliminary sealing film on the sacrificial material buried in the recess; a first removal step of removing the sacrificial material in the recess through the preliminary sealing film, by annealing the workpiece at a first temperature and thermally decomposing the sacrificial material; a processing step of performing a predetermined process on a portion other than the recess in the workpiece, in a state in which the recess is covered with the preliminary sealing film; and a second removal step of removing the preliminary sealing film.

Abstract: Semiconductor devices having one or more vias filled with a transparent and electrically conductive material are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die stacked over a second semiconductor die. The first semiconductor die can include at least one via that is axially aligned with a corresponding via of the second semiconductor die. The vias of the first and second semiconductor dies can be filled with a transparent and electrically conductive material that both electrically and optically couples the first and second semiconductor dies.

Abstract: A memory device includes a first electrode, a second electrode and a magnetic tunnel junction (MTJ) between the first electrode and the second electrode. The MTJ includes a fixed magnet, a free magnet and a tunnel barrier between the fixed magnet and the free magnet. The MTJ further includes a conductive layer between the free magnet and the second electrode, the conductive layer having a metallic dopant, where the metallic dopant has a concentration that increase with distance from an interface between the free magnet and the conductive layer. A capping layer is between the conductive layer and the second electrode.