Patents Examined by William Coleman
  • Patent number: 10847420
    Abstract: A wafer processing method includes a polyolefin sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyolefin sheet on a back side of the wafer and on a back side of the ring frame, a uniting step of heating the polyolefin sheet as applying a pressure to the polyolefin sheet to thereby unite the wafer and the ring frame through the polyolefin sheet by thermocompression bonding, a dividing step of cutting the wafer by using a cutting apparatus to thereby divide the wafer into individual device chips, and a pickup step of picking up each device chip from the polyolefin sheet.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: November 24, 2020
    Assignee: DISCO CORPORATION
    Inventors: Shigenori Harada, Minoru Matsuzawa, Hayato Kiuchi, Yoshiaki Yodo, Taro Arakawa, Masamitsu Agari, Emiko Kawamura, Yusuke Fujii, Toshiki Miyai, Makiko Ohmae
  • Patent number: 10847636
    Abstract: A method for forming a semiconductor structure is provided. The method includes the following operations. A substrate is received. The substrate includes a fin structure, a semiconductor layer over the fin structure, and a dielectric layer sandwiched between the fin structure and the semiconductor layer. The semiconductor layer is patterned to form a sacrificial gate layer over a portion of the fin structure. A first cleaning operation is performed with a HF solution. Spacers are formed over sidewalls of the sacrificial gate layer. Recesses are formed in the fin structure at two sides of the sacrificial gate layer. A second cleaning operation is performed with an HF-containing plasma.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: November 24, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chun Hsiung Tsai, Ru-Shang Hsiao, Clement Hsingjen Wann
  • Patent number: 10847486
    Abstract: A semiconductor die assembly in accordance with an embodiment of the present technology includes first and second semiconductor dies spaced apart from one another. The first semiconductor die has a major surface with non-overlapping first and second regions. The semiconductor die assembly further includes an array of first pillars extending heightwise from the first region of the major surface of the first semiconductor die toward the second semiconductor die. Similarly, the semiconductor die assembly includes an array of second pillars extending heightwise from the second region of the major surface of the first semiconductor die toward the second semiconductor die. The first and second pillars have different lateral densities and different average widths. The latter difference at least partially offsets an effect of the former difference on relative metal deposition rates of an electrochemical plating process used to form the first and second pillars.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: November 24, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Jonathan S. Hacker
  • Patent number: 10840131
    Abstract: Semiconductor devices and methods of forming semiconductor devices are provided. A method includes forming a first mask layer over a target layer, forming a plurality of spacers over the first mask layer, and forming a second mask layer over the plurality of spacers and patterning the second mask layer to form a first opening, where in a plan view a major axis of the opening extends in a direction that is perpendicular to a major axis of a spacer of the plurality of spacers. The method also includes depositing a sacrificial material in the opening, patterning the sacrificial material, etching the first mask layer using the plurality of spacers and the patterned sacrificial material, etching the target layer using the etched first mask layer to form second openings in the target layer, and filling the second openings in the target layer with a conductive material.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: November 17, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tai-Yen Peng, Wen-Yen Chen, Chih-Hao Chen
  • Patent number: 10840191
    Abstract: A film package includes a film substrate, a first semiconductor chip on a first surface of the film substrate, a second semiconductor chip on the first surface of the film substrate, and a first conductive film on the first surface of the film substrate. The first conductive film covers the first semiconductor chip and the second semiconductor chip and includes a slit(s) or a notch(es). The slit(s) or notch(es) is/are disposed in a bridge region between the first semiconductor chip and the second semiconductor chip, in a plan view of the package.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: November 17, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Min Jung, JiAh Min
  • Patent number: 10833089
    Abstract: An embodiment may include a method of forming an integrated circuit. The method may include forming a first pair of transistors stacked vertically above a semiconductor substrate arranged substantially perpendicular to the plurality of layers. Each of the first pair of vertically stacked transistors are of the same type and are connected in series. The method may include forming a second pair of transistors connected in parallel and arranged substantially perpendicular to the plurality of layers. The second pair of transistors are a different type than the first pair of vertically stacked transistors. The method may include forming a power supply rail within the semiconductor substrate and arranged at one end of the first pair of vertically stacked transistors.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Juergen Pille, Albert Frisch, Tobias Werner, Rolf Sautter, Dieter Wendel
  • Patent number: 10832976
    Abstract: In a semiconductor manufacturing process, it is necessary to cut a die close to the edge of a wafer in order to obtain as many dies as possible from one wafer. Accordingly, with respect to a charged particle beam device and an optical inspection device used in a semiconductor manufacturing process, there is a demand for detecting the height of the wafer close to the edge of the wafer with high accuracy, in order to measure or examine close to the edge of the wafer with high accuracy. Further, there is a demand for high speed height-detection in order to realize high throughput for the semiconductor manufacturing process. In the present invention, the foregoing can be achieved by the following configuration: sandwiching a target region on a wafer, a first pattern and a second pattern are projected onto one side and the other side respectively of the target region from an oblique direction with respect to the wafer top-surface, enabling an image of the first pattern and/or second pattern to be used.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: November 10, 2020
    Assignee: Hitachi High-Tech Corporation
    Inventor: Koichi Taniguchi
  • Patent number: 10833044
    Abstract: Apparatuses relating to a microelectronic package are disclosed. In one such apparatus, a substrate has first contacts on an upper surface thereof. A microelectronic die has a lower surface facing the upper surface of the substrate and having second contacts on an upper surface of the microelectronic die. Wire bonds have bases joined to the first contacts and have edge surfaces between the bases and corresponding end surfaces. A first portion of the wire bonds are interconnected between a first portion of the first contacts and the second contacts. The end surfaces of a second portion of the wire bonds are above the upper surface of the microelectronic die. A dielectric layer is above the upper surface of the substrate and between the wire bonds. The second portion of the wire bonds have uppermost portions thereof bent over to be parallel with an upper surface of the dielectric layer.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: November 10, 2020
    Assignee: Tessera, Inc.
    Inventors: Hiroaki Sato, Teck-Gyu Kang, Belgacem Haba, Philip R. Osborn, Wei-Shun Wang, Ellis Chau, Ilyas Mohammed, Norihito Masuda, Kazuo Sakuma, Kiyoaki Hashimoto, Kurosawa Inetaro, Tomoyuki Kikuchi
  • Patent number: 10825879
    Abstract: A pixel structure includes a substrate and a thin-film transistor having a first top surface and disposed above the substrate. The first top surface has a first projection area. A data line has a data line adjoining area connected to the thin-film transistor. A pixel electrode has a second top surface and disposed above the thin-film transistor. The second top surface has a second projection area that is greater than the first projection area. The second projection area has a first part and a second part; the first part corresponding to the first projection area is removed by at least 50%; and the second part corresponding to the data line adjoining area is at most 70% removed. The pixel structure omits an insulation layer under the pixel electrode to lower the cost of production and speed up the manufacturing process.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: November 3, 2020
    Assignee: HANNSTOUCH SOLUTION INCORPORATED
    Inventors: Ching-Feng Tsai, Che-Yu Chuang
  • Patent number: 10818872
    Abstract: The present invention provides an encapsulation thin-film, including a first inorganic layer composed of a first oxide; a polymer layer disposed on the first inorganic layer, and composed of a polymer bonded to the first oxide by a chemical bond; and a second inorganic layer disposed on the polymer layer, and bonded to the polymer by a chemical bond. The encapsulation thin-film and the display device according to the present invention, the first inorganic layer, the polymer layer and the second inorganic layer are bonded by a chemical bond, thus can prevent external water and oxygen corrosion and improve bending resistance of the display device.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: October 27, 2020
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Jiangjiang Jin, Hsianglun Hsu
  • Patent number: 10818670
    Abstract: A memory device and a method for manufacturing the memory device are provided. The memory device includes an interlayer insulating layer formed on a substrate, a conductive contact plug formed in the interlayer insulating layer, a conductive barrier structure formed on the conductive contact plug, and a capacitor structure formed on the conductive barrier structure. The area of the top surface of the conductive contact plug is smaller than the area of the bottom surface of the conductive barrier structure, and the top surface of the conductive contact plug is completely covered by the bottom surface of the conductive barrier structure.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: October 27, 2020
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Jiun-Sheng Yang, Noriaki Ikeda
  • Patent number: 10811356
    Abstract: Provided is an integrated circuit device including a plurality of word lines overlapping each other, in a vertical direction, on a substrate, a plurality of channel structures extending in the vertical direction through the plurality of word lines on an area of the substrate, a plurality of bit line contact pads on the plurality of channel structures, and a plurality of bit lines, wherein the plurality of bit lines include a plurality of first bit lines extending parallel to each other at a first pitch in a center region of the area, and a plurality of second bit lines extending at a second pitch in an edge region of the area, the second pitch being different from the first pitch.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: October 20, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-jin Jung, Joon-hee Lee
  • Patent number: 10797200
    Abstract: The invention relates to a method for manufacturing an optoelectronic device (1), comprising the following steps: a) providing a growth substrate (10) made from a semiconductor material; b) forming a plurality of diodes (20) each comprising a lower face (20i); c) removing at least a portion (12; 13) of the substrate so as to free the lower face (20i); wherein: step a) involves producing a lower part and an upper part of the substrate, the upper part (12) having a uniform thickness (eref) and a level of doping less than that of the lower part; step c) involving removal of the lower part (11) by selective chemical etching with respect to the upper part (12).
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: October 6, 2020
    Assignee: ALEDIA
    Inventor: Eric Pourquier
  • Patent number: 10790460
    Abstract: Disclosed herein is an organic light-emitting display device having a first flexible substrate; a second flexible substrate; a plurality of organic light-emitting pixels on the first flexible substrate and between the first flexible substrate and the second flexible substrate; an encapsulation unit covering the pixels; and an adhesive layer on the encapsulation unit. The Young's modulus of the adhesive layer is equal to or larger than a value so that the first flexible substrate is not deformed by bending stress when it is rolled up.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: September 29, 2020
    Assignee: LG Display Co., Ltd.
    Inventors: JooHwan Shin, BongChul Kim, Jaewook Park
  • Patent number: 10790138
    Abstract: There is provided a method for forming a target film on a substrate comprising: preparing the substrate having a first substrate region and a second substrate region that has at least two types of surfaces formed of materials different from a material of the first substrate region; selectively forming, on the surfaces of the second substrate region, an intermediate film capable of adsorbing a first self-assembled monolayer that inhibits formation of the target film on the second substrate region; selectively adsorbing the first self-assembled monolayer on a surface of the intermediate film; and selectively forming the target film on a surface of the first substrate region.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: September 29, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Shuji Azumo
  • Patent number: 10790444
    Abstract: A phase change memory (PCM) cell with a low deviation contact area between a heater and a phase change element is provided. The PCM cell comprises a bottom electrode, a dielectric layer, a heater, a phase change element, and a top electrode. The dielectric layer overlies the bottom electrode. The heater extends upward from the bottom electrode, through the dielectric layer. Further, the heater has a top surface that is substantially planar and that is spaced below a top surface of the dielectric layer. The phase change element overlies the dielectric layer and protrudes into the dielectric layer to contact with the top surface of the heater. Also provided is a method for manufacturing the PCM cell.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: September 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi Jen Tsai, Shih-Chang Liu
  • Patent number: 10784110
    Abstract: A tungsten film forming method in which a substrate having a TiN film formed thereon is disposed in a processing container and a tungsten film is formed above a surface of the substrate while heating the substrate in a reduced pressure atmosphere, includes forming a first film of an aluminum-containing material on the substrate and forming the tungsten film on the first film.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: September 22, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Takashi Sameshima, Koji Maekawa, Katsumasa Yamaguchi
  • Patent number: 10784329
    Abstract: A display apparatus includes: a thin-film transistor including a source electrode, a drain electrode, and a gate electrode; a data line in a layer different from the source electrode, the drain electrode, and the gate electrode, wherein the data line is configured to transmit a data signal; and a shield layer between the data line and a component of the thin-film transistor.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: September 22, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yangwan Kim, Wonkyu Kwak, Jaedu Noh, Jaeyong Lee
  • Patent number: 10777588
    Abstract: The present application provides a method of fabricating a thin film transistor. The method includes selecting a nano-structure material having a monotonic relationship between a threshold voltage and a channel length when the nano-structure material is formed as a channel part in a thin film transistor; forming an active layer using the nano-structure material; determining a nominal channel length of a channel part of the thin film transistor based on the monotonic relationship and a reference threshold voltage so that the thin film transistor is formed to have a nominal threshold voltage; and forming a source electrode and a drain electrode thereby forming the channel part in the active layer having the nominal channel length.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: September 15, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., PEKING UNIVERSITY
    Inventors: Hu Meng, Xuelei Liang, Jiye Xia, Boyuan Tian, Guodong Dong, Qi Huang
  • Patent number: 10777538
    Abstract: Embodiments include devices and methods, including a device including a substrate comprising a semiconductor, the substrate including a front side comprising active elements and a backside opposite the front side. The device includes a dielectric layer on the backside, and a passive component on the dielectric layer on the backside. In certain embodiments, the passive device is formed on a self-assembled monolayer (SAM). Other embodiments are described and claimed.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: September 15, 2020
    Assignee: INTEL CORPORATION
    Inventors: Fay Hua, Telesphor Kamgaing, Johanna M. Swan