Patents Examined by William Coleman
  • Patent number: 10475810
    Abstract: Some embodiments include a memory assembly having memory cells proximate a conductive source. Channel material extends along the memory cells and is electrically coupled with the conductive source. The conductive source is over an insulative material and includes an adhesion material directly against the insulative material. The adhesion material comprises one or more of metal, silicon nitride, silicon oxynitride, silicon carbide, metal silicide, metal carbide, metal oxide, metal oxynitride and metal nitride. The conductive source includes metal-containing material over and directly against the adhesion material. The metal-containing material consists essentially of metal. The conductive source includes a metal-and-nitrogen-containing material over and directly against the metal-containing material, and includes a conductively-doped semiconductor material over the metal-and-nitrogen-containing material.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: November 12, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Sudip Bandyopadhyay, Keen Wah Chow, Devesh Kumar Datta, Anurag Jindal, David Ross Economy, John Mark Meldrim
  • Patent number: 10457001
    Abstract: A method for forming a matrix composite layer on a workpiece and a workpiece with a matrix composite layer are disclosed. In an embodiment the method includes forming a wall around a metallic surface such that the wall extends in a vertical direction from a plane formed by the metallic surface, and depositing a filler material in a walled area on the metallic surface. The method further includes depositing a plastic material on the filler material and performing a vacuum treatment of the filler material and the plastic material thereby forming a matrix composite layer disposed on the metallic surface.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: October 29, 2019
    Assignee: Infineon Technologies AG
    Inventors: Jayaganasan Narayanasamy, Jagen Krishnan, Sanjay Kumar Murugan, Hong Lim Lee
  • Patent number: 10461244
    Abstract: A laminated structure according to an embodiment includes: a ferromagnetic layer; and a multiferroic layer formed on one surface of the ferromagnetic layer, wherein a surface of the multiferroic layer on the ferromagnetic layer side includes a first region, a crystalline phase of which is rhombohedral, and a second region, a crystalline phase of which is tetragonal.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: October 29, 2019
    Assignee: TDK CORPORATION
    Inventors: Eiji Suzuki, Katsuyuki Nakada
  • Patent number: 10461271
    Abstract: A light-emitting element with high emission efficiency which includes fluorescent materials is provided. The light-emitting element includes a first light-emitting layer and a second light-emitting layer. The first light-emitting layer includes a first fluorescent material and a first host material, and the second light-emitting layer includes a second fluorescent material and a second host material. The second host material includes a first organic compound and a second organic compound. The first organic compound and the second organic compound form an exciplex. A singlet excited energy level of the first host material is higher than a singlet excited energy level of the first fluorescent material, and a triplet excited energy level of the first host material is lower than a triplet excited energy level of the first fluorescent material.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: October 29, 2019
    Assignee: Semiconductor Energy Laboratories Co., Ltd.
    Inventors: Satoshi Seo, Takahiro Ishisone
  • Patent number: 10453885
    Abstract: The present disclosure relates to a solid-state imaging apparatus and an electronic device capable of reducing a product yield and reliability risk. By forming a contact by forming an opening in an insulating film on a back surface of a peripheral circuit region without connecting a light-shielding metal on the peripheral circuit region to the ground (GND), the light-shielding metal is connected to a Si substrate. Furthermore, a light-shielding metal on a pixel region is connected to the ground (GND). Therefore, by disposing an isolated region (insulating region) where no metal is formed between the light-shielding metal on the pixel region and the light-shielding metal on the peripheral circuit region, the light-shielding metal on the pixel region does not cause a short circuit with the light-shielding metal on the peripheral circuit region. The present disclosure can be applied to, for example, a CMOS solid-state imaging apparatus used for an imaging apparatus such as a camera.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: October 22, 2019
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Shin Iwabuchi, Kazuhiro Satou, Kensuke Motozono, Masatoshi Iwamoto
  • Patent number: 10453888
    Abstract: In a semiconductor apparatus including: a semiconductor substrate in which a plurality of semiconductor elements are provided; a first semiconductor layer which is overlapped on the semiconductor substrate and in which a plurality of photoelectric conversion elements are provided; a second semiconductor layer that is arranged between the semiconductor substrate and the first semiconductor layer; a first wiring structure that is arranged between the first semiconductor layer and the second semiconductor layer; a second wiring structure that is arranged between the second semiconductor layer and the semiconductor substrate; and a third wiring structure that is arranged between the second wiring structure and the semiconductor substrate, widths of a plurality of through electrodes are different from each other.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: October 22, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventor: Masahiro Kobayashi
  • Patent number: 10446414
    Abstract: A semiconductor package includes an integrated circuit formed on a semiconductor substrate. A stress buffer layer is provided on the integrated circuit. Further, a mold compound is provided on a surface of the stress buffer layer opposite the integrated circuit. The mold compound comprises a resin. The resin includes filler particles. The filler particles have multiple sizes with the largest of the particles having a size between 5 microns and 32 microns.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: October 15, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Amit Sureshkumar Nangia, Siva Prakash Gurrum, Janakiraman Seetharaman
  • Patent number: 10446481
    Abstract: A fan-out semiconductor package includes: an interconnection member including a first insulating layer, first and second pads respectively disposed on opposite sides of the first insulating layer and a first via connecting the first and second pads to each other; a semiconductor chip disposed on the interconnection member; and an encapsulant encapsulating at least portions of the semiconductor chip. A center line of the first via is out of alignment with at least one of a center line of the first pad and a center line of the second pad.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: October 15, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sun Ho Kim, Ji Hoon Kim, Ha Young Ahn, Shang Hoon Seo, Seung Yeop Kook, Sung Won Jeong
  • Patent number: 10446295
    Abstract: Provided is a thin-film chip resistor including an insulating substrate; a thin-film resistive element formed on the substrate; a pair of electrodes connected to the thin-film resistive element; and a protective film covering at least the thin-film resistive element between the pair of electrodes, in which the protective film includes a first protective film and a second protective film, the first protective film containing silicon nitride in contact with the thin-film resistive element, and the second protective film containing silicon oxide in contact with the first protective film.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: October 15, 2019
    Assignee: KOA CORPORATION
    Inventor: Yasushi Hiroshima
  • Patent number: 10446603
    Abstract: The present technology relates to an imaging element, a driving method of an imaging element, and an electronic device capable of preventing deterioration in image quality.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: October 15, 2019
    Assignee: SONY CORPORATION
    Inventors: Yoshihiro Ando, Fumihiko Koga
  • Patent number: 10439029
    Abstract: A field plate power device comprises: a substrate; a multilayer semiconductor layer disposed on the substrate; a source electrode, a drain electrode, and a gate electrode located between the source electrode and the drain electrode disposed on the multilayer semiconductor layer; a dielectric layer disposed on the gate electrode, a part of the multilayer semiconductor layer between the gate electrode and the source electrode and another part of the multilayer semiconductor layer between the gate electrode and the drain electrode; a groove disposed in a part of the dielectric layer between the gate electrode and the drain electrode; and a field plate disposed on the groove. The field plate comprises a first portion away from the gate electrode in a horizontal direction, and the first portion has an overall upward tilted shape in the horizontal direction away from the gate electrode.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: October 8, 2019
    Assignee: GPOWER SEMICONDUCTOR, INC.
    Inventors: Yuan Li, Yi Pei, Feihang Liu
  • Patent number: 10438962
    Abstract: Some embodiments include an assembly having a channel to conduct current. The channel includes a first channel portion and a second channel portion. A first memory cell structure is between a first gate and the first channel portion. The first memory cell structure includes a first charge-storage region and a first charge-blocking region. A second memory cell structure is between a second gate and the second channel portion. The second memory cell structure includes a second charge-storage region and a second charge-blocking region. The first and second charge-blocking regions include silicon oxynitride. A void is located between the first and second gates, and between the first and second memory cell structures. Some embodiments include memory arrays (e.g., NAND memory arrays), and some embodiments include methods of forming memory arrays.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: October 8, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Changhan Kim
  • Patent number: 10439015
    Abstract: A display apparatus includes: a thin-film transistor including a source electrode, a drain electrode, and a gate electrode; a data line in a layer different from the source electrode, the drain electrode, and the gate electrode, wherein the data line is configured to transmit a data signal; and a shield layer between the data line and a component of the thin-film transistor.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: October 8, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yangwan Kim, Wonkyu Kwak, Jaedu Noh, Jaeyong Lee
  • Patent number: 10429698
    Abstract: The present disclosure discloses a method for fabricating an array substrate, including: providing a base substrate which includes a transparent substrate, a data electrode pattern layer formed on the transparent substrate, and an insulation layer covering the data electrode pattern layer, the data electrode pattern layer comprising at least one data electrode; forming a via-hole penetrating through the insulation layer so as to expose at least a part of one of the at least one data electrode; forming a transparent electrode material layer; forming a transparent electrode layer which includes a transparent electrode and a connecting portion connected to the transparent electrode, the connecting portion being located in the via-hole so as to electrically connect the transparent electrode with a corresponding data electrode, and a filling being provided above the connecting portion. The present disclosure also discloses an array substrate and a display device.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: October 1, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Yanchun Lu, Jideng Zhou
  • Patent number: 10427937
    Abstract: A method for manufacturing a multi-layer MEMS component includes: providing a multi-layer substrate that has a monocrystalline carrier layer, a monocrystalline functional layer having a front side and a back side, and a bonding layer located between the back side and the carrier layer; growing a first polycrystalline layer over the front side of the monocrystalline functional layer; removing the monocrystalline carrier layer; and growing a second polycrystalline layer over the back side of the monocrystalline functional layer.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: October 1, 2019
    Assignee: Robert Bosch GmbH
    Inventors: Arnd Kaelberer, Christian Zielke, Hans Artmann, Oliver Breitschaedel, Peter Borwin Staffeld
  • Patent number: 10421123
    Abstract: A method for manufacturing a conductive film, the method comprising the steps of: preparing a mixture liquid in which a catalytic metal is dispersed in a precursor or a precursor compound of a two-dimensional nanomaterial; and forming a catalytic metal/two-dimensional nanomaterial by irradiating the mixture liquid with ultrasonic waves to generate microbubbles, degrading the precursor compound using energy, which is generated when the microbubbles burst, to synthesize the two-dimensional nanomaterial on an outer wall of the catalytic metal, wherein the method further comprises: dispersing the catalytic metal/two-dimensional nanomaterial in a dispersion to prepare ink; and applying the ink on a substrate and performing rapid air-sintering. Thus, the two-dimensional nanomaterial is synthesized on an outer wall of a non-noble metal having high oxidative characteristics, thereby preventing oxidation of the metal from air and increasing thermal conductivity and electrical conductivity.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: September 24, 2019
    Assignee: Korea Electrotechnology Research Institute
    Inventors: Hee Jin Jeong, Geon Woong Lee, Ho Young Kim, Kang Jun Baeg, Seung Yol Jeong, Joong Tark Han
  • Patent number: 10418413
    Abstract: A method for manufacturing a light emitting diode (LED) display includes providing a template having keyed holes disposed in the template, depositing keyed LED's onto the template manipulating the keyed LED's such that each of the keyed LED's fits within a corresponding keyed hole in the template, and transferring the keyed LED's onto a circuit board.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: September 17, 2019
    Assignee: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventors: Susan C. Ellis, Jarvis Chau
  • Patent number: 10418415
    Abstract: Approaches for an interconnect cladding process for integrating magnetic random access memory (MRAM) devices, and the resulting structures, are described. In an example, a memory structure includes an interconnect disposed in a trench of a dielectric layer above a substrate, the interconnect including a diffusion barrier layer disposed at a bottom of and along sidewalls of the trench to an uppermost surface of the dielectric layer, a conductive fill layer disposed on the diffusion barrier layer and recessed below the uppermost surface of the dielectric layer and an uppermost surface of the diffusion barrier layer, and a conductive capping layer disposed on the conductive fill layer and between sidewall portions of the diffusion barrier layer. A memory element is disposed on the conductive capping layer of the interconnect.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: September 17, 2019
    Assignee: Intel Corporation
    Inventors: Christopher J. Wiegand, Oleg Golonzka, MD Tofizur Rahman, Brian S. Doyle, Mark L. Doczy, Kevin P. O'Brien, Kaan Oguz, Tahir Ghani, Satyarth Suri
  • Patent number: 10418477
    Abstract: A silicon carbide semiconductor device, including a silicon carbide substrate, a drift layer provided on a front surface of the silicon carbide substrate, an embedded layer selectively provided in a surface layer of the drift layer, an epitaxial layer provided on the drift layer, a channel layer provided on the epitaxial layer, a source region selectively provided in a surface layer of the channel layer, a trench penetrating the source region and the channel layer and reaching the epitaxial layer, a gate electrode provided in the trench via a gate insulating film, a source electrode in contact with the channel layer and the source region, and a drain electrode provided on a rear surface of the silicon carbide substrate. The embedded layer is arranged underneath the trench in a depth direction. A longitudinal direction of the trench, which is perpendicular to the depth direction, is parallel to the off-direction of the silicon carbide substrate.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: September 17, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takeshi Tawara, Akimasa Kinoshita, Shinsuke Harada, Yasunori Tanaka
  • Patent number: 10403499
    Abstract: A laser polycrystallization apparatus including: a light source for emitting a laser beam; a diffraction grating for receiving the laser beam from the light source, changing a path and a magnitude of the received laser beam, and outputting the changed laser beam; a light split portion for splitting the laser beam received from the diffraction grating; and a light superposition portion for superposing the split laser beams received from the light split portion and irradiating the superposed split laser beams to a substrate. An angle between the laser beam irradiated to an incidence surface of the diffraction grating from the light source and a line substantially perpendicular to an emission surface of the diffraction grating is an acute angle.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: September 3, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Emil Aslanov, Jekil Ryu, Haesook Lee, Gyoowan Han