Patents Examined by William D. Bunch
  • Patent number: 5108948
    Abstract: A method of producing a semiconductor device such as a semiconductor laser having a controllably disordered superlattice. The superlattice is grown epitaxially and in the same epitaxial growth process a heavily selenium doped semiconductor layer is also grown in a known spatial relationship to the superlattice. The doped layer is patterned as by etching and then the device is annealed to diffuse selenium impurities from the doped layer. The time and temperature of annealing are controlled such that the impurities diffuse into and thereby disorder regions of the superlattice layer, leaving a non-disordered region which can serve as a resonator in a laser.
    Type: Grant
    Filed: November 17, 1988
    Date of Patent: April 28, 1992
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Takashi Murakami, Kanamf Otaki, Hisao Kumabe
  • Patent number: 5108947
    Abstract: A method of growing a GaAs crystalline layer on a Si substrate by means of which mechanical stresses causing microcracks in the materials when cooled due to the difference in their thermal coefficients are reduced and the location of the microcrack is controlled to predetermined sites. Microcracks are deliberately induced in the GaAs layer at locations where the operation of the ultimate electronic device created on the material is not affected by applying to the substrate a SiO.sub.2 mask providing a deposition opening or window for the GaAs layer, which masks defines along the opening boundary at least one vertex in the cleavage direction of the GaAs crystals. The vertices in the mask create notches in the periphery of the deposited layer which determines the location of any microcracks.
    Type: Grant
    Filed: January 25, 1990
    Date of Patent: April 28, 1992
    Assignee: Agfa-Gevaert N.V.
    Inventors: Piet M. Demeester, Ann M. Ackaert, Peter P. Van Daele, Dirk U. Lootens
  • Patent number: 5098857
    Abstract: A method of forming semi-insulating gallium arsenide by oxygen doping in a metal-organic vapor phase epitaxy system. The metal organic reactant gas containing aluminum and oxygen is introduced into the reaction chamber together with the gallium and arsenic containing reactant gases. A deep level oxygen impurity is incorporated into the growing gallium arsenide layer to form semi-insulating gallium arsenide.
    Type: Grant
    Filed: December 22, 1989
    Date of Patent: March 24, 1992
    Assignee: International Business Machines Corp.
    Inventors: Thomas F. Kuech, Michael A. Tischler
  • Patent number: 5071786
    Abstract: A multiple wavelength semiconductor laser with two active layers separated by either a p-cladding layer of a p-n junction cladding layers. A p-disordered region and a n-disordered region extend through one of the active layers and into the intermediate cladding layer. A lateral waveguide is formed between the disordered regions in the active layer and a deep waveguide is formed beneath the p-disordered region in the other active layer. Since both active layers generate lightwaves at different wavelengths, forward-biasing the p-disordered region can cause either or both waveguides to emit radiation but at different wavelengths. The deep waveguide can also be a buried heterostructure laser.
    Type: Grant
    Filed: October 20, 1990
    Date of Patent: December 10, 1991
    Assignee: Xerox Corporation
    Inventor: Thomas I. Paoli
  • Patent number: 5057022
    Abstract: A method for forming a semiconductor waveguide includes forming a layer of expitaxial silicon (12) over a substrate (10). The impurity concentration of the layer (12) is higher than that of the substrate (10). A second layer (14) of epitaxial silicon is disposed over the upper surface of the layer (12) with a higher resistivity than that of the substrate (10). A masking layer (16) is then disposed over the substrate and then patterned, and then the layer (14) selectively etched down to the upper surface of the layer (12). The layer (12)) is then porified to form an insulating layer (12') from the layer (12). The porous film is then converted by oxidation to a silicon dioxide layer (13). The sidewalls of the resulting ridge (14) are then oxidized to form sidewall layers (13') and then the masking layer (16) removed from the upper layer. The upper surface of ridge (14) is oxidized to form an upper insulating layer to extend the sidewall layer (13') over the entire upper surface and sidewalls of the ridge (14).
    Type: Grant
    Filed: May 21, 1990
    Date of Patent: October 15, 1991
    Inventor: Robert O. Miller
  • Patent number: 5053346
    Abstract: Vertical buried emitter heterojunction bipolar transistors having greatly reduced emitter to base junction area and collector dimensions are fabricated in a gallium arsenide substrate to form an integrated circuit structure. The ability to scale these critical dimensions is made possible by forming a portion of the base along the side walls and bottom of a trench which has been etched in the upper two layers of a layered gallium arsenide structure. The base is formed by implanting beryllium into the surface of an upper layer, the trench sidewalls which are formed in an undoped layer, and the bottom of the trench which is an undoped layer formed on the buried emitter. A GaAs collector layer having reduced lateral dimensions is deposited in the trench and in part, on the surface of the layered structure. Since only a small portion of the base region (the bottom of the trench) is in direct contact with the heavily doped emitter layer, the emitter to base junction area can be significantly reduced.
    Type: Grant
    Filed: March 20, 1990
    Date of Patent: October 1, 1991
    Assignee: Texas Instruments Incorporated
    Inventors: Han-Tzong Yuan, Liem Th Tran
  • Patent number: 5039627
    Abstract: A method of producing a quasi-flat semiconductor device capable of a multi-wavelength laser effect and the device thus produced.On the basis of a double heterostructure stack supported by a substrate comprising steps, following levelling of the stack and diffusion through a flat surface, a semiconductor device is obtained which is capable of a multi-wavelength laser effect, of which the different junctions are situated in a plane parallel with the base of the substrate.
    Type: Grant
    Filed: January 17, 1990
    Date of Patent: August 13, 1991
    Assignee: Etat Francais, Ministre des Postes, des Telecommunications et de l'Espace (Centre National d'Etudes des Telecommunications)
    Inventors: Louis Menigaux, Louis Dugrand
  • Patent number: 5037770
    Abstract: In a field effect transistor, nonalloyed ohmic source-drain contacts (7, 8) are made possible, as the channel layer (3) is coated with lanthanide-arsenide which serves as contact-mediating layer and is covered with a very thin, conducting, monocrystalline, epitactic gallium-arsenide layer (10) on which nickel (11) is vaporized, an alloying step being dispensed with.
    Type: Grant
    Filed: September 21, 1990
    Date of Patent: August 6, 1991
    Assignee: Fraunhofer-Gesellschaft zur Forderung der Angewandten Forschung E.V.
    Inventor: Peter Wennekers
  • Patent number: 5028562
    Abstract: A semiconductor laser includes, serially disposed, a semiconductor substrate of a first conductivity type, a semiconductor current blocking layer of a second conductivity type opposite the first conductivity tyupe, a first semiconductor cladding layer of the first conductivity type, an active semiconductor layer, a second semiconductor cladding layer of the second conductivity type, and a semiconductor contacting layer of the second conductivity type, and a structure for laterally confining the transverse flow of electrical current through the layers, the structure including a portion of the first cladding layer being disposed in a longitudinal groove extending through the current blocking layer into the substrate and high resistance longitudinal stripes disposed adjacent the groove between the second cladding layer and the current blocking layer, the high resistance stripes forming discontinuities in the active semiconductor layer.
    Type: Grant
    Filed: June 14, 1990
    Date of Patent: July 2, 1991
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Akihiro Shima
  • Patent number: 5028560
    Abstract: A method and apparatus for manufacturing a semiconductor device having a thin layer of material formed on a semiconductor substrate with a much improved interface between them are disclosed. A silicon substrate is heated up to a temperature around 300.degree. C. in the presence of ozone gas under exposure to UV light. Through this process, organic contaminants that might be present on the surface of the silicon substrate are dissipated by oxidation, and a thin oxide film is formed on the substrate surface on the other. The silicon substrate with the thin oxide film coated thereon is then heated up to temperature of 200.degree.-700.degree. C. in the presence of HCl gas under illumination to UV light to strip the oxide film off the substrate surface, thereby exposing the cleaned substrate surface. Finally, HCl cleaned surface of the silicon substrate is coated with a thin layer of material such as monocrystalline silicon without exposing the cleaned substrate surface.
    Type: Grant
    Filed: March 1, 1989
    Date of Patent: July 2, 1991
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Katsuhiro Tsukamoto, Akira Tokui
  • Patent number: 5024967
    Abstract: A process is described for making semiconductor devices with highly controlled doping profiles. The process involves minimizing or eliminating segregation effects caused by surface electric fields created by Fermi-level pinning. These electric fields act on dopant ions and cause migration from the original deposition site of the doplant ions. Dopant ions are effectively shielded from the surface electric fields by illumination of the growth surfaces and by background doping. Also, certain crystallographic directions in certain semiconductors do not show Fermi-level pinning and lower growth temperatures retard or eliminate segregation effects. Devices are described which exhibit enhanced characteristics with highly accurate and other very narrow doping profiles.
    Type: Grant
    Filed: June 30, 1989
    Date of Patent: June 18, 1991
    Assignee: AT&T Bell Laboratories
    Inventors: Rose F. Kopf, J. M. Kuo, Henry S. Luftman, Erdmann F. Schubert
  • Patent number: 5017517
    Abstract: A method for fabricating a semiconductor device comprises the steps of forming the first semiconductor layer on a semiconductor substrate, forming a surface protection layer of antimony (Sb) or the material having Sb as its main component, executing the other steps necessary for the fabrication of the semiconductor device, removing the surface protection layer, and forming, on the first semiconductor layer thus exposed, the second semiconductor layer.
    Type: Grant
    Filed: May 2, 1990
    Date of Patent: May 21, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Kazuhiro Mochizuki, Tomonori Tanoue, Chushirou Kusano, Hiroshi Masuda, Katsuhiko Mitani
  • Patent number: 5013684
    Abstract: In situ removal of selected or patterned portions of semiconductor layers is accomplished by induced evaporation enhancement to form patterned buried impurity layers in semiconductor devices, such as heterostructure lasers and array lasers, which function as buried impurity induced layer disordering (BIILD) sources upon subsequent annealing. These layers may be formed to either function as buried impurity induced layer disordering (BIILD) sources or function as a reverse bias junction configuration of confining current to the active region of a laser structure. Their discussion here is limited to the first mentioned function.
    Type: Grant
    Filed: March 24, 1989
    Date of Patent: May 7, 1991
    Assignee: Xerox Corporation
    Inventors: John E. Epler, Thomas L. Paoli
  • Patent number: 5013682
    Abstract: Selective growth of GaAs and related semiconductors (34) by use of tungsten silicide and related materials for growth masks (36) plus devices incorporating the selective growth plus use of the growth masks as electrical contacts are disclosed. The deposition of semiconductor (38) on such masks (36) is inhibited and single crystal vertical structures (34) grow on unmasked regions of the lattice-matched substrate (32). Variation of the mask (36) composition can vary the inhibited deposition on the mask (36) from small isolated islands of polycrystalline semiconductor (38) to a uniform layer of polycrystalline semiconductor abutting the single crystal structures. Preferred embodiments include bipolar transistors with the selectivity grown structure forming the base and emitter or collector and the mask being the base contact and also include lasers with the vertical structures including the resonant cavities with the mirros being the sidewalls of the vertical structures.
    Type: Grant
    Filed: June 30, 1989
    Date of Patent: May 7, 1991
    Assignee: Texas Instruments Incorporated
    Inventors: Donald L. Plumton, Liem T. Tran, Hung-Dah Shih
  • Patent number: 5013681
    Abstract: A process for fabricating thin film silicon wafers using a novel etch stop composed of a silicon-germanium alloy includes properly doping a prime silicon wafer for the desired application, growing a strained Si.sub.1-x Fe.sub.x alloy layer onto seed wafer to serve as an etch stop, growing a silicon layer on the strained alloy layer with a desired thickness to form the active device region, oxidizing the prime wafer and a test wafer, bonding the oxide surfaces of the test and prime wafers, machining the backside of the prime wafer and selectively etching the same to remove the silicon, removing the strained alloy layer by a non-selective etch, thereby leaving the device region silicon layer. In an alternate embodiment, the process includes implanting germanium, tin or lead ions to form the strained etch stop layer.
    Type: Grant
    Filed: September 29, 1989
    Date of Patent: May 7, 1991
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: David J. Godbey, Harold L. Hughes, Francis J. Kub
  • Patent number: 4994408
    Abstract: A method for growing high quality epitaxial films using low pressure MOCVD that includes providing a substrate that is misoriented from a singular plane, placing the substrate into an MOCVD reactor at a total pressure of less than 0.2 atmospheres and then growing an epitaxial film on the substrate. When providing a misoriented gallium arsenide substrate, the MOCVD reactor is set at a temperature in the range of 650 to 750 degrees centigrade to grow an aluminum gallium arsenide film. This temperature is substantially lower than that at which aluminum gallium arsenide epitaxial films are commonly grown and the resulting film has a smooth surface morphology and enhanced photoluminesence properties.
    Type: Grant
    Filed: February 6, 1989
    Date of Patent: February 19, 1991
    Assignee: Motorola Inc.
    Inventor: Eric S. Johnson
  • Patent number: 4990466
    Abstract: A method of altering a refractive index, as for an optical waveguide, as in a buried heterostructure laser, by inducing disordering in a region of a semiconducotr body comprises exposing a surface portion of the semiconductor body to plasma etching, coating at least a part of the surface portion with an oxide layer, heat treating the semiconductor body.
    Type: Grant
    Filed: November 1, 1988
    Date of Patent: February 5, 1991
    Assignee: Siemens Corporate Research, Inc.
    Inventors: Chan-Long Shieh, Joseph I. Mantz, Reinhard W. H. Engelmann
  • Patent number: 4988640
    Abstract: The present invention addresses the use of at least partially fluorinated organometallic compounds in reactive deposition applications. More specifically, the present invention addresses the use of the fluoroorganometallic compounds M(CF.sub.3).sub.3, or any M(C.sub.n F.sub.(2n+1)).sub.3-y H.sub.y compound where (y.ltoreq.2), M(CH.sub.2 CF.sub.3).sub.3 or any fluoroalkyl organometallics of the general formula M(C.sub.n H.sub.[(2n+1)-x] F.sub.x).sub.3-y H.sub.y, where y.ltoreq.2; x has a value 1.ltoreq.x.ltoreq.2n+1; and M=As, P, or Sb, in processes requiring deposition of the corresponding element. These uses include a number of different processes; the organometallic vapor phase epitaxy of compound semiconductor materials such as GaAs, InP, AlGaAs, InSb, etc. doping of SiO.sub.
    Type: Grant
    Filed: November 6, 1989
    Date of Patent: January 29, 1991
    Assignee: Air Products and Chemicals, Inc.
    Inventors: David A. Bohling, Gregory T. Muhr, David A. Roberts
  • Patent number: 4987096
    Abstract: An InGaAlP NAM structure laser is formed with a double-heterostructure section disposed on an n-type GaAs substrate. The double-heterostructure section includes a first cladding layer of n-type InGaAlP, a non-doped InGaP active layer, and a second cladding layer of p-type InGaAlP. An n-type GaAs current-blocking layer having a stripe opening and a p-type GaAs contact layer are sequentially formed on the second cladding layer by MOCVD crystal growth. A low-energy band gap region is defined in a central region of the active layer located immediately below the stripe opening. A high-energy band gap region is defined in a peripheral region of the active layer corresponding to a light output end portion of the laser and located immediately below the current-blocking layer. Therefore, self absorption of an oscillated laser beam at the output end portion can be reduced or prevented.
    Type: Grant
    Filed: December 13, 1989
    Date of Patent: January 22, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Ishikawa, Hajime Okuda, Hideo Shiozawa, Kazuhiko Itaya, Yukio Watanabe, Mariko Suzuki, Genichi Hatakoshi
  • Patent number: 4983539
    Abstract: A process for producing a semiconductor article comprises applying crystal formation treatment to a substrate having a free surface on which a nonnucleation surface exhibiting a smaller nucleation density and a nucleation surface of an amorphous material exhibiting a larger nucleation density and having a sufficiently minute area so as to allow only a single nucleus to be formed thereon are disposed next to each other whereby a semiconductor monocrystal is permitted to grow from the nucleus, the production conditions during said crystal formation treatment being varied to form semiconductor crystal regions different in their characteristics within at least part of said semiconductor monocrystal.
    Type: Grant
    Filed: April 13, 1990
    Date of Patent: January 8, 1991
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kenji Yamagata, Takeshi Ichikawa