Patents Examined by William D. Bunch
  • Patent number: 4950615
    Abstract: A technique is disclosed forming thin films (13) of group IIB metal-telluride, such as Cd.sub.x Zn.sub.1-x Te (0.ltoreq.x.ltoreq.1), on a substrate (10) which comprises depositing Te (18) and at least one of the elements (19) of Cd, Zn, and Hg onto a substrate and then heating the elements to form the telluride. A technique is also provided for doping this material by chemically forming a thin layer of a dopant on the surface of the unreacted elements and then heating the elements along with the layer of dopant.
    Type: Grant
    Filed: February 6, 1989
    Date of Patent: August 21, 1990
    Assignee: International Solar Electric Technology, Inc.
    Inventors: Bulent M. Basol, Vijay K. Kapur
  • Patent number: 4950624
    Abstract: An improved CVD apparatus for depositing a uniform film is shown. The apparatus comprises a reaction chamber, a substrate holder and a plurality of light source for photo CVD or a pair of electrode for plasma CVD. The substrate holder is a cylindrical cart which is encircled by the light sources, and which is rotated around its axis by a driving device. With this configuration, the substrates mounted on the cart and the surroundings can be energized by light or plasma evenly throughout the surfaces to be coated.
    Type: Grant
    Filed: May 16, 1988
    Date of Patent: August 21, 1990
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takashi Inuzima, Shigenori Hayashi, Toru Takayama, Seiichi Odaka, Naoki Hirose
  • Patent number: 4950622
    Abstract: A method for manufacturing a surface emitting type AlGaAs/GaAs semiconductor LASER diode by a selective epitaxy method which is capable of forming naturally a 45.degree. mirror reflective face during the epitaxy method itself. The method comprises the steps of forming a silicon oxide or silicon nitride layer on one side of a n-type single crystal GaAs substrate as a mask, removing the mask of the regions each for forming a 45.degree. mirror reflective face and a LASER diode by use of a photolithography and a chemicaletching, forming the two layers by removing the photoresistor on the remaining mask after a selective epitaxy process and converting a slant face of the LASER diode into a vertical face, depositing a n-type metal layer on the other side of the substrate, and carrying out a heat treatment.
    Type: Grant
    Filed: April 27, 1989
    Date of Patent: August 21, 1990
    Assignee: Korea Advanced Institute of Science and Technology
    Inventors: Young Se Kwon, Tae Kyung Yoo
  • Patent number: 4948751
    Abstract: A method of selective epitaxial growth includes a step of selectively forming an insulator film on a predetermined region of a semiconductor substrate and a step of evaporating a starting material containing a Group III element in vacuum in the presence of a Group V element to grow epitaxially a III-V compound semiconductor selectively on the semiconductor substrate under the condition where the partial pressure of the Group III element just above the semiconductor substrate is greater than the equilibrium vapor pressure of the Group III element contained in the III-V compound semiconductor existing on the semiconductor substrate and is smaller than the equilibrium vapor pressure of the Group III element contained in the III-V compound semiconductor existing on the insulator film.When InAs is grown epitaxially and selectively on a GaAs substrate, the GaAs substrate is kept at 500.degree. to 650.degree. C.
    Type: Grant
    Filed: May 19, 1988
    Date of Patent: August 14, 1990
    Assignee: NEC Corporation
    Inventors: Akihiko Okamoto, Keiichi Ohata
  • Patent number: 4937204
    Abstract: A semiconductor apparatus is disclosed, in which the entire or part of an electron active region is formed by a superlattice structure semiconductor layer in which a plurality of different semiconductor layers, less than 8 monolayers, and containing a fraction or a binary compound semiconductor layers are alternately and epitaxially grown and a main current direction is selected to be in the direction perpendicular to the laminae of said superlattice layers.
    Type: Grant
    Filed: January 4, 1989
    Date of Patent: June 26, 1990
    Assignee: Sony Corporation
    Inventors: Akira Ishibashi, Yoshifumi Mori, Masao Itabashi
  • Patent number: 4927778
    Abstract: A high yield method for the fabrication of multi-element, gallium-arsenide-phosphide light emitting diode arrays having square light emitting elements 7903 square microns on 88.9 micron center suitable for use in electronic/optical printers, is described. The resulting arrays at a current density of 200 A/cm.sup.2 have 0.6% power efficiency and a radiant exitance of 3.8 W cm -2 with less than 2% standard deviation in element to element radiant exitance. The integrated, relatively low cost LED arrays, are particularly suitable for use in electronic/optical printing applications.
    Type: Grant
    Filed: August 5, 1988
    Date of Patent: May 22, 1990
    Assignee: Eastman Kodak Company
    Inventor: Daniel C. Abbas
  • Patent number: 4888300
    Abstract: To completely isolate an island of silicon, a trench is cut into an epitaxial layer to provide access to a differently doped buried layer. While suspending the portion of the epitaxial layer surrounded by the trench by means of an oxide bridge, the underlying region of the buried layer is etched away to form a cavity under the active area. This cavity, as well as the surrounding trench, is then filled with a suitable insulating material to isolate the active island from the substrate.
    Type: Grant
    Filed: November 7, 1985
    Date of Patent: December 19, 1989
    Assignee: Fairchild Camera and Instrument Corporation
    Inventor: Gregory N. Burton
  • Patent number: 4888302
    Abstract: A defect free monocrystalline layer of silicon on an insulator is produced by forming a thin layer of silicon dioxide on a monocrystalline silicon substrate, forming a thin layer of polycrystalline or amorphous silicon on the silicon dioxide layer and focussing two beams from lamps on the thin silicon layer to form a line image providing a melt zone surrounded by two narrow heated zones having temperatures lower than the melt zone and having a temperature differential of from 2.degree.-10.degree. C./mm decreasing form the melt zone while heating the substrate to a temperature below that of the zones heated by the lamps and scanning the structure.
    Type: Grant
    Filed: March 29, 1989
    Date of Patent: December 19, 1989
    Assignee: North American Philips Corporation
    Inventor: Subramanian Ramesh
  • Patent number: 4885257
    Abstract: A semiconductor substrate and process for making are disclosed. The substrate is suitable for use in manufacturing large scale integrated circuits. The process comprises the steps of heating a semiconductor substrate at a temperature not lower than 1100.degree. C., implanting electrically inert impurities into the major surface of the substrate, heating the substrate at a temperature ranging from 600.degree. to 900.degree. C. and providing a single crystal semiconductor layer.
    Type: Grant
    Filed: June 2, 1987
    Date of Patent: December 5, 1989
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshiaki Matsushita
  • Patent number: 4885258
    Abstract: There is provided an improved thin-film transistor of which a principal semiconducting layer comprises a layer composed of an amorphous material prepared by (a) introducing (i) a gaseous substance containing atoms capable of becoming constituents for said layer into a film forming chamber having a substrate for thin-film transistor through a transporting conduit for the gaseous substance and (ii) a gaseous halogen series substance having a property to oxidize the gaseous substance into the film forming chamber through a transporting conduit for the gaseous halogen series oxidizing agent, (b) chemically reacting the gaseous substance and the gaseous halogen series agent in the film forming chamber in the absence of a plasma to generate plural kinds of precursors containing exited precursors and (c) forming said layer on the substrate with utilizing at least one kind of those precursors as a supplier.
    Type: Grant
    Filed: November 1, 1988
    Date of Patent: December 5, 1989
    Assignee: Canon Kabushiki Kaisha
    Inventors: Shunichi Ishihara, Hirokazu Ootoshi, Masaaki Hirooka, Junichi Hanna, Isamu Shimizu
  • Patent number: 4865655
    Abstract: An epitaxial wafer for producing arrays of GaAsP-LEDs comprises, in the GaAs.sub.1-x P.sub.x layer with varying X, a layer region(s) with a discontinuous variance of x along the thickness of the GaAs.sub.1-x P.sub.x layer. This layer region(s) contribute to a uniformity in the brightness of the light emission of LEDs formed in the epitaxial wafer.
    Type: Grant
    Filed: November 18, 1987
    Date of Patent: September 12, 1989
    Assignees: Mitsubishi Monsanto Chemical Co., Ltd., Mitsubishi Chemical Industries, Ltd.
    Inventors: Hisanori Fujita, Masaaki Kanayama, Takeshi Okano
  • Patent number: 4863878
    Abstract: The described embodiments of the present invention provide a semiconductor on insulator structure providing a semiconductor layer less susceptible to single event upset errors (SEU) due to radiation. The semiconductor layer is formed by implanting ions which form an insulating layer beneath the surface of a crystalline semiconductor substrate. The remaining crystalline semiconductor layer above the insulating layer provides nucleation sites for forming a crystalline semiconductor layer above the insulating layer. The damage caused by implantation of the ions for forming an insulating layer is left unannealed before formation of the semiconductor layer by epitaxial growth. The epitaxial layer, thus formed, provides superior characteristics for prevention of SEU errors, in that the carrier lifetime within the epitaxial layer, thus formed, is less than the carrier lifetime in epitaxial layers formed on annealed material while providing adequate semiconductor characteristics.
    Type: Grant
    Filed: April 6, 1987
    Date of Patent: September 5, 1989
    Assignee: Texas Instruments Incorporated
    Inventors: Larry R. Hite, Ted Houston, Mishel Matloubian
  • Patent number: 4859627
    Abstract: A method of producing n-type III-V compound semiconductor comprises growing a plurality of monolayers of III-V compound semiconductor molecules on a III-V compound substrate; growing a single layer of group VI element on the III-V monolayers so as to occupy the lattice points for group V element by means of Atomic Layer Epitaxy process; decreasing the number of group VI element by exposing the single layer to the gas of group V element; and growing a plurality of monolayers of III-V compound semiconductor molecules on the group VI element-doped layer by means of the Atomic Layer Epitaxy process.
    Type: Grant
    Filed: July 1, 1988
    Date of Patent: August 22, 1989
    Assignee: NEC Corporation
    Inventor: Haruo Sunakawa
  • Patent number: 4845049
    Abstract: An n-type III-V compound semiconductor comprises a plurality of monolayers of III-V compound semiconductor molecules having a layer-by-layer structure of group III element and group V element laminated alternately, and a group VI element-doped monolayer. The group VI element-doped monolayer is inserted into the III-V compound semiconductor molecules by occupying lattice points which were occupied by the group V element. The layers of the semiconductor are grown by Atomic Layer Epitaxy process.
    Type: Grant
    Filed: March 28, 1988
    Date of Patent: July 4, 1989
    Assignee: NEC Corporation
    Inventor: Haruo Sunakawa
  • Patent number: 4829023
    Abstract: A method for producing a semiconductor laser including successively growing at least two semiconductor layers simultaneously on a substrate, the finally grown layer not containing aluminum and the layer grown immediately before the finally grown layer containing aluminum, etching a stripe groove through the finally grown layer to expose part of the semiconductor layer containing aluminum, growing a second semiconductor layer not including aluminum on the finally grown layer and the exposed surface of the semiconductor layer containing aluminum, and growing a semiconductor layer including aluminum on the second semiconductor layer not containing aluminum.
    Type: Grant
    Filed: November 30, 1987
    Date of Patent: May 9, 1989
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yutaka Nagai, Yutaka Mihashi, Tetsuya Yagi, Yoichiro Ota
  • Patent number: 4829021
    Abstract: An injection block having a plurality of geometrically arranged injection sources for gaseous Group III metal organic compounds is oriented substantially perpendicular to the placement of at least one semiconductor wafer substrate within a vacuum reaction chamber. The injector sources are sized to provide disbursing flow of the compounds capable of depositing a layer of about 5% uniform thickness or less over substantially the entire semiconductor wafer. An injection source of Group V compounds is located centrally within the geometrically arranged injection sources for the Group III compounds. The Group V injection source is sized to supply an excess of the Group V compounds required to react with the Group III compounds in order to form Group III-V semiconductor layers on the substrate and partition the Group III sources into groups having substantially equal numbers of injection sources. An excess of Group V comounds is injected.
    Type: Grant
    Filed: December 9, 1987
    Date of Patent: May 9, 1989
    Assignee: Daido Sanso K.K.
    Inventors: Lewis M. Fraas, Paul S. McLeod, John A. Cape
  • Patent number: 4829022
    Abstract: A method of forming a III-V semiconductor on the surface of a substrate which is placed in a vacuum chamber and is heated, by supplying one element of Group III and one element of Group V of the periodic table in the form of atoms or molecules to the surface of the substrate. The supply of the element of Group V is decreased to a small quantity insufficient to form a III-V compound semiconductor at least at one period of the growth of the III-V compound, and the element of Group V in the small quantity and the element of Group III are supplied to the surface of the substrate. This method makes it possible to grow III-V compound epitaxial layers which have a high degree of purity and fewer crystal defects and in which surfaces and the interfaces of the heterojunctions are flat on an atomic scale, at a wide temperature range. The present invention can be used for the fabrication of various optical devices and super-high-speed electronic devices.
    Type: Grant
    Filed: August 5, 1987
    Date of Patent: May 9, 1989
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Naoki Kobayashi, Hideo Sugiura, Yoshiji Horikoshi
  • Patent number: 4824798
    Abstract: A thin film bilayer composite source comprises a deposited impurity source layer, e.g. Si or Sb, heavily doped with a diffusion enabling agent, e.g. As, and capped with a passivating layer, e.g. Si.sub.3 N.sub.4, SiO.sub.2, AlN or SiO.sub.x N.sub.y. In a preferred embodiment, a thin film bilayer composite source comprises a Si layer on the surface of said structure vapor deposited at a temperature in excess of 500.degree. C. in the presence of a source of As to hevily dope the layer in the range of 5%-20% atomic weight and a thin cap layer of Si.sub.3 N.sub.4 deposited on the Si layer at a temperature in excess of 500.degree. C. having a thickness only sufficient to prevent the outdiffusion of Ga and As, which thickness may be about 400 .ANG.-700 .ANG.. An important aspect of the employment of this bilayer composite source as a diffusion source for III-V structures is that the composite source is initially deposited at high temperatures, above 500.degree.0 C., i.e.
    Type: Grant
    Filed: November 5, 1987
    Date of Patent: April 25, 1989
    Assignee: Xerox Corporation
    Inventors: Robert D. Burnham, Robert L. Thornton
  • Patent number: 4803181
    Abstract: A process for forming sidewalls for use in the fabrication of semiconductor structures, where the thin, vertical sidewalls are "image transferred" to define sub-micron lateral dimensions.First, a patterned resist profile with substantially vertical edges is formed on a substrate on which the sidewalls are to be created. Then, the profile is soaked in a reactive organometallic silylation agent to silylate the top and the vertical edges of the resist to a predetermined depth, thereby rendering the profile surfaces highly oxygen etch resistant. In a subsequent anisotropic RIE process, the horizontal surfaces of the silylated profile and the unsilylated resist are removed, leaving the silylated vertical edges, that provide the desired free-standing sidewalls, essentially unaffected.
    Type: Grant
    Filed: March 17, 1987
    Date of Patent: February 7, 1989
    Assignee: International Business Machines Corporation
    Inventors: Peter L. Buchmann, Peter Vettiger, Bart J. Van Zeghbroech
  • Patent number: 4771018
    Abstract: An improved method for eutectically bonding a silicon wafer onto a gold preform is described. A gold/silicon seed is placed on a pure gold preform. Then a die is placed onto the pure gold preform and the gold/silicon seed, wherein the seed acts as a catalyst to form an eutectic bond.
    Type: Grant
    Filed: March 19, 1987
    Date of Patent: September 13, 1988
    Assignee: Intel Corporation
    Inventors: Bidyut K. Bhattacharyya, Eric S. Tosaya