Abstract: To fabricate masks for deep ultra-violet lithography and for extreme ultra-violet lithography, a layer of material opaque to deep ultra-violet radiation and an extreme ultra-violet radiation absorbent layer are each deposited successively with a layer of silicon and a layer of metal on a respective transparent substrate. A focused electron beam is displaced on the superposed layers of metal and silicon to form a structure of etch-resistant metal/silicon compound. The deep ultra-violet mask is then formed by etching the three layers to leave on the substrate, the metal/silicon compound structure with the extreme ultra-violet absorbent layer beneath it.

Abstract: A process for fabricating an MOS device having a highly-localized halo region includes the formation of a first halo region at a first surface of a silicon substrate, and a second halo region at a second surface of the silicon substrate. The second surface of the silicon substrate is formed by anisotropically etching the first surface of the silicon substrate to remove a portion of the material from the substrate. Both the first and second halo regions are formed by low-energy ion implantation. For the fabrication of an n-channel device, boron is implanted at an energy of no more than about 1 keV. Upon implantation and a subsequent annealing process, the first and second halo regions form a continuous halo region within the semiconductor substrate.

Abstract: A semiconductor device comprising a wiring substrate which has a laminated glass fabric body made by laminating a plurality of glass fabrics and impregnating with resin. A resin layer is provided on at least one of surfaces of the laminated glass fabric body. A plurality of pad electrodes are formed on the resin layer. The resin layer has a thickness from 1.5 to 2.5 times the depth of unevenness of the surface of the laminated glass fabric body on which the resin layer exists. A semiconductor pellet is disposed on the wiring substrate and has a plurality of projected electrodes. The projected electrodes are electrically coupled to the pad electrodes by pressing the projected electrodes to the pad electrodes while heating the wiring substrate and/or the semiconductor pellet. Tip portions of the projected electrodes together with the pad electrodes plunge into the resin layer.

Abstract: A CMOS device formed with a Silicon On Insulator (SOI) technology with reduced Drain Induced Barrier Lowering (DIBL) characteristics and a method for producing the same. The method involves a high energy, high dose implant of boron and phosphorus through the p- and n-wells, into the insulator layer, thereby creating a borophosphosilicate glass (BPSG) structure within the insulation layer underlying the p- and n-wells of the SOI wafer. Backend high temperature processing steps induce diffusion of the boron and phosphorus contained in the BPSG into the p- and n-wells, thereby forming a retrograde dopant profile in the wells. The retrograde dopant profile reduces DIBL and also provides recombination centers adjacent the insulator layer and the active layer to thereby reduce floating body effects for the CMOS device.

Abstract: The invention provides microelectronic devices such as integrated circuit devices. Such have vias, interconnect metallization and wiring lines using dissimilar low dielectric constant intermetal dielectrics. The use of both organic and inorganic low-k dielectrics offers advantages due to the significantly different plasma etch characteristics of the two kinds of dielectrics. One dielectric serves as the etchstop in etching the other dielectric so that no additional etchstop layer is required. A microelectronic device is formed having a substrate and a layer of a first dielectric material positioned on the substrate. A layer of a second dielectric material is positioned on the first dielectric layer and an additional layer of the first dielectric material positioned on the second dielectric material.

Abstract: A Pb3GeO5 phase PGO thin film is provided. This film has ferroelastic properties that make it ideal for many microelectromechanical applications or as decoupling capacitors in high speed multichip modules. This PGO film is uniquely formed in a MOCVD process that permits a thin film, less than 1 mm, of material to be deposited. The process mixes Pd and germanium in a solvent. The solution is heated to form a precursor vapor which is decomposed. The method provides deposition temperatures and pressures. The as-deposited film is also annealed to enhanced the film's ferroelastic characteristics. A ferroelastic capacitor made from the present invention PGO film is also provided.

Abstract: Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate area over which a field effect transistor gate is to be formed. A dopant of a first conductivity type is provided through the opening and into the substrate. Sidewall spacers are formed over respective sidewaUs of the opening. Enhancement dopant of a second conductivity type which is different from the first conductivity type is provided through the opening and into the substrate. A transistor gate is formed within the opening proximate the sidewall spacers, and source/drain regions of the second conductivity type are diffused into the substrate operably proximate the transistor gate. The first conductivity type dopant forms a halo region proximate the source/drain regions and lightly doped drain (LDD) regions for the transistor.

Abstract: A TMR element includes: a free layer formed on a lower gap layer; a tunnel barrier layer formed on the free layer; and a pinned layer formed on the tunnel barrier layer. In the step of forming the tunnel barrier layer on the free layer, an Al layer used for making the tunnel barrier layer is formed through sputtering, for example, on the free layer while the substrate is cooled. The Al layer is oxidized to form the tunnel barrier layer.

Abstract: The present invention discloses a method for fabricating a SOI wafer.

Abstract: A transistor structure includes a retrograde gate structure (112) that is narrower at the end that interfaces with the gate dielectric (120) than it is at the opposite end and method for manufacture of such a structure. The retrograde gate structure (112) is formed by depositing a layer of gate material (104) that has varying composition in the vertical direction. The differentiation in composition causes varying lateral etch rate characteristics along the vertical direction of the gate structure (112) such that increased etching of the gate material (104) occurs near the interface with the gate dielectric layer (102).

Abstract: A semiconductor device for use in a memory cell includes an active matrix provided with a semiconductor substrate, a transistor formed on the semiconductor substrate, an isolation region for isolating the transistor and an insulating layer formed on top of the transistor and the isolation region; and a capacitor structure, formed on top of the insulating layer, composed of a bottom electrode, a capacitor thin film placed on top of the bottom electrode and a top electrode formed on top of the capacitor thin film, wherein the capacitor thin film is made of Nb doped lead zirconate titanate (PNZT). In the device, the PNZT is formed by using a sol-gel coating solution is represented by a formula Pb(1−x/2)Pbx(Zr0.52Ti0.48)(1−x)O3, where x is equal to 0˜0.05 assuming that Nb compensates charges generated by Pb vacancies. The semiconductor device can lower leakage current approximately 2 order by adding Nb dopants to the PZT.

Abstract: An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate, and a channel dielectric layer formed on the device dielectric layer has an opening formed therein. A barrier layer of titanium, tantalum, tungsten, or a nitride of the aforegoing is deposited to line the opening, and a copper or copper alloy conductor core is deposited to fill the channel opening over the barrier layer. After planarization of the conductor core and the barrier layer, an ammonia, nitrogen hydride, or hydrogen plasma treatment is performed below 300° C. to reduce the residual oxide on the conductor core material. The plasma treatment is followed by the deposition of a silicon nitride capping layer performed below 300° C. After the reducing and deposition process, a densification process is performed between 380° C. and 420° C.

Abstract: A semiconductor memory device includes a memory cell region having an array of a plurality of memory cells, and a peripheral circuit region to which a bit line connected to a predetermined number of the memory cells in the memory cell region is extended and connected. The bit line in the memory cell region and the bit line in the peripheral circuit region have substantially the same upper surface height.

Abstract: A TFT having stable characteristics is obtained by using a crystal silicon film obtained by crystallizing an amorphous silicon film by using nickel. Phosphorus ions are implanted to regions 111 and 112 by using a mask 109. Then, a heat treatment is performed to getter nickel existing in a region 113 to the regions 111 and 112. Then, the mask 109 is side-etched to obtain a pattern 115. Then, the regions 111 and 112 are removed by utilizing the pattern 115 and to pattern the region 113. Thus, a region 116 from which nickel element has been removed is obtained. The TFT is fabricated by using the region 116 as an active layer.

Abstract: A ferroelectric non-volatile memory in which each memory cell consists of a single electronic element, a ferroelectric FET. The FET includes a source, drain, gate and substrate. The fact that the drain to source current, lds, is always negative if a substrate to drain bias, Vss, of 0.8 volts or more is applied, permits the creation of a read and write truth table. A gate voltage equal to one truth table logic value is applied via a column decoder and a substrate bias equal to another truth table logic value is applied via a row decoder to write to the memory a resultant lds logic state, which can be read whenever a voltage is placed across the source and drain.

Abstract: Method for producing an NMOS, PMOS or CMOS semiconductor device with reduced substrate current and increased device lifetime. A source-gate-drain device is fabricated having a moderately doped source region, a lightly doped source region, a gate or channel region, a lightly doped drain region, and a moderately doped drain region, arranged consecutively in that order, with the channel region adjacent to the gate having opposite electrical conductivity type to the electrical conductivity type of the source and drain regions. The source region and drain region are formed by ion implantation with ion kinetic energies of 40 keV or more, to increase the width and depth of charge carrier flow in these regions and to thereby reduce the substrate current associated with the device to less than one &mgr;Amp/&mgr;m.

Abstract: Dynamic Random Access Memory (DRAM) cells are formed in a P well formed in a biased deep N well (DNW). PMOS transistors are formed in N wells. The NMOS channels stop implant mask is modified not to be a reverse of the N well mask in order-to block the channels stop implant from an N+ contact region used for DNW biasing. In DRAMS and other integrated circuits, a minimal spacing requirement between a well of an integrated circuit on the one hand and adjacent circuitry on the other hand is eliminated by laying out the adjacent circuitry so that the well is located adjacent to a transistor having an electrode connected to the same voltage as the voltage that biases the well. For example, in DRAMs, the minimal spacing requirement between the DNW and the read/write circuitry is eliminated by locating the DNW next to a transistor precharging the bit lines before memory accesses. One electrode of the transistor is connected to a precharge voltage.

Abstract: A method for manufacturing a cylindrical storage electrode of a semiconductor device includes forming a contact pad to be connected to an active region of a semiconductor substrate in an interlayer insulator film on the semiconductor substrate. Then, a silicon nitride layer as an etching stop layer is formed on the contact pad. Next, an insulating layer is formed on the silicon nitride layer. A portion of the surface of the silicon nitride layer is exposed by partially removing the insulating layer. Then, the exposed portion of the silicon nitride layer is removed using a wet etching process using a predetermined etchant to expose the surface of the contact pad. A conductive layer for a storage electrode is formed on the insulating layer and the surface of the exposed contact pad. Finally, a cylindrical storage electrode is completed by removing the upper portion of the conductive layer for a storage electrode, the insulating layer and the silicon nitride layer.

Abstract: A method is provided for improving the tungsten, W-filling of hole openings in semiconductor substrates. This is accomplished by forming an opening—which can be used either as a contact or via hole—with a faceted entrance along with tapered side-walls. This combination of faceted entrance and tapered side-walls improves substantially the tungsten W-filling of contact/via holes in substrates without the formation of key-holes, thereby resulting in metal plugs of high electrical integrity and high reliability.

Abstract: Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate area over which a field effect transistor gate is to be formed. A dopant of a first conductivity type is provided through the opening and into the substrate. Sidewall spacers are formed over respective sidewalls of the opening. Enhancement dopant of a second conductivity type which is different from the first conductivity type is provided through the opening and into the substrate. A transistor gate is formed within the opening proximate the sidewall spacers, and source/drain regions of the second conductivity type are diffused into the substrate operably proximate the transistor gate. The first conductivity type dopant forms a halo region proximate the source/drain regions and lightly doped drain (LDD) regions for the transistor.