Abstract: A method of producing patterned epitaxial silicon films and devices fabricated thereby is described. The method forms a first layer of a refractory material on a substrate and pattern delineates the first layer. Silicon is then deposited at a temperature within the range between 400 degrees C. and 700 degrees C. and the polycrystalline material that forms is removed.

Abstract: A vertical transistor device is characterized by active regions vertically separated by a narrower control region. The control region is defined by conducting layer extensions which extend into a groove within which semiconductor material is regrown during device fabrication. The device is further characterized by regions of isolating material, located horizontally adjacent to the active regions, said isolating material serving to reduce parasitic capacitance and improve thermal distribution within the device, thereby improving frequency and power performance.

Abstract: Dislocation densities are reduced in growing semiconductors from the vapor phase by employing a technique of interrupting growth, cooling the layer so far deposited, and then repeating the process until a high quality active top layer is achieved. The method of interrupted growth, coupled with thermal cycling, permits dislocations to be trapped in the initial stages of epitaxial growth.

Abstract: A method of making a dielectric isolation integrated circuit structure in which dielectric material grooves formed by ion implantation extend down into the structure and intersect a PN junction or other active region at intersection lines such that each intersection line is within microns both laterally from the center of the groove and vertically from the bottom of the groove and the grooves continuously curve at least at the intersection lines at a radius of curvature less than 1 cm.

Abstract: Process for the production of semiconductor devices by using silicon-on-insulator (SOI) techniques. The Si layers of the SOI structure include an interfacial layer of Si and a buffer layer of Si formed thereon, whereby the formation of stacking faults in the Si layers can be effectively prevented. Pretreatment of the underlying insulating material with a molybdate solution and interposition of an additional layer of slowly grown single-crystalline Si between the buffer layer of Si and the overlying active Si layer are also effective to inhibit the stacking faults. Semiconductor devices with high quality can be produced with good yield.

Abstract: A permeable base transistor (30) including a metal base layer (34) embedded in a semiconductor crystal (32) to separate collector (38) and emitter (40) regions and form a Schottky barrier with each is disclosed. The metal base layer has at least one opening (37) through which the crystal semiconductor (32) joins the collector (38) and emitter (40) regions. Ohmic contacts (42,44) are made to the emitter (38) and collector (40) regions. The width of all openings (37) in the base layer (34) is of the order of the zero bias depletion width corresponding to the carrier concentration in the opening. The thickness of the metal layer (34) is in the order of 10% of this zero bias depletion width. As a result, a potential barrier in each opening limits current flow over the lower portion of the bias range.

Abstract: The method for making an improved, surface-passivated and electrically isolated silicon device (including integrated circuit) comprises providing in a silicon wafer with a pn junction or other electronic rectifying barrier; and thermally oxidizing or ion-implanting oxygen or nitrogen into selected silicon surface regions to form electrically isolating grooves. The grooves have symmetrical, centrally rounded bottoms which are located within a few microns below the pn junction or rectifying barrier. Through these unique oxide/nitride forming conditions and curvature, symmetry, and proximity effects, novel passivation and isolation results obtain.

Abstract: Certain semiconductor device structures are described in which single crystal layers of cubic Group II fluorides cover at least part of the surface of III-V semiconductor compound. The fluoride crystal has a cubic structure and may be lattice matched or lattice mismatched to the compound semiconductor substrate depending on fluoride composition. These fluoride single crystal layers are put down by a moleuclar beam epitaxy procedure using certain critical substrate temperature ranges and a particular cleaning procedure.

Abstract: Certain semiconductor device structures are described in which single crystal layers of cubic Group II fluorides cover at least part of the surface of III-V semiconductor compound. The Fluoride crystal has a cubic structure and may be lattice matched or lattice mismatched to the compound semiconductor substrate depending on fluoride composition. These fluoride single crystal layers are put down by a molecular beam epitaxy procedure using certain critical substrate temperature ranges and a particular cleaning procedure.

Abstract: A molecular beam epitaxy method of growing Ge.sub.x Si.sub.1-x films on silicon substrate is described. Semiconductor heterostructures using Ge.sub.x Si.sub.1-x layers grown on either Ge or Si substrates are described.

Abstract: The present invention deals with a semiconductor memory circuit device, in which a memory array portion of a rectangular shape consisting of semiconductor non-volatile memory elements is formed on a main surface of the semiconductor substrate, a low voltage driver circuit (decoder) is formed along a side of the memory array portion, and a high voltage driver circuit is formed along an opposite side of the memory array portion. This permits a reduction in word line length and avoids crossing of the word lines to permit increased operation speed and, particularly, increased reading speed.

Abstract: The fabrication of high performance and reliable Buried Channel Field Effect Transistor (BCFET) using Schottky gate junction and heavily doped N layers for the source and drain electrode is described. The BCFET is composed of a semi-insulating substrate in which two N layers for the drain electrodes and one N layer for the source electrode are formed in one of the semi-insulating surface. The N source electrode is centrally located between the two N drain electrodes and all three lie in the same plane. The source and drain electrodes are separated by a thin semi-insulating layer, the length of which can range from 0.5 micron to several micron range, depending on the desired voltage breakdown. A Schottky gate is defined in an active N layer directly above the source N Layer. The ohmic contacts for the source and drain N layers are defined several microns away from the schottky junction, resulting in a considerable improvement in device reliability.

Abstract: A method for manufacturing a semiconductor device of the invention comprises the steps of(a) forming a gate insulating film on a surface of a silicon substrate, and a gate electrode on said gate insulating film;(b) forming a source region and a drain region by doping said substrate with an impurity which has a conductivity type opposite to a conductivity type of said silicon substrate;(c) forming a self-aligned insulating layer on the side walls of the gate electrode;(d) forming a self-aligned metal layer on a region on which an insulating film is not formed, the region including the source region and the drain region; and(e) forming electrodes which are connected to the source region, drain region and gate electrode.

Abstract: Semiconductor components which have a plurality of layers lying on top of one another are manufactured with the assistance of a method for light-induced, photolytic deposition. Particularly, periodically alternating layers (hyperfine structure elements) and/or doping patterns are produced simultaneously with deposition of layers and/or with randomly selected doping gradients. In particular, the method is also suited for simultaneous deposition of layers lying laterally side-by-side or of laterally side-by-side differing dopings of a layer being deposited. In the context of doping, the radiation damage known from implantation is avoided.

Abstract: The invention relates to a process for the manufacture of semiconductor layers on semiconductor bodies or for the diffusion of impurities from compounds into semiconductor bodies, with fission products which are to be withdrawn during the process being formed. The gist of the invention is that the reactivity of certain fission products is increased by plasma excitation or by the supplying of photons. In particular, active hydrogen is made available for entry into a highly volatile, gaseous combination with existing fission products.

Abstract: A method for fabricating a semiconductor device in which the base resistance is minimized to increase the speed of operation of the device. This is accomplished because the device made by the method makes it possible to form the base and emitter contacts next to each other laterally but spaced vertically.

Abstract: A method of producing sheets of crystalline material is disclosed, as well as devices employing such sheets. In the method, a growth mask is formed upon a substrate and crystalline material is grown at areas of the substrate exposed through the mask and laterally over the surface of the mask to form a sheet of crystalline material. This sheet is separated, and the substrate can optionally be reused. The method has particular importance in forming sheets of crystalline semiconductor material for use in solid state devices.

Abstract: The fabrication of high performance and reliable Buried Channel Field Effect Transistor (BCFET) using Schottky gate junction and heavily doped N layers for the source and drain electrode is described. The BCFET is composed of a semi-insulating substrate in which two N layers for the drain electrodes and one N layer for the source electrode are formed in one of the semi-insulating surface. The N source electrode is centrally located between the two N electrodes and all three lie in the same plane. The source and drain electrodes are separated by a thin semi-insulating layer, the length of which can range from 0.5 micron to several micron range, depending on the desired voltage breakdown. A Schottky gate is defined in an active N layer directly above the source N layer. The ohmic contacts for the source and drain N layers are defined several microns away from the Schottky junction, resulting in a considerable improvement in device reliability.

Abstract: A high power MOSFET is disclosed in which two laterally spaced sources each supply current through respective channels in one surface of a semiconductor chip which are controlled by the same gate. The channels lead from the source electrodes to a relatively low resistivity region and from there to a relatively high resistivity epitaxially formed region which is deposited on a high conductivity substrate. The drain electrode may be either on the opposite surface of the chip or laterally displaced from and on the same side as the source regions. The epitaxially deposited semiconductor material immediately adjacent and beneath the gate and in the path from the sources to the drain has a relatively high conductivity, thereby to substantially reduce the on-resistance of the device without effecting the breakdown voltage of the device.

Abstract: The mobility of a relatively narrow bandgap semiconductor material can be significantly enhanced by incorporating it into a multilayered structure (10) comprising a first plurality of relatively narrow bandgap layers (12) of the material and a second plurality of wider bandgap semiconductor layers (14) interleaved with and contiguous with the first plurality. The wide bandgap and narrow bandgap layers are substantially lattice-matched to one another, and the wide bandgap layers are doped such that the impurity concentration-thickness product therein is greater than the same product in the narrow bandgap layers. The fabrication of the structure by MBE to enhance the mobility of GaAs is specifically described. In this case, the narrow bandgap layers (12) comprise GaAs and are unintentionally doped to about 10.sup.14 /cm.sup.3, whereas the wide bandgap layers (14) comprise AlGaAs doped n-type to about 10.sup.16 to 10.sup.18 /cm.sup.3. The incorporation of this structure in an FET is also described.