Abstract: The present invention teaches a process for fabrication of quantum-well devices, in which the quantum-wells are configured as small islands of GaAs in an AlGaAs matrix. Typically these islands are roughly cubic, with dimensions of about 100 Angstroms per side. To fabricate these, an n- on n+ epitaxial GaAs structure is grown, and then is etched to an e-beam defined patterned twice, and AlGaAs is epitaxially regrown each time. This defines the quantum wells of GaAs in an AlGaAs matrix, and output contacts are then easily formed.

Abstract: Prior to packaging, semiconductor lasers are purged by being subjected first to high temperature and high current simultaneously so as to suppress stimulated emission and stress the shunt paths which allow leakage current to flow around the active region. A prudent, but nonessential, second step is to lower the temperature and/or current so that the lasers emit stimulated emission (preferably strongly, near the peak output power), thereby stressing the active region. Lasers subjected to such a purge exhibit stabilized degradation rates in short times (of the order of a few hours) and provide a robust population which meets the performance criteria of long lifetime systems.

Abstract: A process is described for fabricating self-aligned buried doped regions in semiconductor devices and integrated circuits which avoids any need for delineation of the buried doped regions in the active portions of the device. Avoiding delineation improves the quality of the epitaxial layer used to cover the buried doped regions thereby improving overall performance and yield. Multiple mask layers are used in connection with a single mask pattern to achieve self-alignment. One mask layer consists of a material with a modifiable etch rate, e.g. polysilicon. A portion of the single crystal substrate is rendered non-single crystal and used as an alignment key which is propagated through the epitaxial layer grown over the undelineated buried doped regions. The dimensions and separations of the self-aligned buried doped regions can be precisely controlled.

Abstract: Grooves are formed in a single crystal silicon wafer in a pattern to encircle surface areas. Silicon dioxide is placed in the grooves and on the surface and then removed from certain of the areas. Layers of silicon are epitaxially grown only on these areas and their surfaces are oxidized. Polycrystalline silicon is deposited to a thickness greater than that of the epitaxial layers. Both sides of the wafer are ground and polished to produce flat, planar, opposite surfaces; one surface exposing surface areas of the epitaxial layers, the other surface exposing the silicon dioxide in the grooves. The resulting substrate has two types of silicon sections, each of which is electrically isolated from the other by silicon dioxide partitions. One type of section is of silicon of the original wafer, has a surface area in only one surface, and is suitable for the fabrication of low voltage, low power devices therein.

Abstract: An MOS device having a gate electrode and interconnect of titanium nitride and especially titanium nitride which is formed by low pressure chemical vapor deposition. In a more specific embodiment the titanium nitride gate electrode and interconnect have a silicon layer thereover to improve oxidation protection.

Abstract: The method suggests the replacement of all or part of the solid or blanket buried region, typically a subcollector region of a bipolar transistor, by a mesh or stripe shaped subcollector. During subsequent thermal processing involving growth of the epitaxial layer, the stripes will at least partially merge, resulting in a solid subcollector. The method of minimizing autodoping implies only a special design of the subcollector mask. Therefore, there is no longer any need for technological changes either in the process or in the equipment. The method also applies to other buried layers, such as, subemitters, resistors, bottom isolation regions, etc.

Abstract: In fabricating a PROM cell, an electrical isolation mechanism (44 and 32) is formed in a semiconductive body to separate islands of an upper zone (36) of first type conductivity (N) in the body. A semiconductor is introduced into one of the islands to produce a region (48) of opposite type conductivity (P) that forms a PN junction with adjacent semiconductive material of the island. Ions are implanted to convert a surface layer (60) of the region into a highly resistive amorphous form which is irreversibly switchable to a low resistance state. A path of first type conductivity extending from the PN junction through another of the islands to its upper surface is created in the body to complete the basic cell.

Abstract: A method for manufacturing semiconductor devices is presented. The method comprises the steps of opening two windows on an insulating layer covering a semiconductor substrate, and forming a polysilicon layer over the entire surface of the insulating layer and the windows. Donor and acceptor impurities are respectively implanted into the portions of the polysilicon layer corresponding to the two opening windows through the appropriate photoresists. The doped impurities are thereafter subjected to annealing to form two different conduction type regions under the two opening windows. Thereafter, a metal layer and a photoresist are deposited in order to make the metal electrodes for each conduction region. Thus, the patterning of the polysilicon can be made in self-alignment with the etching mask, and the formation of two different conduction type semiconductor regions are simultaneously attained.

Abstract: In fabricating a PROM cell, an electrical isolation mechanism (44 and 32) is formed in a semiconductive body to separate islands of an upper zone (36) of first type conductivity (N) in the body. A semiconductor impurity is introduced into one of the islands to produce a region (48) of opposite type conductivity (P) that forms a PN junction laterally bounded by the island's side boundaries. A highly resistive amorphous semiconductive layer (58) which is irreversibly switchable to a low resistive state is deposited above the region in such a manner as to be electrically coupled to the region. A path of first type conductivity extending from the PN junction through another of the islands to its upper surface is created in the body to complete the basic cell.

Abstract: A method for fabricating a wafer for a dielectric isolation (DI) integrated circuit device is provided, wherein the substrate of the wafer, comprises portions of polycrystalline silicon positioned beneath regions for electrical elements, namely, "islands", and portions of single crystal silicon are positioned in other areas of the wafer such as scribing regions, peripheral regions and contact regions. The single crystal portions of the substrate are grown during its fabricating steps by exposing surfaces of an original substrate of single crystal silicon, before the deposition of silicon onto the original substrate, by removing a dielectric isolation layer over the predetermined regions to be exposed. The single crystal silicon portions of the wafer provide various advantages for subsequent mechanical processing of the wafer such as shaping and rounding of the peripheral region and the scribing of the wafer into dice.

Abstract: A method for growing a Group II-VI epitaxial layer on a substrate, said epitaxial layer having an electron mobility greater than 1.5.times.10.sup.5 cm.sup.2 /V-sec at 77.degree. K. and a carrier concentration less than 4.times.10.sup.15 (cm.sup.-3) is described. The method includes the steps of directing a plurality of vapor flows towards the substrate including a Group II metalorganic vapor having a mole fraction in the range of 3.0.times.10.sup.-4 to 4.5.times.10.sup.-4, a Group VI metalorganic vapor having a mole fraction in the range of 2.9.times.10.sup.-3 to 3.5.times.10.sup.-3 and a Group II elemental metal vapor having a mole fraction in the range of 2.6.times.10.sup.-2 to 3.2.times.10.sup.-2. The source of Group II metal is heated to at least 240.degree. C. while radiant energy is directed toward the reactor vessel to warm the zone of the reactor vessel between the Group II metal source and the substrate to at least 240.degree. C.

Abstract: A layer of Cd.sub.x Hg.sub.1-x Te is grown on a substrate by growing layers of HgTe t.sub.1 thick, and CdTe t.sub.2 thick alternately. The thicknesses t.sub.1 and t.sub.2 combined are less than 0.5 .mu.m so that interdiffusion occurs during growth to give a single layer of Cd.sub.x Hg.sub.1-x Te. The HgTe layers are grown by flowing a Te alkyl into a vessel containing the substrate and filled with an Hg atmosphere by an Hg bath. The CdTe layers are grown by flowing of Cd alkyl into the vessel where it combines preferentially with the Te on the substrate. Varying the ratio of t.sub.1 to t.sub.2 varies the value of x. Dopants such as alkyls or hydrides of Al, Ga, As and P, or Si, Ge, As and P respectively may be introduced to dope the growing layer.

Abstract: In the fabrication of buried heterostructure InP/InGaAsP lasers, mask undercutting during the mesa etching step is alleviated by a combination of steps which includes the epitaxial growth of a large bandgap InGaAsP cap layer (1.05 eV.ltorsim.E.sub.g .ltorsim.1.24 eV) and the plasma deposition of a SiO.sub.2 etch masking layer. Alternatively, the cap layer may be a bilayer: an InGaAs layer or narrow bandgap InGaAsP (E.sub.g .ltorsim.1.05 eV), which has low contact resistance, and a thin InP protective layer which reduces undercutting and which is removed after LPE regrowth is complete. In both cases, etching at a low temperature with agitation has been found advantageous.

Abstract: An amorphous or polycrystalline film which continuously covers the exposed surface of a single crystal substrate and an insulating film, is deposited in ultra-high vacuum and then heat-treated. The film is subjected to solid phase epitaxial growth at a temperature far lower than in prior-art methods, whereby a single crystal film is formed.

Abstract: Semiconductor device, such as bipolar transistor, is made by molecular beam epitaxy, wherein a emitter layer (27) and overriding contact regions (28) of polycrystalline silicon are grown continuously on a silicon substrate (23+26) without breaking high vacuum, thus eliminating the adverse interface of natural oxide film under the polycrystalline silicon layer (28) and the adverse donor-acceptor compensation while attaining a well controlled h.sub.FE and enabling a shallow emitter junction.

Abstract: A method for the growth of a compound semiconductor comprises growing on a silicon substrate a polycrystalline layer of a desired Group III-V compound semiconductor or a crystal layer of the desired Group III-V compound semiconductor having inferior crystallinity, growing on the formed layer at least one layer of the same semiconductor as the desired Group III-V compound semiconductor and at least one layer of a Group III-V compound semiconductor having a lattice constant approximating the lattice constant of the desired Group III-V compound semiconductor, which layers are alternately disposed, and growing on the alternately disposed layers a layer of the desired Group III-V compound semiconductor.

Abstract: A sidewall-nitride isolation technology refines process control over lateral oxide encroachment by preventing any thinning of the nitride moat-masking layer during the nitride etch step which clears the sidewall nitride layer from the bottom of the etched recesses in silicon. This is done by initially patterning the moat regions in an oxide/nitride/oxide stack, rather than the nitride/oxide stack of the prior art.

Abstract: There is disclosed a process and the resulting semiconductor wafer wherein the backside of the wafer has applied thereto a layer of polysilicon. Portions of this layer are exposed to an energy beam to recrystallize them into single crystal silicon fused to and extending from the underlying wafer. The recrystallized portions contact adjacent portions of the polysilicon layer, thereby providing a path for impurities migrating from the wafer to the polysilicon.

Abstract: A method of making very pure cubic silicon carbide, SiC, comprising the steps of: loading a first inner graphite cup of a Lely type furnace while cold with a large number of crystals of SiC that are used as substrates; sealing the first cup with a graphite lid; inserting the first cup into a second graphite cup and inserting them into the furnace; filling the area between the first cup and the second cup with SiC; heating the first cup to between 2300.degree. C. and 2700.degree. C. until an atmosphere saturated with Si, C, SiC.sub.2 and Si.sub.2 C is created; and cooling the furnace quickly to a temperature less than 1800.degree. C.

Abstract: To minimize the number of independent masking operations in the manufacture of a CMOS integrated circuit device using twin tub technology, the n-tub is made by separate phosphorus and arsenic implants through a common mask, and the p-tub is made by two separate boron implants through a common mask, complementary to that used for forming the n-tub. One of the boron implants occurs before, the other after, the drive-in heating step. After tub formation, further movement of the implanted ions is kept small by use of a high pressure process for growing the field oxide and by only limited further heating. Transistors are then formed in the tubs.