Abstract: An integrated substrate structure includes a redistribution film, a circuit substrate, and a plurality of conductive features. The redistribution film includes a fine redistribution circuitry, a circuit substrate is disposed over the redistribution film and includes a core layer and a coarse redistribution circuitry disposed in and on the core layer. The circuit substrate is thicker and more rigid than the redistribution film, and a layout density of the fine redistribution circuitry is denser than that of the coarse redistribution circuitry. The conductive features are interposed between the circuit substrate and the redistribution film to be connected to the fine redistribution circuitry and the coarse redistribution circuitry. A redistribution structure and manufacturing methods are also provided.

Abstract: Provided herein are low resistance metallization stack structures for logic and memory applications and related methods of fabrication. In some embodiments, thin metal oxynitride or metal nitride nucleation layers are deposited followed by deposition of a pure metal conductor. The nucleation layer is amorphous, which templates large pure metal film grain growth and reduced resistivity. Further, certain embodiments of the methods described below convert most or all of the metal oxynitride nucleation layer to a pure metal layer, further lowering the resistivity.

Abstract: Some embodiments relate to a semiconductor structure. The semiconductor structure includes a first substrate including a first plurality of conductive pads that are laterally spaced apart from one another on the first substrate. A first plurality of conductive bumps are disposed on the first plurality of conductive pads, respectively. A multi-tiered solder-resist structure is disposed on the first substrate and arranged between the first plurality of conductive pads. The multi-tiered solder-resist structure has different widths at a different heights over the first substrate and contacts sidewalls of the first plurality of conductive bumps to separate the first plurality of conductive bumps from one another.

Abstract: A semiconductor package including: a first substrate; a first semiconductor device on the first substrate; a first mold layer covering the first semiconductor device; a second substrate on the first mold layer; a support solder ball interposed between the first substrate and the second substrate, and electrically disconnected from the first substrate or the second substrate, wherein the support solder ball includes a core and is disposed near a first sidewall of the first semiconductor device; and a substrate connection solder ball disposed between the first sidewall of the first semiconductor device and the support solder ball to electrically connect the first substrate to the second substrate, wherein a top surface of the first semiconductor device has a first height from a top surface of the first substrate, and the core has a second height which is equal to or greater than the first height.

Abstract: A method for underfilling an electronic circuit assembly may include mounting one or more structures to a substrate, mounting one or more spacers to the substrate at one or more positions, respectively, to form one or more passages between the one or more spacers and the one or more structures, dispensing underfill to the one or more passages, and curing the underfill to secure the one or more structures to the substrate. The one or more structures may include one or more dies.

Abstract: The electronic device includes a first semiconductor device having a logic circuit, a second semiconductor device having a memory circuit, and a wiring substrate to which the first and second semiconductor devices are mounted. The first semiconductor device has a plurality of terminals arranged on a main surface. The plurality of terminals includes a plurality of differential pair terminals electrically connected to the second semiconductor device and to which differential signals are transmitted. The plurality of differential pair terminals is arranged along a side of the main surface, that is extending in an X direction, and includes a first differential pair terminal constituted by a pair of terminals arranged along a Y direction orthogonal to the X direction, and a second differential pair terminal constituted by a pair of terminals arranged along the Y direction. The first and second differential pair terminals are arranged along the Y direction.

Abstract: A semiconductor package includes a first substrate, a first semiconductor chip and a passive device which are laterally spaced apart from each other on the first substrate and are disposed face-up on the first substrate, a first molding part surrounding the first semiconductor chip and the passive device on the first substrate, a second semiconductor chip disposed on the first molding part and electrically connected to the first semiconductor chip and the passive device, a second molding part surrounding the second semiconductor chip on the first molding part, first through-electrodes vertically penetrating the first molding part, at least some of first through-electrodes electrically connect the first substrate to the second semiconductor chip, and external terminals provided under the first substrate.

Abstract: Apparatuses, such as semiconductor device packages, may include, for example, a device substrate including a semiconductor material and bond pads coupled with an active surface of the device substrate. A package substrate may be secured to the device substrate, the package substrate configured to route signals to and from the bond pads. A ball grid array may be supported on, and electrically connected to, the package substrate. Each ball of the ball grid array positioned and configured to carry a clock signal or a strobe signal may be located in a central column of the ball grid array.

Abstract: The present application provides a display panel, a display module, and a display device. A flexible substrate of the display panel includes a first flexible substrate and a second flexible substrate, and the first flexible substrate is provided with a first through-hole corresponding to a lighting path of an electronic component. Based on the first through-hole, light transmittance of the display panel is increased, so that electronic components such as a camera can be disposed below the display panel, and a narrow bezel design is realized.

Abstract: A semiconductor device including: a trench defining an active region in a substrate; a first semiconductor liner formed over the trench; a second semiconductor liner formed over the first semiconductor liner; and a device isolation layer formed over the second semiconductor liner and filling the trench. Disclosed is also a method for fabricating a semiconductor device, the method including: forming a trench defining an active region in a substrate; forming a plurality of semiconductor liners over the trench; performing pretreatment before forming each of the semiconductor liners; and performing post-treatment after forming each of the semiconductor liners.

Abstract: A semiconductor package includes a package substrate; a semiconductor die mounted on a top surface of the package substrate; a plurality of conductive elements disposed on a bottom surface of the package substrate; and a land-side silicon capacitor disposed on the bottom surface of the package substrate and surrounded by the plurality of conductive elements. The land-side silicon capacitor includes at least two silicon capacitor unit dies adjoined to each other with an integral scribe line region.

Abstract: The present application discloses a semiconductor device. The semiconductor device includes a package structure including a first side and a second side opposite to the first side; an interposer structure positioned over the first side of the package structure; a first die positioned over the interposer structure; a second die positioned over the interposer structure; and a plurality of bottom interconnectors positioned on the second side of the package structure, and respectively including: a bottom exterior layer positioned on the second side of the to package structure; and a cavity enclosed by the bottom exterior layer.

Abstract: The present disclosure provides a semiconductor device and a fabrication method thereof. The semiconductor device includes a substrate, a group III-V layer disposed on the substrate, a dielectric layer disposed on the group III-V layer, and an inclined sidewall extending from the dielectric layer to the substrate. Wherein the substrate comprising a relative rough surface opposite the inclined sidewall.

Abstract: A structure of flash memory cell includes a substrate. A floating gate is disposed on the substrate. A low dielectric constant (low-K) spacer is disposed on a sidewall of the floating gate. A trench isolation structure has a base part disposed in the substrate and a protruding part above the substrate protruding from the base part. The low-K spacer is sandwiched between the floating gate and the protruding part of the trench isolation structure.

Abstract: A semiconductor device includes a die, an encapsulant over a front-side surface of the die, a redistribution structure on the encapsulant, a thermal module coupled to the back-side surface of the die, and a bolt extending through the redistribution structure and the thermal module. The die includes a chamfered corner. The bolt is adjacent to the chamfered corner.

Abstract: A semiconductor package includes a lower semiconductor chip having a lower semiconductor substrate and upper pads on a top surface of the lower semiconductor substrate, an upper semiconductor chip stacked on the lower semiconductor chip, the upper semiconductor chip including an upper semiconductor substrate and solder bumps on a bottom surface of the upper semiconductor substrate, and a curing layer between the lower semiconductor chip and the upper semiconductor chip, the curing layer including a first curing layer adjacent to the upper semiconductor chip, the first curing layer including a first photo-curing agent, and a second curing layer between the first curing layer and the top surface of the lower semiconductor substrate, the second curing layer including a first thermo-curing agent.

Abstract: A system-in-package module includes a substrate, an application specific integrated circuit (ASIC) chip on the substrate, first wafer level package (WLP) memories on the substrate spaced apart from the ASIC chip in a first direction parallel to an upper surface of the substrate, and second WLP memories on the substrate spaced apart from the ASIC chip in a direction opposite to the first direction.

Abstract: The present disclosure provides a semiconductor memory device with improved element performance and reliability. The semiconductor memory device comprises a substrate, a gate electrode extending in a first direction in the substrate, a plurality of buried contacts on the substrate, and a fence in a trench between adjacent ones of the buried contacts. The fence is on the gate electrode. The fence includes a spacer film on side walls of the trench and extending in a second direction intersecting the first direction, and a filling film in the trench and on the spacer film. An upper surface of the spacer film is lower than an upper surface of the filling film with respect to the substrate.

Abstract: The invention discloses a pattern layout of an active region and a forming method thereof. The feature of the present invention is that in the sub-pattern unit, an appropriate active area pattern is designed according to the bit line pitch (BLP) and the word line pitch (WLP), the active area pattern is a stepped pattern formed by connecting a plurality of rectangular patterns in series, and the active area pattern is arranged along a first direction, the angle between the first direction and the horizontal direction is A. In addition, according to the angle A, the shortest distance (P) between adjacent stepped patterns, the length and width of sub-pattern units, etc., The positions of some stepped active area patterns are adjusted, so that the distance between multiple active area patterns can be consistent when being repeatedly arranged, thereby improving the uniformity of overall pattern distribution.

Abstract: A semiconductor device may include active pattern, a silicon liner, an insulation layer, an isolation pattern and a transistor. The active pattern may protrude from a substrate. The silicon liner having a crystalline structure may be formed conformally on surfaces of the active pattern and the substrate. The insulation layer may be formed on the silicon liner. The isolation pattern may be formed on the insulation layer to fill a trench adjacent to the active pattern. The transistor may include a gate structure and impurity regions. The gate structure may be disposed on the silicon liner, and the impurity regions may be formed at the silicon liner and the active pattern adjacent to both sides of the gate structure.