Abstract: A power converter includes: a power module that converts direct-current electric power from a power storage apparatus and alternating-current electrical power to be supplied to a load; a charger that converts alternating-current electrical power supplied via an external connector to direct-current electric power and charges the power storage apparatus therewith; a capacitor module that is arranged between the power module and the charger and that has a capacitor that smoothes voltage; a DC/DC converter that converts direct-current voltage supplied from the power storage apparatus; and a signal line connected to the charger, wherein the power module and the capacitor module are connected by high-voltage wire on one surface side of the capacitor module, and the signal line is connected to the charger by extending via other surface of the capacitor module opposite from the one surface.

Abstract: An electric power supply system, to which the electric field coupling electric power transmission technology is applied, includes an electric power transmission electrode for transmitting electric power from an electric power source, an electric power reception electrode that is disposed so as to contactlessly face the electric power transmission electrode to form a junction capacitance, and receives the electric power transmitted from the electric power transmission electrode through the junction capacitance, and a plasma generation unit for generating a plasma in a space between the electric power transmission electrode and the electric power reception electrode in which the junction capacitance is formed.

Abstract: An apparatus is disclosed for mixer biasing with baseband filter common-mode voltage. In an example aspect, the apparatus includes a mixer, a baseband filter, and a bias circuit. The mixer has a mixer transistor that is coupled to a bias node and a baseband node. The baseband filter is coupled to the mixer via the baseband node. The baseband filter is configured to operate with a common-mode reference voltage that is associated with a common-mode voltage applied at the baseband node. The bias circuit is coupled to the baseband filter and the bias node. The bias circuit is configured to receive the common-mode reference voltage from the baseband filter and generate, at the bias node, a bias voltage for biasing the mixer transistor based on the common-mode reference voltage.

Abstract: An exemplary voltage correction circuit includes a high-pass filter coupled with an integrated load, and an active clamp coupled with the high-pass filter in a closed-loop feedback arrangement. The high-pass filter includes an impedance network having a frequency response defining a lower frequency boundary of a passband of the voltage correction circuit, and the active clamp has a frequency response defining an upper frequency boundary of the passband of the voltage correction circuit. The active clamp is adapted to receive an input voltage proportional to a load transient within the passband and to generate an output current of the voltage correction circuit that cancels the effects of the load transient. A loop gain of the voltage correction circuit is greater than or equal to one within the passband and is less than one for frequencies lower than the lower frequency boundary and higher than the upper frequency boundary.

Abstract: A technique relates to a superconducting device. A gyrator includes a first mixing device coupled to a second mixing device. A lumped-element resistor is connected in parallel to the gyrator.

Abstract: A hot swap controller circuit includes a comparator and current control circuitry. The comparator is configured to compare voltage across a power transistor controlled by the hot swap controller circuit to a predetermined threshold voltage. The current control circuitry is coupled to the comparator. The current control circuitry is configured to limit current through the power transistor to no higher than a predetermined high current based on the voltage across the transistor being less than the predetermined threshold voltage. The current control circuitry is also configured to limit the current through the transistor to be no higher than a predetermined low current based on the voltage across the transistor being greater than the predetermined threshold voltage. The predetermined high current is greater than the predetermined low current.

Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include clock circuitry having a first plurality of logic components arranged to receive a low voltage supply, a data input signal and a clock input signal and to provide a first plurality of intermediate signals and multiple intermediate clock signals. The integrated circuit may include level converter core circuitry having voltage biasing circuitry and voltage control circuitry arranged to receive a high voltage supply, the first plurality of intermediate signals and the multiple intermediate clock signals and to provide a second plurality of intermediate signals. The integrated circuit may include latch circuitry having a second plurality of logic components arranged to receive the high voltage supply, the low voltage supply and the second plurality of intermediate signals and to provide a data output signal.

Abstract: An analog circuit including a pair of input nodes and a pair of output nodes is coupled to a mismatch reduction circuit including an input node, an output node, a phase controller that times even and odd phases, an input switch, and an output switch. The input switch electrically connects the mismatch reduction circuit input node to a first node of the pair of analog circuit input nodes during each even phase and to electrically connects the mismatch reduction circuit input node to a second node of the pair of analog circuit input nodes during each odd phase. The output switch electrically connects a first node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each even phase and electrically connects a second node of the pair of analog circuit output nodes to the mismatch reduction circuit output node during each odd phase.

Abstract: A controlled transconductance circuit (CTC) is disclosed. The CTC includes (i) a transistor comprising a drain terminal, a gate terminal, and a transistor source terminal, (ii) a biasing circuit element connected between the transistor source terminal and a CTC source terminal, and a variable capacitor connected between the transistor source terminal and a constant voltage terminal where the constant voltage terminal is adapted to receive a constant voltage, and (iii) a CTC control terminal adapted to control a transconductance of the CTC by controlling a capacitance of the variable capacitor.

Abstract: A wireless power receiver is disclosed. The wireless power receiver comprises: a resonance tank for receiving magnetic resonance-type wireless power; a rectifier including a diode bridge and a first switch connected to both ends of any one diode for forming the diode bridge, so as to rectify wireless power received by the resonance tank and supply the rectified wireless power to a load; and a controller controlling the first switch so as to operate the rectifier as a full-wave rectifier or a half-wave rectifier.

Abstract: Described is an apparatus which comprises: a driver comprising a push-pull transmitter; a first circuitry to sense variation in a power supply; and a second circuitry coupled to the first circuitry and to the driver, the second circuitry to generate a code according to an output of the first circuitry, wherein the code is provided to the driver to adjust a performance parameter of the driver.

Abstract: A gate control circuit for a tristate output buffer operating in a first voltage domain includes a pull-up circuit coupled between an upper rail and a first gate control signal, a pull-down circuit coupled between a lower rail and a second gate control signal, and a gate isolation switch coupled between the first gate control signal and the second gate control signal. The gate isolation switch includes a first PMOS transistor coupled in parallel with a first NMOS transistor. The first NMOS transistor is controlled by a first enable signal and the first PMOS transistor is controlled by a second enable signal.

Abstract: An aircraft jet propulsion system is disclosed. The aircraft jet propulsion system may comprise a thermoelectric generator array (“TEG” array) coupled to a portion of the aircraft jet propulsion system, wherein the TEG array converts heat energy to electrical energy, and supplies power to the aircraft jet propulsion system, wherein the electrical energy is supplied to a power supply. The aircraft jet propulsion system may comprise an alternator that generates less energy than is required to power the aircraft jet propulsion system. The TEG array may supplement the energy generated by the alternator. The energy generated by the TEG array and the energy generated by the alternator may be sufficient to power the aircraft jet propulsion system and/or the electrical energy generated by the TEG array may be sufficient to power to aircraft jet propulsion system.

Abstract: Provided is a wireless power supply control system including a control apparatus controlling driving of one or more driving devices in accordance with a plurality of predetermined driving patterns, a first radio having a directional antenna, and a second radio driven by power supply radio waves transmitted from the first radio. Target driving directivity information corresponding to a target driving pattern acquired by an acquisition unit is selected from among pieces of driving directivity information relating to a directivity applied to the directional antenna, in a state in which driving of the driving devices is controlled by the control apparatus in accordance with the driving patterns, the selected target driving directivity information is applied to the directional antenna of the first radio, and wireless power supply from the first radio to the second radio is executed.

Abstract: An input/output circuit includes a first switch element, a control voltage providing circuit and a floating voltage providing circuit. The first switch element includes a control terminal, a first path terminal, a second path terminal and a base terminal. The first path terminal receive a first voltage, and the second path terminal receives a second voltage. The control voltage providing circuit provides a control voltage to the control terminal of the first switch element. The floating voltage providing circuit provides the larger between the first voltage and the second voltage to the base terminal of the first switch element, so as to prevent a leakage current from being generated between the first voltage source or the second voltage source and the base terminal of the first switch element.

Abstract: Disclosed is a voltage generator that includes a first voltage generation circuit and a second voltage generation circuit. The first voltage generation circuit is selectively operable in a single trimming mode enabling positive trimming only or in a dual trimming mode that shifts the voltage range downward enabling a somewhat smaller amount of positive trimming and also some negative trimming. The second voltage generation circuit is selectively operable in a single trimming mode enabling negative trimming only or in a dual trimming mode that shifts the voltage range upward enabling a somewhat smaller amount of negative trimming and also some positive trimming. Also disclosed is an integrated circuit (IC) chip that incorporates one or more such voltage generators for back-biasing the field effect transistors in one or more circuit blocks, respectively.

Abstract: A bandgap reference circuit including a clamp circuit is provided. The bandgap reference circuit performs the calibration only for one time in a normal mode to store a control code of a reference generator of the clamp circuit. In a suspend mode, the control code is used for controlling the reference generator to cause the clamp circuit to provide a desired source voltage, and a bandgap reference voltage source is shut down to reduce the power consumption.

Abstract: A hybrid energy storage system is configured to control pulsed power. A first dynamo-electric machine is coupled to an inertial energy storage device and has multiple input stator windings configured to accept input power from a source. A polyphase output stator winding is configured to deliver electric power having a first response time to a DC bus. A secondary energy storage system is coupled to the DC bus and is configured to convert its stored energy to electric power in a bidirectional manner. A second dynamo-electric machine has an input stator winding and at least one polyphase output stator winding coupled to a converter, the converter coupled to a DC output. A polyphase boost exciter is configured to derive energy from the DC bus and excite the second machine input stator winding, wherein the second machine is configured to be excited at a faster rate than the first response time of the first machine.

Abstract: A bidirectional clock synchronization circuit is provided. The circuit includes a bidirectional port having an input/output terminal and a transceiver, having a first interface with a unidirectional input and a unidirectional output, and a second interface with a bidirectional input/output coupled to the input/output terminal of the bidirectional port. The circuit includes a phase locked loop (PLL), having an output coupled to the unidirectional input of the transceiver, and having an input coupled to the unidirectional output of the transceiver, the phase locked loop selectable as to frequency range for the input or the output of the phase locked loop.

Abstract: In some examples, a control circuit is configured to control a transistor, and the control circuit includes a leading-edge detection unit configured to detect a time interval that corresponds to a leading-edge current spike through the transistor, wherein the time interval is independent of temperature. In some examples, the control circuit also includes a blanking unit configured to prevent the control circuit from turning off the transistor during the time interval.