Abstract: According to certain aspects, a driver includes an output transistor coupled between a first rail and an output of the driver, a first current source coupled to a gate of the output transistor, a second current source, and a switch, wherein the switch and the second current source are coupled in series between the gate of the output transistor and a second rail. The driver also includes a current sensor configured to generate a sense current based on an output current of the driver, and a reference current source configured to generate a reference current, wherein the current sensor and the reference current source are coupled to a control input of the switch.

Abstract: An electronic device having multiple power output circuits that individually include a switch control input, a bypass control input, an output transistor and an output control circuit that includes an RC circuit with a resistor and a capacitor coupled to the output transistor gate and a bypass switch in parallel with the RC circuit resistor. The electronic device includes a controller that selects one of the power output circuits for a given power transfer cycle, closes the bypass switch to bypass the resistor of the selected power output circuit and turns the output transistor of the selected power output circuit on to transfer current from the inductor to a load of the selected power output circuit.

Abstract: A zero-crossing detection circuit includes a zero-crossing detection unit arranged to compare a first monitoring target signal and a second monitoring target signal respectively input through diodes from a first node and a second node between which an AC signal is applied, so as to generate a first comparison signal, and a logic unit arranged to estimate a zero cross of the AC signal from the first comparison signal so as to generate a zero-crossing detection signal. The zero-crossing detection circuit preferably includes a monitoring unit arranged to adjust the first monitoring target signal and the second monitoring target signal to be suitable for input to the zero-crossing detection unit. The logic unit preferably counts a period of the first comparison signal and estimates a zero cross of the AC signal using a count value thereof.

Abstract: Circuits and systems for generating counter signals are provided herein. A circuit may comprise a shift register having a series of flip-flops. Each of the flip-flops of the series may be coupled to a clock. The shift register may generate a borrowing clock signal using an output of a flip-flop of the shift register, and a transition of the borrowing clock signal may be advanced by a number of clock cycles based on a position of the flip-flop of the shift register. The circuit may further comprise a clock divider circuit having a number of divide-by-N counters and a number of flip-flops. A divide-by-N counter may be coupled to a flip-flop of the shift register, and a flip-flop of the clock divider circuit may be coupled to one of the divide-by-N counters and to the clock.

Abstract: According to embodiments of the present invention, a circuit is provided. The circuit includes a first set of transistors configured to receive one or more input signals provided to the circuit, and a second set of transistors electrically coupled to each other, wherein the second set of transistors is configured to provide one or more output signals of the circuit, wherein the first set of transistors and the second set of transistors are electrically coupled to each other, and wherein, for each transistor of the first set of transistors and the second set of transistors, the transistor is configured to drive a load associated with the transistor and has an aspect ratio that is sized larger than an aspect ratio of a transistor that is optimized for driving the load.

Abstract: An embodiment power-on-reset circuit, having a power supply input to receive a power supply voltage, generates a reset signal with a value switching upon the power supply voltage crossing a POR detection level. The power-on-reset circuit has: a PTAT stage having a left branch and a right branch and generating a current equilibrium condition between the currents circulating in the left and right branches upon the power supply voltage reaching the POR detection level; and an output stage coupled to the PTAT stage and generating the reset signal, with the value switching at the occurrence of the current equilibrium condition for the PTAT stage. The power-on-reset circuit further comprises a detection-level generation stage, coupled to the PTAT stage as a central branch thereof to define the value of the POR detection level.

Abstract: A wireless power system has a wireless power transmitting device and a wireless power receiving device. The wireless power transmitting device may be a wireless charging mat or other device with coils for transmitting wireless power signals. The wireless power receiving device may be a cellular telephone or other device with coils for receiving the transmitted wireless power signals. The wireless power receiving device has adjustable rectifier circuitry coupled to a pair of coils. The pair of coils is coupled in series at a node. A transistor is coupled between ground and the node and is controlled by control circuitry. The state of the transistor can be changed to place the adjustable rectifier circuitry in either a first mode of operation in which the adjustable rectifier circuitry forms a full-bridge rectifier or a second mode of operation in which the adjustable rectifier circuitry forms a pair of parallel half-bridge rectifiers.

Abstract: According to one embodiment, an electronic device includes processor circuitry. The processor circuitry is configured to control detection module to execute a first carrier sense by performing at least one of phase control and amplitude control corresponding to a first beam pattern for a received wireless signal, and execute a second carrier sense by performing at least one of phase control and amplitude control corresponding to a second beam pattern for the received wireless signal, and supply power by an electromagnetic wave with the first beam pattern based on a result of the first carrier sense, and control power supply module to supply power by an electromagnetic wave with the second beam pattern based on a result of the second carrier sense.

Abstract: A switching element 1 has a gate terminal connected to an output end 123 of a driving circuit 12 via a capacitor 11 and a resistor 13 connected in parallel. The switching element 1 has a source terminal connected to the driving circuit 12 via a capacitor 14. A diode 15 connected in series with a resistor 16 has a cathode terminal connected to a section between the capacitor 11 and the resistor 13, and the gate terminal and an anode terminal connected, via the resistor 16, to a section between the source terminal and the capacitor 14.

Abstract: A 15-level multilevel inverter circuit includes an outer circuit, an inner circuit, a polarity changing circuit and a computing device. The outer circuit and the inner circuit include a plurality of DC voltage supplies. Each DC voltage supply has a positive and a negative terminal. The outer circuit, the inner circuit and the polarity changing circuit include a plurality of unidirectional power switches. Each unidirectional power switch is a transistor with a diode connected in parallel to the transistor. The computing device is configured to provide control signals to the gates of the plurality of the unidirectional power switches of the outer circuit and the inner circuit to add or subtract the voltage of each of inner DC voltage supplies to form square waveforms approximating sinusoidal waveforms, and to the gates of the plurality of the unidirectional power switches of the polarity changing circuit to switch the polarity of the voltage.

Abstract: A low distortion triangular wave generator circuit generates a triangular wave signal by performing integration on an integration capacitor via a charging current and a discharging current during a charging period and a discharging period within a switching period of an external clock signal. A time length of the charging period is identical to a time length of the discharging period. A common mode related signal related to a common mode characteristic of the triangular wave signal is generated. An adjusting signal is generated according to a difference between the common mode related signal and a predetermined DC (direct current) level. The adjusting signal adjusts at least one of the charging current and the discharging current via feedback mechanism such that the triangular wave signal is a symmetrical triangular wave, and an average voltage of the triangular wave signal is equal to a target DC level.

Abstract: A switching control circuit that controls switching of a switching device of a bridge circuit for driving a load. The switching control circuit includes a control circuit that outputs, on a signal line, a control signal at first and second logic levels for turning on and off the switching device based on a set signal and a reset signal, respectively, a setting circuit that is connected to the signal line, and that sets the logic level of the signal line to the second logic level for a period after the reset signal is inputted to the control circuit and before the set signal is inputted to the control circuit, a holding circuit that is connected to the signal line, and that holds the logic level of the signal line, and a drive circuit that is connected to the holding circuit, and that drives the switching device based on the output of the holding circuit.

Abstract: A transmit resonator is provided. The transmit resonator comprises: two inductors; a switching network electrically connected to the inductors; a plurality of capacitive electrodes electrically connected to the switching network; a detector communicatively connected to the capacitive electrodes; and a controller communicatively connected to the switching network and the detector. The detector is configured to detect impedance. The controller is configured to control the switching network to control which electrodes are connected to the inductors based on the detected impedance. The inductors and electrodes are configured to resonate to generate an electric field.

Abstract: A sensor arrangement to sense an external signal comprises a sensor (100) and a charge generator (200) to generate a compensation current (Ic) to compensate the sensor current. A charge generator (200) comprises a first transistor (210) having a parasitic capacitor (212) and a first conductive path. The charge generator (200) comprises a second transistor (220) having a second conductive path being coupled in series to the first transistor (210) and coupled to the output node (O200) of the charge generator (200). The control circuit (600) is configured to control the conductivity of the respective first and second conductive path of the first and the second transistor (210, 220) of the charge generator (200) so that the sensor current is compensated by the compensation current (Ic).

Abstract: A driving circuit includes a plurality of differential amplifier circuits each electrically connected to a power supply line. Each differential amplifier circuit includes a differential pair circuit and a series resistance circuit. In the differential pair circuit, a first transistor and a second transistor are electrically connected to the power supply line through a first load resistor and a second load resistor, respectively. A center node is electrically connected between the first transistor and the second transistor. Each differential amplifier circuit generates a differential output signal in accordance with a differential incoming signal. The series resistance circuit includes a resistor and a line element. The line element includes a signal line which extends straight with a distance between the signal line and a ground line extending in parallel thereto. The resistor and the line element are connected in series between the center node and a static potential line.

Abstract: A transmit resonator is provided. The transmit resonator comprises: at least two inductors; at least one switching network electrically connected to one inductor of the at least two inductors; at least one secondary capacitive electrode electrically connected to the switching network; at least one main capacitive electrode electrically connected to one inductor of the at least two inductors; and a controller electrically connected to the switching network. The controller is configured to control the switching network to control connection of the secondary capacitive electrode to one inductor of the at least two inductors via the switching network. The inductors and electrodes are configured to resonate to generate an electric field.

Abstract: For near field communications, inductive coils coupled to each communicating circuit are brought close together so that there is inductive coupling between the two coils. Data signals can then be relayed between the two circuits without any direct connection between them. However, the system is susceptible to common mode noise, such as ambient EMI. In addition to the “active” coil pairs used for transmitting and receiving data, a pair of “passive” coils is provided, proximate to the active coil pairs, that is only used for detecting the ambient EMI. The EMI signals detected by the passive coils are processed by a noise detector/processor, and the noise detector processor then controls the transmitters and/or receivers to at least partially compensate for the detected EMI signals. Transmit power or receiver thresholds may be controlled by the noise detector/processor to improve the signal-to-noise ratio, or other compensation techniques can be used.

Abstract: An internal latch circuit having a plurality of low initial value D flip-flops, a plurality of high initial value D flip-flops, an internal latch signal generating circuit and a NAND gate, and a method for generating latch signal thereof is provided. First, an input delay signal in response to a clock signal is generated. Then, a first internal input signal, a first reverse internal input signal, a second internal input signal, and a second reverse internal input signal are generated by using the low initial value D flip-flops and the high initial value D flip-flops, based on the internal data strobe signal and in response to the input delay signal, and are transmitted to the internal latch signal generating circuit. Then, the internal latch signal generating circuit outputs the first reverse pre-output signal and the second reverse pre-output signal. Finally, an internal latch signal is generated through a NAND gate.

Abstract: A multi-voltage, high voltage I/O buffer in low-voltage technology is disclosed. In one embodiment, the I/O buffer includes a logic circuit configured to generate a signal based on a data signal and a first control signal. A level shifter is coupled between a supply voltage terminal and a ground terminal, and the level shifter is generates first and second output signals in first and second voltage domains, respectively, at first and second nodes, respectively, based on the signal from the logic circuit. A control circuit is coupled between the second node and a third node. The control circuit transmits the second output signal to the third node when the first control signal is asserted, and the control circuit couples the third node to the ground terminal when the first control signal is not asserted.

Abstract: A power distribution device includes an input, an output, a power switch controller, and a voltage isolation device. The power distribution device includes, and is designed to provide power to, for example, non-radiation-tolerant or non-radiation hardened components for use in low Earth orbit (LEO) missions. The input is configured to receive power from a power source. The output is configured to provide the power to an electrical load. The power switch controller is configured to selectively operate the power distribution device in a first mode responsive to a first event, and to selectively operate the power distribution device in a second mode responsive to a second event. The voltage isolation device includes a plurality of switches configured, in the first mode, to pass the power between the input and the output, and, in the second mode, to interrupt the passage of the power between the input and the output.