Abstract: This disclosure describes a non-dissipative snubber circuit configured to boost a voltage applied to a load after the load's impedance rises rapidly. The voltage boost can thereby cause more rapid current ramping after a decrease in power delivery to the load which results from the load impedance rise. In particular, the snubber can comprise a combination of a capacitive element, two inductive elements, and three switches, where a duty cycle of two of the three switches controls the voltage boost. The snubber can be arranged between a DC power supply and a switching circuit configured to generate a pulsed waveform for provision to the load.

Abstract: A system-on-a-chip includes a first digital domain and a second digital domain. An interface circuit includes a level-shifting circuit for converting a signal between the first digital domain and the second digital domain. The first digital domain includes a control circuit configured to generate a control signal for transmission to the second digital domain. The control signal includes a pulse having a nominal duration adapted to the level-shifting circuit. At the input of the level-shifting circuit, the interface circuit includes, in the first domain, a conditional pulse-stretching circuit that lengthens a duration of the pulse of the control signal to at least the nominal duration when a duration of the pulse of the control signal is shorter than the nominal duration and non-zero.

Abstract: Wireless power transfer systems, disclosed, include one or more circuits to facilitate high power transfer at high frequencies. Such wireless power transfer systems include a damping circuit, configured to dampen a wireless power signal such that communications fidelity is upheld at high power. The damping circuit includes at least a damping transistor that is configured to receive, from the transmitter controller, a damping signal for switching the transistor to control damping during transmission of amplitude shift keying (ASK) wireless data signals. Utilizing such systems enables wireless power transfer at high frequency, such as 13.56 MHz, at voltages over 1 Watt, while maintaining fidelity of in-band communications associated with the higher power wireless power signal.

Abstract: Described herein are related to a device for communication. In one aspect, the device a first circuit configured to generate a signal. In one aspect, the device includes a port. In one aspect, the device includes a set of switches. Each switch of the set of switches may be coupled in parallel between the first circuit and the port. In one aspect, the device includes a second circuit configured to enable a subset of the set of switches, according to an amplitude of the signal.

Abstract: A motion sensing system uses high-voltage biasing to achieve high resolution with ultra-low power. The motion sensing system consists of a motion sensor, a readout circuit, and a high-voltage bias circuit to generate the optimized bias voltage for the motion sensor. By using the high-voltage bias, the signal from the motion sensor is raised above the readout circuit's noise floor, eliminating the power-hungry amplifier and signal-chopping used in conventional motion sensing systems. The bias circuit, while producing the programmable bias voltages for the motion sensor, also compensates for the process mismatch raised by the high voltage biases.

Abstract: A sample and hold amplifier output buffer with the low leakage of metal oxide semiconductor field effect transistors (MOSFET) combined with the linearity and dynamic range of silicon-germanium (SiGe) bipolar junction transistors (BJT). In one aspect, the present disclosure provides a sample and hold amplifier output buffer placing a MOSFET input device between the base and emitter of a high linearity SiGe BJT.

Abstract: An electrical circuit includes a MOSFET and an electronic driver circuit for driving the MOSFET, having four pins, the electrical circuit including at least one electrical track to which the MOSFET is connected by a bond wire having an intrinsic inductance. The electronic driver circuit is connected to the MOSFET by a first terminal directly linked to the first source and, in parallel, by a second terminal linked to the second source. The bond wire is arranged between the second terminal and the second source. The electronic driver circuit is configured so as to apply an electrical driver signal between the gate and the first source or between the gate and the second source of the MOSFET, in order to trigger a change of state of the MOSFET to the OFF state or to the ON state, respectively.

Abstract: An electronic device may include a low drop output regulator (LDO); a first DC-to-DC converter; an antenna module including an antenna array IC and an antenna array; a second DC-to-DC converter disposed outside the antenna module and supplying power to the low drop output regulator; a power generation circuit for supplying power to the first DC-to-DC converter and the second DC-to-DC converter; and a processor operatively coupled to the antenna module, the second DC-to-DC converter, and the power generation circuit.

Abstract: Certain aspects are directed to apparatus and methods for signal integrity monitoring. The method generally includes: receiving a data signal; generating a first set of delayed versions of the data signal via a plurality of delay elements; comparing each of the first set of delayed versions of the data signal with a clock signal; and generating an output signal based on the comparison.

Abstract: An electronic circuit for controlling a power switch having a gate input, includes a signal generator configured to generate a gate driver input signal. The gate driver input signal has a first voltage during a first period of time, a second voltage during a second period of time, and toggles between the first voltage and the second voltage during a third period of time. The electronic circuit also includes a gate driver configured to receive the gate driver input signal and to provide a gate driver output signal based on the gate driver input signal. The signal generator is configured to cause the gate driver input signal to toggle during the third period of time such that the gate driver output signal has a third voltage during the second period of time, and an intermediate voltage that is less than the third voltage during the third period of time.

Abstract: A semiconductor device includes a first transistor, a first drive circuit including a second transistor, and a second drive circuit including a third transistor. The second transistor and the third transistor are connected in series; and a connection node of the second and third transistors is connected to a gate electrode of the first transistor. The first transistor, the second transistor, and the third transistor are normally-off MOS HEMTs formed in a first substrate that includes GaN. The first drive circuit charges a parasitic capacitance of the first transistor. The second drive circuit discharges the parasitic capacitance of the first transistor.

Abstract: A digital phase shift circuit includes: a signal line extending in a predetermined direction; two inner lines disposed on both one side and another side of the signal line and separated a predetermined distance from the signal line; two outer lines provided at positions which are farther from the signal line than the inner lines on both the one side and the other side; a first grounding conductor electrically connected to one end of each of the inner lines and the outer lines; and a second grounding conductor electrically connected to other ends of the outer lines, and the predetermined distance is set to be less than 10 ?m.

Abstract: A device, a method and a storage medium for accelerating activation function in relation to data processing by artificial neural network provides a register for storing a storage table, a matching unit including a plurality of comparators, a logic unit, and a selection unit. The comparators compare an input variable of the activation function with the variable intervals of the activation function to obtain a comparison output result, the logic unit performs a logical operation according to the comparison output result to obtain a logic output result and determines a variable interval to be calculated according to the logic output. The selection unit queries the storage table according to the variable interval to be calculated and obtains parameters of fitted quadratic function. A calculation unit performs calculations on the input variable according to the parameters.

Abstract: Embodiments relate to a cascode diode circuit. The cascode diode circuit comprises a normally on transistor, a low voltage diode and a high voltage diode. The normally on transistor has a gate, a drain, and a source. The low voltage diode has a cathode connected to the source of the normally on transistor and an anode connected to the gate of the normally on transistor. The high voltage diode has a cathode connected to a node between the normally on transistor and the low voltage diode, and an anode connected the drain of the normally on transistor.

Abstract: A filter circuit for use with a system configured to be coupled with an electrical load, the filter circuit comprising a first filter, wherein the first filter is configured to receive a first voltage and provide an output voltage, the output voltage being the first voltage after filtering by the first filter, and the filter circuit is configured to adjust the bandwidth of the first filter in response to a load transient.

Abstract: Aspects of the subject disclosure may include, for example, an inner clock generation circuit, including: a selectable frequency divider having: a ring of tri-state inverters; a reset gate on an output of each tri-state inverter in the ring; and a reset circuit comprising one or more selectable flip-flops; and a duty-cycle limiter that generates clock signals having a 25% duty cycle from three out of four quadrature clock signals. Other embodiments are disclosed.

Abstract: Wireless power transfer systems, disclosed, include one or more circuits to facilitate high power transfer at high frequencies. Such wireless power transfer systems include a transmission integrated circuit which includes a damping circuit and a transmitter controller, configured to dampen a wireless power signal such that communications fidelity is upheld at high power. The damping circuit includes at least a damping transistor that is configured to receive, from the transmitter controller, a damping signal for switching the transistor to control damping during transmission of the wireless data signals. Utilizing such systems enables wireless power transfer at high frequency, such as 13.56 MHz, at voltages over 1 Watt, while maintaining fidelity of in-band communications associated with the higher power wireless power signal.

Abstract: In one example, a method comprises: receiving a voltage from a power converter, and generating a comparison result representing a comparison between the voltage and a voltage threshold. The method further comprises providing one of a first current reference or a second current reference to the power converter responsive to the comparison result, in which the first and second current references represent different current levels.

Abstract: A system is disclosed. The system includes a first circuit that includes a first receiver configured to receive a wireless power input, a first conductor, and operably coupled to the first receiver, and a switch network operably coupled to the first conductor configured to rectify the wireless power input and generate a rectified voltage. The first circuit further includes a first field effect transistor operably coupled to the first conductor and configured to receive a portion of the wireless power input from the first conductor and output an output voltage back to the first conductor based upon a gate input.

Abstract: An integrated circuit device includes: a Buck converter; and a control circuit for the Buck converter, which includes: a comparator configured to compare a feedback voltage of the Buck converter with a reference voltage that increases from a first voltage to a second voltage; a pulse-width modulator configured to generate a pulse-width modulated (PWM) signal having a timing-varying pulse width proportional to the reference voltage; an AND gate configured to generate a first control signal by performing a logic AND operation on an output of the comparator and the PWM signal; a pulse generator configured to generate a second control signal by generating a pulse in response to a rising edge in the output of the comparator; and a selection circuit configured to, based on an output voltage of the Buck converter, select the first control signal or the second control signal as a control signal for the Buck converter.