Abstract: The present invention relates to a wireless power transmission device formed so as to wirelessly transmit power to a wireless power reception device, wherein the wireless power transmission device comprises: a first coil formed so as to transform a current into a magnetic field; and a first metal member formed so as to cover at least a portion of the first coil, and, in the present invention, the first metal member changes an emission direction of a magnetic field formed in the first coil so as to allow the power to reach the wireless power reception device which is positioned on a side surface of the wireless power transmission device.

Abstract: The present disclosure describes aspects of a sub-device field-effect transistor architecture for integrated circuits. In some aspects, an integrated field-effect transistor (FET) is implemented with multiple FET sub-devices. During operation, source-side FET sub-devices of the integrated FET may operate in the linear region instead of in saturation. Operating in the linear region, the source-side FET sub-devices of the integrated FET may exhibit less threshold voltage or current sensitivity than other drain-side FET sub-devices that operate in saturation. A device layout of the integrated FET may be designed such that the less sensitive source-side FET sub-devices surround or protect the other more sensitive drain-side FET sub-devices from random variations or density issues at edges of the device layout. By so doing, a threshold voltage or current sensitivity of the integrated FET may be reduced, resulting in improved matching between integrated FET devices.

Abstract: A diving circuit drives an output transistor according to a control signal SCTRL. The gate of the first transistor is biased. The source of the first transistor is coupled to an internal line. In the on period of the output transistor, the voltage of the internal line is applied to a control electrode of the output transistor. A voltage correction circuit controls the internal line so as to gradually lower the voltage VREGB of the internal line with time.

Abstract: A charge pump controller for controlling a charge pump adapted to convert an input voltage into an output voltage with a conversion ratio is presented. The charge pump is operable in a plurality of modes corresponding to different conversion ratios. The controller includes a first selector for selecting a mode of operation of the charge pump. The first selector comprises a first input for coupling to a voltage supply; and a second input for coupling to a source signal. The first selector identifies a target value of the output voltage. The selector calculates a product of the conversion ratio and the input voltage. The selector compares the product with the target value and selects a mode of operation of the charge pump by increasing or decreasing the conversion ratio based on the comparison. The selector maintains the conversion ratio for a length of time before decreasing the conversion ratio.

Abstract: An apparatus and a method for generation and adaptive regulation of body bias voltages of an integrated circuit efficiently generates control voltages for active body biasing The apparatus includes a digital circuit, a counter, a control unit and at least one charge pump. The control unit and the digital circuit are connected in a closed control loop, and the digital circuit comprises at least one hardware performance monitor to monitor a timing of a body bias voltage. The control loop is formed by a control path comprising the at least one charge pump, the hardware performance monitor and the control unit. The charge pump is controllably connected to the control unit to adjust the charge pump for generation and adaptive regulation of the body bias voltage according to a timing frequency difference between an output signal of the hardware performance monitor and a reference clock signal.

Abstract: A switching control circuit has a detector to detect a difference between a control object signal of a switching element to drive a load and a target signal of the control object signal, and gate adjustment circuitry to search for the timing at which the difference becomes the smallest by sweeping timing of adjustment of a gate signal of the switching element.

Abstract: A switch circuit and a high-speed multiplexer-demultiplexer are provided. The switch circuit includes an equalization module and an MOS transistor. A gate of the first MOS transistor is connected to an output terminal of the equalization module. An input terminal of the first MOS transistor is connected to a signal source. An output terminal of the first MOS transistor is connected to a subsequent circuit. The equalization module is configured to: supply a turning-on signal to the first MOS transistor in a case that an operation signal is acquired, to turn on the first MOS transistor; and generate a compensation signal for compensating an attenuation of the signal transmitted through the first MOS transistor, and apply the compensation signal to the gate of the first MOS transistor. The switch circuit operates in response to the operation signal.

Abstract: An isolated insulated gate bipolar transistor (IGBT) gate driver is provided which integrates circuits, in-module, to support the measurements of threshold voltage, and collector-emitter saturation voltage of IGBTs. The measured gate threshold and collector-emitter saturation voltage can be used as precursors for state of health predictions for IGBTs. During the measurements, IGBTs are biased under specific conditions chosen to quickly elicit collector-emitter saturation and gate threshold information. Integrated analog-to-digital converter (ADC) circuits are used to convert measured analog signals to a digital format. The digitalized signals are transferred to a micro controller unit (MCU) for further processing through serial peripheral interface (SPI) circuits.

Abstract: In accordance with an embodiment, a method includes performing an analog-to-digital conversion on a signal at an input pin of an integrated circuit using an analog-to-digital converter having a first input range, monitoring the signal at the input pin using a first comparator having a first threshold outside of the first input range, operating the integrated circuit in a first mode when the signal at the input pin is within the first input range, and operating the integrated circuit in a second mode different from the first mode when the signal at the input pin is outside of the first input range and crosses the first threshold.

Abstract: In one embodiment, an apparatus includes a first stage comprising a first active switch, a first resonant inductor, and a resonant capacitor and a second stage comprising a second active switch, a second resonant inductor, and a filter capacitor. The first and second stages form a non-isolated multi-resonant converter for converting a DC input voltage to a DC output voltage.

Abstract: A slew-rate-control (SLC) circuit is coupled to an input for a driver circuit to provide a first binary value when the circuit is powered on and to control a slew rate when a pass element controlled by the driver circuit is enabled. The SLC circuit includes a capacitor node for coupling to a first terminal of an external capacitor, the capacitor node being coupled to the input. The SLC circuit also includes a SLC element coupled between the input and a first source of voltage to define the slew rate and a reset FET coupled between the input and a second source of voltage. The reset FET's gate is controlled by an over-current-protection signal that changes binary value when a short is detected.

Abstract: For near field communications, inductive coils coupled to each communicating circuit are brought close together so that there is inductive coupling between the two coils. Data signals can then be relayed between the two circuits without any direct connection between them. However, the system is susceptible to common mode noise, such as ambient EMI. In addition to the “active” coil pairs used for transmitting and receiving data, a pair of “passive” coils is provided, proximate to the active coil pairs, that is only used for detecting the ambient EMI. The EMI signals detected by the passive coils are processed by a noise detector/processor, and the noise detector processor then controls the transmitters and/or receivers to at least partially compensate for the detected EMI signals. Transmit power or receiver thresholds may be controlled by the noise detector/processor to improve the signal-to-noise ratio, or other compensation techniques can be used.

Abstract: Disclosed herein are voltage driver circuits and methods of operating the same. In some embodiments, a plurality of circuit slices are provided in a voltage driver circuit, each circuit slice is controlled to switchably connect a driver output to either a high voltage level or a low voltage level via a resistor, or to disconnect the driver output from both voltage levels. The circuit slices may provide an adjustable output impedance, which may be set to match the impedance of different loads. The circuit slices may also provide adjustable voltages with low power consumption, particularly in high speed applications. A calibration procedure is disclosed herein to generate a lookup table for how to selectively connect circuit slices to supply voltages given a target output voltage.

Abstract: A load switch circuit implemented on an IC chip includes a first node for coupling to an input voltage, a second node for coupling to an external load, first and second capacitor nodes for coupling to first and second terminals of an external capacitor, and a first PFET coupled between the first node and the second node to control an output voltage to the external load. The load switch circuit also includes a driver circuit having a first NFET that has a drain coupled to the first node and a source coupled to a gate of the first PFET. A slew-rate-control circuit is coupled to a gate of the first NFET and includes the first capacitor node, which is coupled to the gate of the first NFET, and the second capacitor node, which is coupled to the second node.

Abstract: Disclosed is a multi-chip module (MCM) with redundant chip-to-chip communication connection(s) to minimize the need to discard a chip-mounting layer due to defective signal traces. The MCM includes at least first and second chips mounted on the chip-mounting layer. The chip-mounting layer includes signal traces that are electrically connected between first and second links on the first and second chips, respectively, to form communication connections including at least one redundant communication connection. Instead of being directly connected to the chip-to-chip communication connections, first and second interfaces on the first and second chips are connected via first and second multiplexors, respectively, to selected ones of multiple chip-to-chip communication connections. By employing the multiplexors and the redundant chip-to-chip communication connection(s), chip-to-chip communication connection(s) with defective signal trace(s) can be bypassed.

Abstract: A dual output power supply including: a first power conversion unit for generating a first DC output voltage to drive a first load according to a DC input voltage; a second power conversion unit for generating a second DC output voltage to drive a second load according to the DC input voltage; a switching unit having two channel ends coupled to the first DC output voltage and the second DC output voltage respectively; a load power measurement unit for measuring a sum of power of the first load and the second load; and a digital microcontroller unit coupled to the switching unit and the load power measurement unit for determining a switching signal to drive a control terminal of the switching unit according to the sum of power.

Abstract: An automotive battery system that includes a lead-acid battery electrically coupled to a first bus, in which the lead-acid battery supplies electrical power to a starter via the first bus to cold crank an internal combustion engine of a vehicle; a lithium-ion battery electrically coupled to a second bus, in which the lithium-ion battery captures and stores electrical energy generated by a regenerative braking system when the vehicle brakes and supplies electrical power to the second bus using the electrical energy captured from the regenerative braking system such that a first portion of the second electrical power is supplied to an electrical system; and a DC/DC converter electrically coupled between the first bus and the second bus, in which the DC/DC converter controls supply of a second portion of the second electrical power to charge the lead-acid battery.

Abstract: A method and apparatus for performing duty cycle correction with read/write calibrations is disclosed. A first calibration is performed in a memory subsystem having a memory and a memory controller. The first calibration includes conveying a first clock signal from the memory controller to the memory, and determining the duty cycle of the first clock signal. If the duty cycle is not within a specified range, the duty cycle is adjusted and the process repeated. After the duty cycle of the first clock signal is within the specified range, a second calibration is performed, the second calibration including conveying a second clock signal from the memory to the memory controller. The duty cycle of the first clock signal may be further adjusted based on the second calibration.

Abstract: A latch comparator which includes a preamplifier and a latch circuit. The preamplifier circuit operates amplification on a pair of differential input signals, and generates a pair of pre-amplified differential signals. The latch circuit receives the pre-amplified differential signals, compares the pair of pre-amplified differential signals, and generates a pair of latched comparison signals. The latch circuit includes a latch and a switch circuit. First and second input terminals of the latch receive the pre-amplified differential signals. The switch circuit includes a switch coupling between one of the first and second input terminals of the latch and the preamplifier circuit. The switch receives one of the pair of latched comparison signals as a control signal, and is switched in response to the one of the latched comparison signal.

Abstract: A circuit includes an input circuit, a level shifter circuit, an output circuit and a feedback circuit. The input circuit is coupled to a first voltage supply, and configured to receive a first input signal, and to generate a second input signal. The level shifter circuit is coupled to the input circuit, and configured to receive an enable signal, the first input signal or the second input signal, and to generate a first signal responsive to the enable signal or the first input signal. The output circuit is coupled to the level shifter circuit, and is configured to receive the first signal, and to generate an output signal or a set of feedback signals responsive to the first signal. The feedback circuit is coupled to the level shifter circuit and output circuit, and is configured to receive the enable signal or the set of feedback signals.