Abstract: An apparatus, including: an integrator including a first input and a second input; and a switched-capacitor, comprising: a first capacitor; a first multi-slope switching circuit coupled to a first plate of the first capacitor; a first switching device coupled between a second plate of the first capacitor and a common mode node; a second switching device coupled between the second plate of the first capacitor and the first input of the integrator; a second capacitor; a second multi-slope switching circuit coupled to a first plate of the second capacitor; a third switching device coupled between a second plate of the second capacitor and the common mode node; and a fourth switching device coupled between the second plate of the second capacitor and the second input of the integrator.

Abstract: The present invention provides a fractional frequency divider, wherein the fractional frequency divider includes a plurality of registers, a counter, a control signal generator and a clock gating circuit. Regarding the plurality of registers, at least a portion of the registers are set to have values The counter is configured to sequentially generate a plurality of counter values, wherein the plurality of counter values correspond to the at least a portion of the registers, respectively, and the plurality of counter values are generated repeatedly The control signal generator is configured to generate a control signal based on the received counter value and the value of the corresponding register. The clock gating circuit is configured to refer to the control signal to mask or not mask an input clock signal to generate an output clock signal.

Abstract: Methods and devices to address antenna termination in absence of power supplies within an electronic circuit including a termination circuit and a switching circuit. The devices include regular NMOS devices that decouple the antenna from the switching circuit in absence of power supplies while the antenna is coupled to a terminating impedance having a desired impedance value through a native NMOS device. The antenna is coupled with the switching circuit via the regular NMOS device during powered conditions while the antenna is decoupled from the terminating impedance.

Abstract: A clock control device for a serial peripheral interface is disposed in a control device. The clock control device includes: a local delay module configured to delay a local clock signal to obtain a first delayed local clock signal; a clock selector configured to select one of the first delayed local clock signal and an external clock signal as a basic clock signal; and a first delay module configured to phase-delay the basic clock signal to obtain a delayed basic clock signal that can be used by the control device as a reception operating clock for sampling an external data signal transmitted by a storage device.

Abstract: According to one embodiment, an input circuit is connected to an output circuit that outputs an output value based on a first voltage and a second voltage, to which the first voltage and the second voltage are applied. The input circuit includes: a first differential transistor section including a plurality of first transistors connected in parallel with each other; a second differential transistor section including a plurality of second transistors connected in parallel with each other; and a selectable cutoff section capable of selecting a state in which a current is cut off. The output circuit includes a first current path section and a second current path section arranged in parallel with each other between ground and a power supply voltage wiring. The first differential transistor section and the second differential transistor section are arranged in parallel with each other between the ground and the power supply voltage wiring.

Abstract: A circuit incudes: a first transistor; a capacitor; a second transistor; and a second resistor. The first transistor has a current terminal and a first control terminal. The capacitor has a capacitor terminal coupled to the current terminal of the first transistor. The second transistor has a first current terminal, a second current terminal, and a second control terminal. The first current terminal of the second transistor is coupled to the capacitor terminal. The second current terminal of the second transistor is coupled to the first control terminal. The resistor has a resistor terminal coupled to the second control terminal.

Abstract: A multi-reference voltage generator, comprising: a current source; a set of resistors coupled in series with the current source between an upper voltage rail and a lower voltage rail; a first set of switching devices coupled between a first output and a set of taps at respective terminals of the set of resistors, wherein the set of taps includes a first tap and a second tap; a second set of switching devices coupled between a second output and the set of taps, respectively; a switching device coupled between the first tap and the second tap; and a control circuit including an output coupled to a control input of the switching device.

Abstract: A semiconductor integrated circuit device includes: a zero-crossing detection unit configured to compare a first monitoring target signal and a second monitoring target signal respectively input through diodes from a first node and a second node between which an AC signal is applied, so as to generate a comparison signal; a logic unit configured to count a period of the comparison signal and estimate a zero-cross of the AC signal using the count value, so as to generate a zero-crossing detection signal; and a monitoring unit configured to adjust the first monitoring target signal and the second monitoring target signal to be suitable for input to the zero-crossing detection unit, where a first chip, in which the monitoring unit is integrated, is cut out in a rectangular shape having a substantially equal ratio between a short side and a long side in a plan view.

Abstract: A filter circuit includes: a magnetic material core having a hollow hole through which a conductor line can be inserted; a wound wire wound around the magnetic material core through the hollow hole of the magnetic material core; and a variable impedance unit that is connected with the wound wire, and has impedance that is variable depending on a current or a voltage induced from the conductor line to the wound wire.

Abstract: A power detector for detecting the RMS power of an AC voltage includes a transconductor configured to receive the AC voltage and to provide a first current to a node with a non-linear relation between the first current and the voltage. A current output digital to analog converter is configured to receive a digital signal and to provide a second current to the node. A low pass filter is coupled to the node, and an inverter is coupled to the node and configured to provide a binary signal.

Abstract: A clock generation circuit performs a delay-locked operation on a reference clock signal. The clock generation circuit is configured to perform the delay-locked operation by comparing the phases of a division reference clock signal and a feedback clock signal. After the delay-locked operation is completed, the clock generation circuit is configured to selectively invert the phase of the division reference clock signal by comparing the phases of the division reference clock signal and the delay feedback clock signal.

Abstract: The control circuit comprises an oscillator generating one or more clock pulse trains with variable clock periods, based on one or more load currents at the output end of the charge pump. The one or more clock pulse trains generated by the oscillator are trimmed based on output from a time-to-voltage converter and a comparator providing information on low load current. Power consumption by a dynamic comparator is reduced at low load current, wherein the dynamic comparator is triggered by the one or more clock pulse trains having variable clock periods.

Abstract: According to an embodiment, a system is proposed for predicting future drain-to-source resistance values of a power metal-oxide-semiconductor field-effect transistor (MOSFET). The system includes a current sensing circuit configured to extract a drain current of the power MOSFET during a transient or switching phase of the power MOSFET; a conditioning circuit configured to extract a drain-to-source voltage of the power MOSFET during the transient or switching phase of the power MOSFET; and a machine learning model configured to receive the drain current and the drain-to-source voltage of the power MOSFET as inputs, and determine future drain-to-source resistance values of the power MOSFET using the machine learning model based on the extracted drain current and the drain-to-source voltage of the power MOSFET, wherein a fault condition of the power MOSFET is signaled in response to the predicted future drain-to-source resistance values exceeding a threshold.

Abstract: According to some embodiments, a load powering circuit includes a power circuit having a power semiconductor device, a mirror circuit connected to power semiconductor device and configured to generate a mirror current signal based on current flowing through the power semiconductor device, and a drain switch having an input connected to a drain of the power semiconductor device, and a driver circuit having an amplifier having a first input terminal and a second input terminal connected to the mirror circuit, and a gate control terminal connected to the power semiconductor device, the mirror circuit, and the drain switch, wherein the drain switch has an output connected to a negative reference terminal of the amplifier, and a voltage supply terminal is connected to a positive reference terminal of the amplifier.

Abstract: Systems, structures, packages, circuits, and methods provide high-side gate driver circuits configured to control operation of high-side power (switching) transistors without use of external bootstrap capacitors. A high-side driver can include three sections, including a pull-up section, first pull-down section, and a second pull-down or Miller clamp section. The gate drivers can include a charge pump circuit and can avoid use of bootstrap capacitors and related circuitry. Partitioned gate drivers can include an individual pull-up section, an individual first pull-down section, and an individual second pull-down section for each of multiple high-side power transistors.

Abstract: Glitch detection is provided for a clock signal in a semiconductor integrated circuit (IC), for example between an input buffer and a Phase Locked Loop (PLL). A first pulse signal is generated in response to a rising edge of the clock signal, and a second pulse signal is generated in response to its falling edge. A third pulse signal is generated at a predetermined period of time after a start of the first pulse signal, and a fourth pulse signal is generated at a predetermined period of time after a start of the second pulse signal. A glitch in the clock signal is indicated based on the third pulse signal having an opposite logical level to the clock signal, and/or based on the fourth pulse signal having the same logical level as the clock signal.

Abstract: A method comprises receiving an input clock signal having a clock frequency band between a lower frequency limit value and an upper frequency limit value, dividing the clock frequency band in a set of frequency ranges having a set of frequency limit values that include the lower frequency limit value and the upper frequency limit value, comparing the frequency of the clock signal with the set of frequency limit values to produce comparison indicators having a first logic value when the measured frequency fails to exceed at least one frequency limit value and having a second logic value when the measured frequency exceeds the at least one frequency limit value, and, as a result of at least one of the logic values of comparison indicators having the second logic value, producing a global flag signal indicating that the measured frequency falls outside of a frequency range.

Abstract: Ground impedance may have adverse effects on the performance of RF circuits that employ shunt switches. The disclosed methods and devices address this issue. The methods and devices involve the use of a switch to remove a decoupling capacitor from an RF circuit on an integrated circuit (IC) pin where the storage cap is connected; or modifying the turn-on threshold of an electrostatic discharge protection device (ESD) on the IC pin with the storage cap present to reduce susceptibility to turning on the ESD with the RF signal; or de-Qing the analog and digital core capacitances to minimize their contribution to resonance; or a combination thereof.

Abstract: Described is circuitry (200) for driving a power switching device (226), the circuitry (200) comprising: a control circuit (211) in a first power domain configured to generate a first power domain PWM pulse signal (208a, 208b, 208c, 208d) in response to received PWM pulse data (207a, 207b, 207c, 207d) that encodes a PWM waveform, the first power domain PWM pulse signal (208a, 208b, 208c, 208d) being synchronous with a system clock signal (210); an isolation coupler (214, 218a, 218b, 218c, 218d) between the first power domain and a second power domain configured to generate a second power domain PWM pulse signal (209a, 209b, 209c, 209d) in response to the first power domain PWM pulse signal (208a, 208b, 208c, 208d); and a drive circuit (212) in the second power domain configured to drive the power switching device (226) with a voltage input (201, 202, 203, 225) in response to the second power domain PWM pulse signal (209a, 209b, 209c, 209d).

Abstract: A clock signal frequency divider according to one aspect of the present disclosure includes: an output signal generation circuit configured to generate, from pulses of a received input clock signal, an output clock signal including a repetition of a periodic pattern signal in which a pulse of a mask pulse number is masked among consecutive pulses of a periodic pulse number, the periodic pattern signal including a marker portion including at least one unmasked pulse at a start portion of the periodic pattern signal; and an output circuit configured to output the output clock signal, wherein the output signal generation circuit generates the periodic pattern signal in such a way that a pattern of a timing of the at least one unmasked pulse of the marker portion does not appear in a portion other than a portion corresponding to the marker portion in the output clock signal.