Abstract: A method for operating a wireless power transmission system includes providing a driving signal for driving a transmission antenna of the wireless power transmission system, the driving signal based, at least, on an operating frequency for the wireless power transmission system. The method further includes inverting, by the at least one transistor, a direct current (DC) input power signal to generate an AC wireless signal at the operating frequency, based on provided driving signals. The method includes receiving, at a damping circuit, damping signals configured for switching the damping transistor to one of an active mode and an inactive mode to control signal damping, wherein the damping signals switch to the active mode periodically. The method further includes selectively damping, by the damping circuit, the AC wireless signals, during transmission of the wireless data signals if the damping signals set the damping circuit to the active mode.

Abstract: A power drive circuit includes a power conversion module, a plurality of gate drivers, a waveform processing unit, a control unit, a weighting unit, and a comparator. Each gate driver includes a drive resistance setting value. The waveform processing unit outputs a current absolute value waveform of an AC power. The weighting unit generates a trigger voltage. When the comparator determines that the current absolute value waveform is greater than the trigger voltage, the comparator outputs a slew rate control signal to each of the gate drivers. When the gate driver receives the slew rate control signal, each of the gate drivers decreases the drive resistance setting value of the gate driver.

Abstract: A circuit, which might be a full-bridge driver circuit, comprises a first PMOS high-side transistor device and a first NMOS low-side transistor device. The circuit further comprises turn-on circuitry configured to turn on the first PMOS high-side transistor device while simultaneously turning on the first NMOS low-side transistor device, by routing charge stored in a gate of the first PMOS high-side transistor device to a gate of the first NMOS low-side transistor device, to charge the gate of the first NMOS low-side transistor device.

Abstract: Wireless power transfer systems, disclosed, include one or more circuits to facilitate high power transfer at high frequencies. Such wireless power transfer systems include a transmission integrated circuit which includes a damping circuit and a transmitter controller, configured to dampen a wireless power signal such that communications fidelity is upheld at high power. The damping circuit includes at least a damping transistor that is configured to receive, from the transmitter controller, a damping signal for switching the transistor to control damping during transmission of the wireless data signals. Utilizing such systems enables wireless power transfer at high frequency, such as 13.56 MHz, at voltages over 1 Watt, while maintaining fidelity of in-band communications associated with the higher power wireless power signal.

Abstract: The present specification relates to a wireless power transmission device. The present specification provides a wireless power transmission device comprising: a power supply unit for supplying power to the wireless power transmission device; at least one first coil for transmitting power to a wireless power reception device; and first and second condensers configured so as to be connected respectively to different both ends of the power supply unit and the first coil.

Abstract: An embodiment of the present description concerns a method wherein a time of beginning of a periodic step of activation of a near-field communication circuit of a first device, charged in near field by a second device, is adjusted according to a frequency of an electromagnetic field emitted by the second device.

Abstract: A controller includes a ramp circuit and control logic. The ramp circuit includes: ramp generation circuitry having a first control input and a first current output; ramp adjustment circuitry having a second control input and a second current output; current scaling circuitry having a first current input, a current sense output and an offset current output, the first current input coupled to the first and second current outputs; and ramp completion circuitry having a current sense input and a completion output, the current sense input coupled to the current sense output. The control logic has a third control input and first and second control outputs. The third control input is coupled to the completion output. The first control output is coupled to the first control input. The second control output is coupled to the second control input.

Abstract: The present disclosure discloses a zero-crossing detection circuit, including: a zero-crossing judgment circuit, configured to detect a zero-crossing signal; and an energy storage capacitor, connected to the zero-crossing judgment circuit in parallel, wherein the energy storage capacitor is configured to provide excitation current for the zero-crossing judgment circuit.

Abstract: Switch circuits for electrical power are formed of a hybrid coupler configured to receive a signal as an input, and output first and second pulsed wave signals along first and second signal paths, respectively; in a plurality of time frames, wherein the phases of the first and second pulsed wave signals along first and second signal paths are aligned. The switch circuits may be incorporated in time folding power circuits as an exemplary application.

Abstract: A driver circuit includes an output terminal adapted for driving a data signal through a coupling capacitor to an external device. A first transistor is employed to drive the signal, and an N-type metal-oxide semiconductor (NMOS) transistor couples power to the first transistor. The NMOS transistor includes a first terminal connected to a positive terminal of a voltage supply, a second terminal coupled to an output terminal through a termination resistor, a gate terminal, and a bulk terminal connected to the negative terminal of the voltage supply. A charge pump circuit supplies a voltage to a gate terminal of the NMOS transistor, and is operable to provide a first voltage higher than that of the voltage supply to activate the NMOS device, and, responsive to detecting a ramp-down of the supply voltage, transition to providing the supply voltage to the NMOS device gate terminal.

Abstract: A power supply output device converts an input from a DC-DC converter into a bipolar voltage output that is supplied to a gate driver circuit driving a power switch. The power output supply device includes a clamping circuit that sets the voltage values of the bipolar voltage output at a predetermined voltage through switching of one or more switching elements. The power supply output device allows shunting of a high current on the negative side so that the required bipolar voltage output is reached very rapidly.

Abstract: According to one embodiment, a coupler includes first to fourth capacitors, first and second inductors, and a first Josephson junction. The first capacitor includes a first capacitor end portion and a first capacitor other-end portion. The first inductor includes a first inductor end portion, and a first inductor other-end portion. The second inductor includes a second inductor end portion, and a second inductor other-end portion. The first Josephson junction includes a first Josephson junction end portion, and a first Josephson junction other-end portion. A space is surrounded with the first inductor, the second inductor, and the first Josephson junction. The third capacitor includes a third capacitor end portion, and a third capacitor other-end portion. The fourth capacitor includes a fourth capacitor end portion, and a fourth capacitor other-end portion.

Abstract: A zero-crossing detection circuit includes a zero-crossing detection unit arranged to compare a first monitoring target signal and a second monitoring target signal respectively input through diodes from a first node and a second node between which an AC signal is applied, so as to generate a first comparison signal, and a logic unit arranged to estimate a zero cross of the AC signal from the first comparison signal so as to generate a zero-crossing detection signal. The zero-crossing detection circuit preferably includes a monitoring unit arranged to adjust the first monitoring target signal and the second monitoring target signal to be suitable for input to the zero-crossing detection unit. The logic unit preferably counts a period of the first comparison signal and estimates a zero cross of the AC signal using a count value thereof.

Abstract: A wireless power system has a wireless power transmitting device and a wireless power receiving device. The devices in the wireless power system may communicate using in-band communication. The wireless power transmitting device may transmit data to the wireless power receiving device using frequency-shift keying (FSK) modulation. The wireless power receiving device may transmit data to the wireless power transmitting device using amplitude-shift keying (ASK) modulation. While transmitting data to the wireless power receiving device using FSK modulation, the wireless power transmitting device may monitor for ASK modulation from the wireless power receiving device. In response to detecting the ASK modulation from the wireless power receiving device, the wireless power transmitting device may abort the FSK data transmission and process the detected ASK modulation to receive data from the wireless power receiving device.

Abstract: A voltage stabilizer is provided for stabilizing a gate-source voltage of a switching element, wherein a source of the switching element receives a first driving voltage. The voltage stabilizer includes a bipolar junction transistor, a first resistor and a second resistor. A base of the bipolar junction transistor receives a second driving voltage, a collector of the bipolar junction transistor is electrically connected to a gate of the switching element, a first terminal of the first resistor is electrically connected to the collector and the gate, a second terminal of the first resistor is electrically connected to the source of the switching element and receives the first driving voltage, a first terminal of the second resistor is electrically connected to an emitter of the bipolar junction transistor, and a second terminal of the second resistor receives a third driving voltage The bipolar junction transistor is operated in an active region.

Abstract: A power converter includes a first contact, a second contact, a third contact, a fourth contact, a first ground contact, a second ground contact, a transformer, and a first switching element to a fifth switching element. The first switching element to the fifth switching element is controllable to switch on or off to form a first configuration and a second configuration, wherein the first configuration allows a power input to the first contact to be transmitted to the third contact through a first side of the transformer, and the second configuration allows a power input to the second contact to be transmitted to the fourth contact through the first side to a second side of the transformer, thereby to distribute the DC power in the same circuit structure.

Abstract: A portable battery pack and portable electronic device communicate by pulsing (turning on/off) their respective battery chargers causing variations in a magnetic field between the battery pack and portable electronic device that can be used to transmit and receive short messages through their respective coils using a magnetic communication protocol. Data or messages can be transferred between portable battery pack and portable electronic device when the portable battery pack and portable electronic device are in a mated configuration. The magnetic communication protocol allows for bi-directional communication of various battery status indicators and other data from the portable battery pack to the portable electronic device and vice-versa.

Abstract: The present disclosure relates to a driving control circuit, method and device for a gallium nitride (GaN) transistor, and a medium. An ADriver pin and an electronic switch are added to an existing flyback power supply circuit. The electronic switch includes a first terminal connected to the ADriver pin, a second terminal connected between a driving resistor and a GaN transistor, and a third terminal connected between a current detection resistor and a current sense pin. By improving the driving control circuit and the driving control method for the GaN transistor, the present disclosure can effectively prevent the false turn-on problem due to high-frequency oscillation between the leakage inductance of the transformer and the parasitic capacitance after the GaN transistor is turned off, and drives the GaN transistor more reliably.

Abstract: A clock generation circuit, equidistant four-phase signal generation method and memory are provided. The circuit includes: a four-phase clock generation circuit for receiving an internal clock signal and complementary clock signal of a memory to which the clock generation circuit belongs, configured to generate a first, second, third and fourth clock signals with the same cycle; a signal delay circuit configured to perform signal delay on the first clock signal, second clock signal, third clock signal and fourth clock signal respectively based on the delay command, herein the delays of the first clock signal, second clock signal, third clock signal and fourth clock signal are different; a signal loading circuit configured to generate a first indication signal and second indication signal; and a test circuit configured to perform a duty cycle test based on the first indication signal and second indication signal to acquire equidistant parallel clock signals.

Abstract: The present invention provides a fractional frequency divider, wherein the fractional frequency divider includes a plurality of registers, a counter, a control signal generator and a clock gating circuit. Regarding the plurality of registers, at least a portion of the registers are set to have values The counter is configured to sequentially generate a plurality of counter values, wherein the plurality of counter values correspond to the at least a portion of the registers, respectively, and the plurality of counter values are generated repeatedly The control signal generator is configured to generate a control signal based on the received counter value and the value of the corresponding register. The clock gating circuit is configured to refer to the control signal to mask or not mask an input clock signal to generate an output clock signal.