Abstract: A transistor is formed in an active area having a segmented gate structure. The segmented gate structure advantageously provides for dynamic control of a channel region formed within the transistor. Lightly doped source and drain (LDD) regions are formed aligned to a gate electrode. After forming an insulating layer adjacent the exposed surfaces of the gate electrode, conductive spacers are formed disposed overlying the LDD regions. These spacers are electrically isolated from the gate electrode by the insulating layer. Heavily doped source and drain (S/D) regions are formed which are aligned to the spacers and make electrical contact, for example through a salicide process, supplied to the conductive spacer, the gate electrode, and the S/D regions. The described structure advantageously supplies dynamic control of the channel region through dynamic, independent control of the LDD portions of the S/D regions.

Abstract: Using a mask opening a gate region, an undoped GaAs layer is selectively etched with respect to an undoped Al0.2Ga0.8As layer by dry etching with introducing a mixture gas of a chloride gas containing only chlorine and a fluoride gas containing only fluorine (e.g. BCl3+SF6 or so forth). By about 100% over-etching is performed for the undoped GaAs layer, etching (side etching) propagates in transverse direction of the undoped GaAs layer. With using the mask, a gate electrode of WSi is formed. Thus, a gap in a width of about 20 nm is formed by etching in the transverse direction on the drain side of the gate electrode. By this, a hetero junction FET having reduced fluctuation of characteristics of an FET, such as a threshold value, lower rising voltage and higher breakdown characteristics is obtained.

Abstract: A field-effect-controllable vertical semiconductor component, and a method for producing the same, include a semiconductor body having at least one drain region of a first conduction type, at least one source region of the first conduction type, at least one body region of a second conduction type between the drain regions and the source regions, and at least one gate electrode insulated from the entire semiconductor body by a gate oxide. A gate terminal and a drain terminal are located on a front side of the wafer, and a source terminal is located on a rear side of the wafer. A monolithically integrated half bridge with a low-side switch and a high-side switch includes the field-effect-controllable vertical semiconductor component and a conventional field-effect-controllable vertical semiconductor component.

Abstract: A semiconductor device includes a substrate, a semiconductor chip for emitting light, and a reflector enclosing the semiconductor chip for reflecting the light emitted from the semiconductor chip. The substrate is provided with a first electrode and a second electrode each electrically connected with the semiconductor chip. A transverse cross-section of the reflector defines an elongated figure, such as oblong, elliptical, rhombic or rectangular.

Abstract: An image pickup element unit and peripheral circuits are formed on a common semiconductor substrate. The image pickup element unit comprises sensors which converts incident lights into charges. The peripheral circuits comprise contact holes therein and transfer signals to external components via the contact holes. A tungsten film which works as both a photo shield and a barrier metal film is formed on the semiconductor substrate so that each of the sensors has its opening portion and the contact holes are filled with the tungsten film. An aluminum film which works as wiring is formed on the tungsten film filing the contact holes. A tungsten silicide layer is formed at conjunction portion between the tungsten film in the contact holes and the semiconductor substrate. Contacts comprising the tungsten film and the tungsten silicide layer show excellent ohmic contact characteristics.

Abstract: A hybrid memory device combines a ferromagnetic layer and a Hall Effect device. The ferromagnetic layer is magnetically coupled to a portion of a Hall plate, and when such plate is appropriately biased, a Hall Effect signal can be generated whose value is directly related to the magnetization state of the ferromagnetic layer. The magnetization state of the ferromagnetic layer can be set to correspond to different values of a data item to be stored in the hybrid memory device. The magnetization state is non-volatile, and a write circuit can be coupled to the ferromagnetic layer to reset or change the magnetization state to a different value. The memory device can also be fabricated to include an associated transistor (or other suitable switch) that functions as an isolation element to reduce cross-talk and as a selector for the output of the device when such is used in a memory array.

Abstract: A process for fabricating a highly stable and reliable semiconductor, comprising: coating the surface of an amorphous silicon film with a solution containing a catalyst element capable of accelerating the crystallization of the amorphous silicon film, and heat treating the amorphous silicon film thereafter to crystallize the film.

Abstract: Semiconductor device according to the present invention includes package frame, bonding wire, pad, first internal power supply line, second internal power supply line, internal circuit, stabilize circuit, GND package frame, GND bonding wire, GND pad, and internal GND line. Bonding wire, pad, and first and second internal power supply lines and function as a filter. As a result, noise generated by operation of internal circuit is absorbed in propagating to stabilize circuit through first internal power supply line, pad, and second internal power supply line. Therefore, effects of noise given to stabilize circuit is small.

Abstract: A PIN photodiode comprising a p region containing a p type dopant, an n region containing an n type dopant, an i region positioned intermediate the p region and the n region, and a relatively thick, undoped buffer region positioned between the n region and the i region which substantially decreases the capacitance of the PIN photodiode such that the photodiode bandwidth is maximized. Typically, the buffer region is formed as a layer of indium phosphide that is at least approximately 0.5 &mgr;m in thickness.

Abstract: An imaging device formed as a CMOS semiconductor integrated circuit includes a buried contact line between the floating diffusion region and the gate of a source follower output transistor. The self-aligned buried contact in the CMOS imager decreases leakage from the diffusion region into the substrate which may occur with other techniques for interconnecting the diffusion region with the source follower transistor gate. Additionally, the self-aligned buried contact is optimally formed between the floating diffusion region and the source follower transistor gate which allows the source follower transistor to be placed closer to the floating diffusion region, thereby allowing a greater photo detection region in the same sized imager circuit.

Abstract: The present invention relates to a semiconductor hetereostructure radiation detector for wavelengths in the infrared spectral range. The semiconductor heterostructure radiation detector is provided with an active layer composed of a multiplicity of periodically recurring single-layer systems each provided with a potential well structure having at least one quantum well with subbands (quantum well), the so-called excitation zone, which is connected on one side to a tunnel barrier zone, whose potential adjacent to the excitation zone is higher than the band-edge energy of a drift zone adjoining on the other side of the potential-well structure.

Abstract: There is provided a hetero-junction field effect transistor including (a) a first semiconductor layer composed of InP, (b) a second semiconductor layer formed on the first semiconductor layer, the second semiconductor layer having a smaller electron affinity than that of the first semiconductor layer, (c) a third semiconductor layer formed on the second semiconductor layer, the third semiconductor layer having a greater electron affinity than that of the second semiconductor layer, and being formed at a surface thereof with an opening, the third semiconductor layer being composed of InP, (d) source and drain electrodes formed on the third semiconductor layer, and (e) a gate electrode formed on the second semiconductor layer in the opening of the third semiconductor layer. In accordance with the hetero-junction field effect transistor, it is possible to enhance noise characteristic and high power characteristic.

Abstract: In one aspect, the invention provides a semiconductor sensor which includes a first single crystal silicon wafer layer. A single crystal silicon structure is formed in the first wafer layer. The structure includes two oppositely disposed substantially vertical major surfaces and two oppositely disposed generally horizontal minor surfaces. The aspect ratio of major surface to minor surface is at least 5:1. A carrier which includes a recessed region is secured to the first wafer layer such that said structure is suspended opposite the recessed region.

Abstract: A method for making a ULSI MOSFET chip includes forming the gate of a transistor on a silicon substrate, covering the gate with a SiON protective layer, and then implanting a pre-amorphization high dose Si or Ge implant into the substrate. Next, dopant is pre-implanted into the substrate to promote subsequent formation of source and drain extensions, with the SiON layer protecting the gate from the pre-amorphization high dose Si or Ge and from the dopant. Undoped polysilicon and polygermanium is then deposited onto the substrate adjacent the gate at relatively low temperatures (600° C.) to establish elevated source and drain regions without excessively thermally stressing the chip. The SiON layer is removed from the gate, and the gate and elevated source and drain regions are implanted with dopant, followed by rapid thermal annealing to form the source and drain extensions in the substrate below the gate. The gate and elevated source and drain regions are then silicidized.

Abstract: The pressure sensor component has a chip carrier carrying a semiconductor chip with an integrated pressure sensor having a pressure-detecting surface exposed to the pressure to be measured. A device encapsulation made from an electrically insulating material surrounds the entire assembly except for protruding electrode terminals. Bond wires connect the electrode terminals with the pressure sensor and/or the electronic circuit of the semiconductor chip. The device encapsulation consists entirely of a homogeneous pressure-transmitting medium comprising an enveloping compound, which transmits the pressure to be measured as free from delay and attenuation as possible but is mechanically resistant and dimensionally stable. The pressure to be measured is transmitted directly by the enveloping compound onto the pressure-detecting surface of the semiconductor chip, and the pressure sensor and/or the pressure sensor component is covered tightly on all sides against mechanical and/or chemical influences.

Abstract: The present invention provides a fingerprint sensor chip formed on a dielectric layer of a semiconductor wafer. The fingerprint sensor chip comprises a plurality of rectangular sensor areas arranged in a matrix format which are surrounded by conductors, a second dielectric layer covering the sensor areas and the conductors wherein the surface of the second dielectric layer positioned above each of the sensor areas is formed as a protruding rectangular platform with a shallow trench around the platform, a rectangular metal plate positioned on top of each of the rectangular platforms which is used as a sensor plate of the fingerprint sensor chip, and a protective layer positioned on the surface of the semiconductor wafer to cover and protect the underlying circuitry.

Abstract: A surface voltage sustaining structure for semiconductor device which includes at least one high-side high-voltage device, comprises at least two surface voltage sustaining regions, wherein a first surface voltage sustaining region is for sustaining a voltage drop from a high voltage terminal of the high-side high-voltage device to a floating voltage terminal of the high-side high-voltage device, and a second surface voltage sustaining region is for sustaining a voltage drop from said high voltage terminal or from said floating voltage terminal to the substrate. The potential of the floating-voltage terminal of the high-side high-voltage device can vary (float) from the potential of the substrate up to the potential of the high voltage terminal.

Abstract: The invention is a Pseudomorphic transistor structure having a semiconductor layer having a 2DEG layer therein, a Schottky layer, a transition layer and an ohmic contact layer on the transition layer, wherein a double recess structure is disposed through the ohmic layer onto the transition layer in which one or two layers of InyGa1−yP are used as etch-stop layers to define the depth of the recess.

Abstract: The present invention relates to a heterojunction structure based upon the oxide/high-k dielectric barrier. In exemplary embodiment, a silicon layer has a silicon dioxide layer thereon, and a high-k dielectric material disposed on the oxide layer. Thereafter, a metal layer, serving as the gate metal for the device is disposed on the high-k dielectric. The silicon dioxide layer has a relatively high barrier height, but has a relatively small thickness, and relative to the high-k dielectric, the barrier height differential fosters real space transfer. In this structure, the high barrier height of the silicon dioxide layer results in higher mobility and thereby greater substrate current. By virtue of the relative thick layer of high-k dielectric, leakage current is significantly reduced.

Abstract: A multilayer mirror includes a multilayer reflection structure formed of an alternate repetition of a first epitaxial layer of a first refractive index and a second epitaxial layer of a second refractive index larger than the first refractive index, wherein the second epitaxial layer includes a group III-V mixed crystal containing N as a group V element.