Abstract: A method for making a metal-insulator-semiconductor field effect transistor (MISFET) having an oxidized aluminum nitride gate insulator formed on a silicon or gallium nitride or other substrate. The method of making the MISFET comprises the steps of depositing an aluminum nitride layer on the entire upper surface of the silicon or gallium nitride or other substrate. Subsequently, the aluminum nitride layer is oxidized to convert it into an oxidized aluminum nitride layer which acts as a gate insulator of the MISFET. Portions of the oxidized aluminum nitride layer are etched to form a plurality of openings that expose regions to become the source and drain regions of the substrate. The source and drain regions are formed in the plurality of openings by conventional techniques including diffusion and ion-implantation. Finally, a metal layer is formed in the plurality of openings of the oxidized aluminum nitride layer, wherein the metal layer contacts the source and drain regions of the substrate.

Abstract: A substantially continuously graded composition silicon oxycarbide (SiOC) antireflective coating (ARC) or antireflective layer (ARL) is interposed between a photoresist layer and an underlying substrate. The ARC matches an optical impedance at the interface between the ARC and photoresist. The optical impedance decreases (absorptivity increases) substantially continuously, in the ARC in a direction away from the interface between the ARC and the photoresist. The ARC composition is graded from SiOC, at its interface with the photoresist, to SiC or Si, in a direction away from the photoresist. Reflections at the ARC-photoresist interface are substantially eliminated. Substantially all incident light, including ultraviolet (UV) and deep ultraviolet (DUV) light, is absorbed in the ARC. As a result, substantially no light reaches or is reflected from the underlying substrate. Photolithographic limitations such as swing effect and reflective notching are reduced.

Abstract: A lateral conduction MOS structure characterized by reduced source resistance and reduced pitch. The structure includes a semiconductor substrate having an epitaxial semiconductor layer thereon, the substrate and epitaxial layer being of the same conductivity type. The structure further includes a source layer and a drain layer, each layer being of a second conductivity type, and a channel layer disposed between the source layer and the drain layer. The channel layer has an oxide layer and a gate disposed thereon. At least one of a wet anisotropic and a reactive ion etching step is performed to define a trench having a maximum width of about from 4-6 microns and a depth that extends well into the substrate. An electrically conductive via is then formed by deposition of metal into the trench to thereby establish a low resistance path between the source and the substrate ground.

Abstract: A semiconductor device includes a Schottky layer, a cap layer covering the surface of the Schottky layer, and a Schottky electrode of a two-level structure. The Schottky electrode has a lower portion that penetrates through the cap layer and reaches the Schottky layer, and has an upper portion larger than the lower portion in cross-sectional area and that overlies the cap layer. With this construction, surface defects are unlikely to occur, so that a highly reliable semiconductor device can be fabricated.

Abstract: A diode for sensing hydrogen and hydrocarbons and the process for manufacturing the diode are disclosed. The diode is a Schottky diode which has a palladium chrome contact on the C-face of an n-type 6H Silicon carbide epilayer. The epilayer is grown on the C-face of a 6H silicon carbide substrate. The diode is capable of measuring low concentrations of hydrogen and hydrocarbons at high temperatures, for example, 800° C. The diode is both sensitive and stable at elevated temperatures.

Abstract: A layer comprising cobalt (Co) is formed on a p+ layer by vapor deposition, and layer comprising gold (Au) is formed thereon. The two layers are alloyed by a heat treatment to form a light-transmitting electrode. The light-transmitting electrode therefore has reduced contact resistance and improved light transmission properties, and gives a light-emitting patten which is stable over a long time. Furthermore, since cobalt (Co) is an element having a large work function, satisfactory ohmic properties are obtained.

Abstract: An optoelectronic semiconductor device in the form of an LED comprises a silicon p-n junction having a photoactive region containing beta-iron disilicide (&bgr;-FeSi2). The LED produces electroluminescence at a wavelength of about 1.5 &mgr;m.

Abstract: The present invention describes the use of large thin film (TF) capacitors having capacitance C made in a separate set of TF layers ABOVE the Si and wiring levels of an integrated circuit (IC). This C is very large. This invention describes a two-level IC architecture in which a metal/insulator/metal (MIM) capacitor structure comprises the upper level, and CMOS logic and memory circuits made in the Si wafer substrate comprise the lower level. The added thin film capacitance serves to stabilize the power supply voltage at a constant level during GHz IC operation.

Abstract: A high-voltage electrostatic discharge protection circuit according to the invention has the following structure. A first high-voltage N-well region, a first high-voltage P-well region, a second high-voltage N-well region and a second high-voltage P-well region are adjacent to each other. A PMOS transistor is formed on the first high-voltage N-well region and has its source electrically connected to a high voltage and its drain electrically connected to an input/output pad. A first isolation region is formed between the first high-voltage N-well region and the first high-voltage P-well region and electrically connected to the drain of the PMOS transistor. A first N+-type region is formed between the first high-voltage P-well region and the second high-voltage N-well region, adjacent to the first isolation region and electrically connected to the input/output pad.

Abstract: This invention prevents an end portion of the LOCOS region having a large number of defects of an MOS sensor from depletion and thereby reduces the leak current that occurs in the defects in the end portion of the LOCOS region. An n-type layer region is formed in a surface area of a p-type substrate for constituting a photodiode with the p-type layer. A LOCOS region is formed on a p+-type layer in a surface area of the silicon substrate as device separation region by oxidizing part of the silicon substrate. The n-type layer region and the LOCOS region are separated from each other by a predetermined distance. A contact region is formed and separated from the n-type layer region by a distance equal to the size of the gate electrode of the read-out transistor of the MOS sensor. A wiring layer is connected to the contact region. Then, a planarizing layer is formed to cover the n-type layer region, the LOCOS region, the gate electrode and the wiring layer.

Abstract: The impurity concentration contained in a layer on an electron supply layer of a high electron mobility field effect transistor is set in the range of 1×1016 to 1×1017 atoms/cm3, or the bandgap of a Schottky layer is set wider than that of the electron supply layer.

Abstract: A compound semiconductor multilayer structure includes a plurality of core layers absorbing light and exhibiting a photoelectric transfer; and a plurality of cladding layers, adjacent two of which sandwich each of the core layers so that the core layers are separated from each other by the cladding layers.

Abstract: A transistor structure is provided. This structure has a source electrode and a drain electrode. A doped cap layer of GaxIn1−xAs is disposed below the source electrode and the drain electrode and provides a cap layer opening. An undoped resistive layer of GaxIn1−xAs is disposed below the cap layer and defines a resistive layer opening in registration with the cap layer opening and having a first width. A Schottky layer of AlyIn1−yAs is disposed below the resistive layer. An undoped channel layer is disposed below the Schottky layer. A semi-insulating substrate is disposed below the channel layer. A top surface of the Schottky layer beneath the resistive layer opening provides a recess having a second width smaller than the first width. A gate electrode is in contact with a bottom surface of the recess provided by the Schottky layer.

Abstract: The surface of a semiconductor wafer comprises a silicon substrate and a well positioned in a predetermined area just under the surface of the substrate. A photo diode comprises a MOS transistor positioned on the surface of the well, a photo sensor positioned beside the well and electrically connected to the MOS transistor, and an insulation layer positioned on the surface of the substrate surrounding the photo sensor. The photo sensor comprises a first doped region positioned on the surface of the photo sensor, and a second doped region positioned between the first doped region and the insulation layer, a portion of the second doped region at least partially under the insulation layer. The dopant density of the second doped region is less than that of the first doped region, and the second doped region functions to reduce the electrical field around the first doped region so as to reduce the leakage current.

Abstract: According to a semiconductor device and a method of manufacturing the same, a storage node has an increased capacity, and a resistance against soft error is improved. A GND interconnection is formed on a first interconnection layer including storage node portions with a dielectric film therebetween. Thereby, the storage node portions, the dielectric film, and the GND interconnection form a capacity element of the storage node portion. The first interconnection layer is arranged symmetrically around the center of the memory cell, and a plurality of memory cells having the same layout and neighboring to each other are arranged along the word lines.

Abstract: Disclosed is a photodetector adapted to be used with a voltage source for replacing the conventional CCD. The photodetector includes a substrate electrically connected with an electrode of the voltage source for generating electron-hole pairs in response to a light, a conducting layer electrically connected with the other electrode of the voltage source, and an ultra thin (˜nm) insulating layer formed between the conducting layer and the substrate, wherein one of electrons and holes, excited by the light, in the substrate will move to the conducting layer through the insulating layer so as to form a photo current when the voltage source provides a bias voltage.

Abstract: There is provided a trench type element isolation structure wherein no recess develops in the edge part of an imbedded oxide film of a trench type element isolation. Thermal oxidation films having higher etching resistance than a CVD film are formed not only on the surroundings of the imbedded oxide film inside the groove formed on the silicon substrate but also on the lateral sides of the imbedded oxide film projecting upward from the silicon substrate surface.

Abstract: A micro-sensor having have a flexible monocrystalline structure that is moved by an external force. In one embodiment, one or more pole tips are mounted on the monocrystalline structure. The monocrystalline structure is suspended over one or more planar coils such that each pole tip is suspended over a corresponding planar coil. As the monocrystalline structure moves in response to the external force, the pole tips are moved in the coils, thereby changing the inductance or inducing a voltage in the coils. In another variation, a micro-switch includes a lower structural member having a pattern of raised spacer pads that laterally surround a plurality of contact pads. The lower structural member is joined to an upper structural member that includes a frame, a platform located in the frame and a plurality of spring elements which connect the frame to the platform. The upper structural member has a conductive layer formed on its planar lower surface.

Abstract: By using the InGaAs layer in which the In composition is graded or varied by stages for the contact resistance reducing cap layer of the recess type compound semiconductor FET as well as using the selective etching to InAs and GaAs at the time of recess etching, the recess profile can be made curvilinear without increasing the number of processes, and occurrence of the concentration of the electric field can be thereby prevented, restriction of the high breakdown voltage value due to recess profile eliminated, and high breakdown voltage achieved.

Abstract: An improved semiconductor device which includes a zener diode and RC network combination that share common semiconductor mask steps during the fabrication process. A common N+ layer serves to provide both the separate N+ cathode regions of the zener diode and the separate bottom electrode N+ region of the capacitor. A common metal layer serves to provide separate electrical contacts to the N+ cathode regions of the zener diode and also provides a separate top metal electrode for the capacitor. The capacitor dielectric is comprised of silicon nitride. A silicon dioxide/silicon nitride insulation layer is formed between the top metal electrode of the capacitor and a resistive layer typically made from tantalum nitride.