Abstract: A method for removing residual photoresist and polymer residues from silicon wafers after a polysilicon plasma etch with minimal gate oxide loss is described. The method is particularly useful for cleaning wafers after polysilicon or polycide gate etching in MOSFET with when very thin gate oxides (<100Å). In order to etch the final portion of the polysilicon gate structure including an over etch to removed isolated polysilicon patches, an etchant containing HBr is used to provide a high polysilicon to gate oxide selectivity. This etch component causes a polymer veil to form over the surface of the photoresist which is difficult to remove except by aqueous etchants which also cause significant gate oxide loss. The method of the invention addresses the removal of the veil polymer, the photoresist, and a sidewall polymer by an all dry etching process.

Abstract: The present invention provides wafer polishing apparatus in which the wafer holding head comprises a diaphragm substantially vertically expanded to the head axis in the head body; a carrier, which is fixed to the diaphragm and provided so as to be able to displace along the head axis direction together with the diaphragm; a retainer fixed to the diaphragm in a concentric relation to the carrier; a pressure adjusting mechanism for controlling the pressure of a fluid chamber formed between the diaphragm and the head body; a plurality of carrier torque mechanisms provided between the head body and the carrier for communicating the torque of the head body to the carrier; a plurality of first sensors, which is provided at individual torque transfer mechanism, for observing the force along the direction of rotation acting on the wafer; and a processor, which is connected to each first sensor, for calculating the force acting on the wafer based on the output from these first sensors.

Abstract: The present invention provides a plasma processing apparatus, system, and method for providing RF power to a plasma processing chamber. The plasma processing system includes an RF generator, a plasma chamber, a match network box, a first cable, a second cable, and means for electrically isolating the match network box. The RF generator is generates RF power for transmission to the plasma chamber. The plasma chamber receives the RF power for processing the wafer and is characterized by an internal impedance during the plasma processing. The plasma chamber has one or more walls for returning RF currents. The match network box is capable of receiving the RF currents and generates an impedance that matches the internal impedance of the plasma chamber to the impedance of the RF generator. The first cable is coupled between the RF generator and the match network box for transmitting RF power between the RF generator and the match network box.

Abstract: A reactive ion beam etching method which employs an oxidizing agent in a plasma contained in an ion source to control carbonaceous deposit (e.g., polymer) formation within the ion source and on the substrate. During operation of an ion source, after operating the ion source with a plasma having a carbonaceous deposit forming species, a plasma containing an oxidizing agent (species) is generated within the ion source. Preferably, within the ion source a plasma is maintained essentially continuously between the time that the carbonaceous deposit forming species is present and the time that the oxidizing agent is present. A reactive ion beam extracted from an ion source containing a plasma having an oxidizing species may be impinged onto a sample substrate to remove (i.e., etch) any carbonaceous material deposits (e.g., polymers) formed on the sample, such as may be formed from previous reactive ion beam etching (RIBE) processing steps using an ion beam having species which may form carbonaceous (e.g.

Abstract: A method is provided for determining an etch endpoint. The method includes collecting intensity data representative of optical emission spectral wavelengths during a plasma etch process. The method further includes analyzing at least a portion of the collected intensity data into at most first and second Principal Components with respective Loadings and corresponding Scores. The method also includes determining the etch endpoint using the respective Loadings and corresponding Scores of the second Principal Component as an indicator for the etch endpoint using thresholding applied to the respective Loadings of the second Principal Component.

Abstract: The present invention discloses a method for fabricating a trench isolation structure in a semiconductor device. A first insulating layer and a first anti-oxidation layer are formed on a semiconductor substrate. Then, a predetermined region of the surface of the substrate is exposed. Thereafter, a trench is formed by etching the exposed surface of the substrate. A second insulating layer is formed along an inner surface of the trench. Next, the first anti-oxidation layer is isotropically etched to a predetermined thickness. A second anti-oxidation layer is formed on the resultant structure. A third insulating layer is formed on the second anti-oxidation layer. The third insulating layer and the first and second anti-oxidation layers are planarized. Finally, the first anti-oxidation layer is removed.

Abstract: The process proposed allows provision of a matrix topography for electronic memory devices using self-alignment etchings capable of removing those spurious electrical contacts between adjacent memory cells. The self-aligned etching process proposed for providing a plurality of mutually parallel word lines in a first conducting layer deposited over a planarized architecture obtained starting from a semiconductor substrate. Provided on the semiconductor substrate is a plurality of active elements extending along separate parallel lines, e.g., memory cell bit lines, and comprising gate regions formed by a first conducting layer, a dielectric interpoly layer and a second conducting layer with said regions being insulated from each other by dielectric insulation films to form said architecture with said word lines being defined photolithographically by protective strips.

Abstract: The present invention provides straight forward methods for plasma etching a trench having rounded top corners, or rounded bottom corners, or both in a silicon substrate. A first method for creating a rounded top corner on the etched silicon trench comprises etching both an overlying silicon oxide layer and an upper portion of the silicon substrate during a “break-through” step which immediately precedes the step in which the silicon trench is etched. The plasma feed gas for the break-through step comprises carbon and fluorine. In this method, the photoresist layer used to pattern the etch stack is preferably not removed prior to the break-through etching step. Subsequent to the break-through step, a trench is etched to a desired depth in the silicon substrate using a different plasma feed gas composition.

Abstract: This invention relates to a method and system for establishing and maintaining a precise concentration of dissolved gas in a liquid. More particularly, the invention relates to a method and system of establishing and maintaining a precise concentration of dissolved gas in a liquid by utilizing a gas blend comprising a sufficient concentration of the desired gas so as to be in equilibrium with the desired concentration of the gas to be dissolved in the liquid, i.e., a “matched gas blend”, to prepare a liquid admixture comprising the desired concentration of the gas. In this manner, the method and system of the present invention are able to produce liquid admixtures comprising precise concentrations of dissolved gas suitable for use in applications with tight specifications, and further, are capable of delivering the liquid admixture so produced to a point of use with substantially no loss of dissolved gas.

Abstract: An apparatus and method for controlling a plasma in a plasma processing system. The apparatus comprises a wafer support pedestal surrounded by a process kit that is driven by an RF signal. Both an electrode (cathode) in the pedestal and the process kit are driven with an RF signal to establish a primary plasma above the pedestal and a secondary plasma above the process kit.

Abstract: A method and apparatus for characterizing processing operations is presented. Following exposure of a wafer to plasma, the surface charge distribution pattern on the wafer is measured. The surface charge distribution pattern on the wafer is then compared with known surface charge distribution patterns to determine if the measured charge distribution pattern correlates to desirable patterns associated with successful performance of one or more processing steps. In some embodiments, the comparison of the measured charge distribution pattern can be used to detect specific problems in one or more processing steps such that corrective action can be taken in a timely manner. The comparison between the measured charge distribution pattern and known charge distribution patterns may be performed using image comparison or using quantitative comparisons based on charge levels measured within each pattern.

Abstract: A two-step chemical mechanical polishing (CMP) process is provided for low dishing of metal lines in trenches in an insulation (oxide) layer, e.g., of silicon dioxide of a thickness of about 100-2000 nm, of a semiconductor wafer, e.g., of silicon, during its fabrication. The first step involves chemically mechanically polishing a metal layer, e.g., of copper of a thickness of about 200-2000 nm, disposed on the oxide layer and having a lower portion located in the trenches for forming metal lines and an upper portion overlying the lower portion. The first step polishing is effected at a high downforce, e.g., 3-8 psi, to remove at a high rate the upper portion of the metal layer substantially without removing the lower portion thereof and substantially without dishing of the lower portion located in the trenches. The second step involves continuing the CMP at a lower downforce, e.g.

Abstract: An etching method for forming an opening includes providing a substrate assembly having a surface and an oxide layer thereon. A patterned mask layer is provided over the oxide layer exposing a portion of the oxide layer. A plasma including one or more of CxHyFz+ ions and CxFz+ ions and further including xenon or krypton ions is used to etch the oxide layer at the exposed portion to define the opening in the oxide layer while simultaneously depositing a polymeric residue on a surface defining the opening. The etching is continued until the opening in the oxide layer is selectively etched to the surface of the substrate assembly.

Abstract: An object of the present invention is to provide a method for accurately determining a swing curve in the &mgr;m order's semiconductor technology. Photoresist films with different thicknesses are coated on silicon dummy wafers, respectively. Using a mask with a critical dimension bar's pattern, each of the chips of the silicon dummy wafers is exposed by different exposure doses such that the pattern is transferred on each of the chips. After the silicon dummy wafers are developed, each of the chips of the silicon dummy wafers is inspected by using a scanning electron microscope. For each of the silicon dummy wafers, the exposure dose resulting in completely removing the photoresist film on the region between the adjacent critical dimension bars of the pattern by developing is recorded. According to the present invention, it is easy to obtain an accurate swing curve since the resolution of the scanning electron microscope is up to the order of &mgr;m.

Abstract: A new method of forming metal interconnects with air gaps between adjacent interconnects in the manufacture of an integrated circuit device is achieved. A semiconductor substrate is provided. The metal interconnects are formed overlying the semiconductor substrate. A silicon nitride liner layer is deposited. A gap filling oxide layer is deposited to fill gaps between adjacent metal interconnects. The gap filling oxide layer is polished down to the silicon nitride liner layer. A silicon nitride thin layer is deposited. The silicon nitride thin layer is patterned using an oversized, reverse mask of the metal interconnects. The patterning of the silicon nitride thin layer creates openings to thereby expose a portion of the gap filling oxide. The gap filling oxide layer is etched away. A self-sealing oxide layer is deposited overlying the silicon nitride thin layer and the silicon nitride liner layer.

Abstract: In one aspect, the invention encompasses a semiconductor processing method. Two silicon-comprising masses are provided. A first of the two masses comprises a higher dopant concentration than a second of the two masses. The two masses are exposed to common conditions which etch the second mass faster than the first mass. In another aspect, the invention encompasses another embodiment semiconductor processing method. A substrate is provided. The substrate has at least one doped polysilicon mass formed thereover, and has regions not proximate the at least one doped polysilicon mass. Roughened polysilicon is formed along the at least one doped polysilicon mass and over said regions of the substrate. A dopant concentration in the roughened polysilicon is increased along the at least one doped polysilicon mass relative to any dopant concentration in the roughened polysilicon over said regions of the substrate.

Abstract: A method for forming copper interconnects, without inducing copper diffusion, by eliminating the copper chemical-mechanical polishing process. A semiconductor structure is provided having a first metal layer thereover. A first inter-metal dielectric layer is formed over the first metal layer and planarized. A first resist layer is formed over the first inter-metal dielectric layer, and the first resist layer and the first inter-metal dielectric layer are patterned to form via openings with the first metal layer forming the bottoms of the via openings. A barrier/seed layer, comprising a barrier layer and an overlying seed layer, is formed on the sidewalls and bottoms of the via openings. A self-align layer, composed of a high-resistivity, inorganic material, is formed over the barrier/seed layer. The self-align layer is patterned to reform the via openings and to form trench openings, exposing the barrier/seed layer on the bottoms and sidewalls of the via openings and on the bottoms of the trench openings.

Abstract: The invention concerns a method for wet-chemical cleaning and etching of disc-shaped substrates in a closed processing chamber, wherein the substrate to be processed is received by a substrate support, the substrate is rotated and both sides of the substrate are simultaneously sprayed with chemicals.

Abstract: Methods of forming substantially defect-free silicon structures at the submicron level by enhancing microscopic etchant concentration uniformity and reducing hydrogen bubble adhesion. Etchant mixtures are subjected to the application of ultrasonic waves. The ultrasonic waves promote cavitation that mixes the etchant mixture on a microscopic level, and also assists in promoting bubble detachment. Wetting agents are added to the etchant mixture to enhance the hydrophilicity of the silicon surfaces and thereby reduce bubble adhesion. Apparatus to carry out the method of forming silicon structures are also disclosed.

Abstract: A method of forming shallow trench isolation trenches for use with borderless contacts is achieved. A silicon nitride layer protects the shallow trench oxide layer from overetch damage. A silicon substrate is provided. A pad oxide layer is grown. A polishing stop layer, of polysilicon or silicon nitride, is deposited. The polishing stop layer, pad oxide layer, and silicon substrate are patterned to form the shallow trenches. A trench oxide layer is deposited to fill the shallow trenches. The trench oxide layer is polished down with the polishing stop layer as a polishing stop. The trench oxide layer is etched down to a level below that of the pad oxide layer. A silicon nitride layer is deposited. A polishing layer of oxide is deposited. The polishing layer and the silicon nitride layer are polished down with the polishing stop layer as a polishing stop. The polishing stop layer is etched away. The silicon nitride layer is etched to remove vertical sidewalls.