Abstract: In a monolithic active matrix circuit that uses offset-gate TFTs in which the gate electrode is offset from the source and drain regions or TFTs whose gate insulating film is formed by vapor deposition, not only an active matrix circuit but also a drive circuit therefor is formed by using P-channel TFTs.

Abstract: Oxidation methods, and resulting structures, comprising providing an oxide layer on a substrate and then re-oxidizing the oxide layer by vertical ion bombardment of the oxide layer in an atmosphere containing at least one oxidant. The oxide layer may be provided over diffusion regions, such as source and drain regions, in a substrate. The oxide layer may overlie the substrate and is proximate a gate structure on the substrate. The at least one oxidant may be oxygen, water, ozone, or hydrogen peroxide, or a mixture thereof. These oxidation methods provide a low-temperature oxidation process, less oxidation of the sidewalls of conductive layers in the gate structure, and less current leakage to the substrate from the gate structure.

Abstract: A method of fabricating an X-ray detector array element. A gate and a gate insulation layer are formed on a substrate. A silicon island is formed on the insulation layer in a transistor area. A common line is formed on the insulation layer, simultaneously; source and drain are formed on the island to form a TFT. A bottom electrode is formed on the insulation layer in a capacitor area and covers the common line. A passivation layer is formed on the insulation layer, the bottom electrode and the TFT. A first via hole penetrates the passivation layer to expose the source. A planarization layer is formed on the passivation layer and fills the first via hole. Second and third via holes penetrate the planarization layer. The second via hole exposes the source. The third via hole exposes part of the passivation layer. A top electrode is formed on the planarization layer and connects the source.

Abstract: A RESURF trench gate MOSFET has a sufficiently small pitch (close spacing of neighbouring trenches) that intermediate areas of the drain drift region are depleted in the blocking condition of the MOSFET. However, premature breakdown can still occur in this known device structure at the perimeter/edge of the active device area and/or adjacent the gate bondpad. To counter premature breakdown, the invention adopts two principles: the gate bondpad is either connected to an underlying stripe trench network surrounded by active cells, or is directly on top of the active cells, and a compatible 2D edge termination scheme is provided around the RESURF active device area. These principles can be implemented in various cellular layouts e.g.

Abstract: In an aspect, an apparatus is provided that sets and reprograms the state of programmable devices. In an aspect, a method is provided such that an opening is formed through a dielectric exposing a contact, the contact formed on a substrate. An electrode is conformally deposited on a wall of the dielectric, utilizing atomic layer deposition (ALD). A programmable material is formed on the electrode and a conductor is formed to the programmable material. In an aspect, a barrier is conformally deposited utilizing ALD, between the electrode and the programmable material.

Abstract: An integrated circuit capacitor is manufactured by forming a lower electrode on a substrate and forming a metal preprocessed layer on the lower electrode using chemical vapor deposition in which a metal precursor is used as a source gas and the metal precursor comprises oxygen. A dielectric layer is then formed on the metal preprocessed layer and an upper electrode is formed on the dielectric layer. The metal preprocessed layer may reduce oxidation of the lower electrode due to oxygen supplied during formation of the dielectric layer.

Abstract: In an aspect, an apparatus is provided that sets and reprograms the state of programmable devices. In an aspect, a method is provided such that an opening is formed through a dielectric exposing a contact formed on a substrate. The resistivity of the contact is modified by at least one of implanting ions into the contact, depositing a material on the contact, and treating the contact with plasma. In an aspect, a spacer is formed within the opening and programmable material is formed within the opening and on the modified contact. A conductor is formed on the programmable material and the contact transmits to a signal line.

Abstract: A color filter substrate for a liquid crystal display device includes a substrate, a plurality of black matrix regions on the substrate, a plurality of color filter layers, each disposed between adjacent ones of the plurality of black matrix regions, a panel identification at an edge of the substrate spaced apart from the plurality of black matrix regions, the panel identification and the plurality of color filter layers include a same material, an overcoat layer on the plurality of color filter layers, and a common electrode on the overcoat layer.

Abstract: A method and system for processing a silicon thin film sample on a substrate. The substrate has a surface portion that does not seed crystal growth in the silicon thin film. The film sample has a first edge and a second edge. An irradiation beam generator is controlled to emit successive irradiation beam pulses at a predetermined repetition rate. Each of the irradiation beam pulses is masked to define a first plurality of beamlets and a second plurality of beamlets, the first and second plurality of beamlets of each of the irradiation pulses being provided for impinging the film sample and having an intensity which is sufficient to melt irradiated portions of the film sample throughout their entire thickness. The film sample is continuously scanned, at a constant predetermined speed, so that a successive impingement of the first and second beamlets of the irradiation beam pulses occurs in a scanning direction on the film sample between the first edge and the second edge.

Abstract: Structures and methods involve dynamic enhancement mode p-channel flash memories with ultrathin tunnel oxide thicknesses. Both write and erase operations are performed by tunneling. The p-channel flash memory cell with thin tunnel oxides will operate on a dynamic basis. The stored data can be refreshed every few seconds as necessary. However, the write and erase operations will now be orders of magnitude faster than traditional p-channel flash memory. Structures and methods for p-channel floating gate transistors are provided that avoid p-channel threshold voltage shifts and achieve source side tunneling erase. The p-channel memory cell structure includes a floating gate separated from a channel region by an oxide layer of less than 50 Angstroms. The methods further include reading the p-channel memory cell by applying a potential to a control gate of the p-channel memory cell of less than 1.0 Volt.

Abstract: A semiconductor device includes a lower copper line formed on a substrate, an interlayer insulating layer formed on the lower copper line, and an upper copper line formed on the interlayer insulating layer. A copper via contact extends through the interlayer insulating layer for electrically connecting the lower copper line and the upper copper line. A concave recess is formed within the lower copper line and is vertically aligned and arranged below the copper via contact. A patterned barrier layer is formed at a bottom portion of the concave recess, such that the lower copper line and the copper via contact are directly electrically connected at an interface along sides of the concave recess, without an intervening barrier layer.

Abstract: Methods and structures to reduce in semiconductor packages the length of critical electrical connections between bond pads on one or multiple semiconductor chips and wire landing pads on a substrate have been achieved. An electrical connection becomes critical if high current, high speed or radio frequency signals have to be transported. Moving the wire landing pads of critical connections on the substrate closer to the semiconductor chip utilizing unpopulated spaces of an array grid design reduces the length of said wires. This could be a ball grid array (BGA) or any other kind of grid array. Said methods and structures invented are applicable to single-chip modules and to multi-chip modules. The design of the grid array has to be modified to provide free spaces for the wire landing pads of critical electrical connections within the grid array close to the semiconductor chip as required by the design rules. The design change can be done without increasing the number of solder balls or solder pins, etc.

Abstract: The semiconductor memory device comprises a glue layer defining a cylinder shell, a bottom electrode made of a material of the platinum group and covering the inner face and the outer face of the cylinder shell, a dielectric layer formed over the bottom electrode, and a top electrode positioned over the dielectric layer. The bottom electrode, the dielectric layer, and the top electrode comprise a cell capacitor.

Abstract: An LCD device includes a plurality of data pads; an LCD panel defined by a plurality of pad regions; a first shorting bar connected to odd numbered data pads among the plurality of data pads; a second shorting bar connected to even numbered data pads among the plurality of data pads; and a test pad formed in a predetermined portion of a pad region among the plurality of pad regions to apply a signal voltage for on/off testing to the first shorting bar and the second shorting bar.

Abstract: A semiconductor device has recesses formed in the substrate during removal of the anti-reflective coating (ARC) because these recess locations are exposed during the etching of the ARC. Although the etchant is chosen to be selective between the ARC material and the substrate material, this selectivity is limited so that recesses do occur. A problem associated with the formation of these recesses is that the source/drains have further to diffuse to become overlapped with the gate. The result is that the transistors may have reduced current drive. The problem is avoided by waiting to perform the ARC removal until at least after formation of a sidewall spacer around the gate. The consequent recess formation thus occurs further from the gate, which results in reducing or eliminating the impediment this recess can cause to the source/drain diffusion that desirably extends to overlap with the gate.

Abstract: There is provided a structure of a pixel TFT (n-channel type TFT) in which an off current value is sufficiently low. In impurity regions, a concentration distribution of an impurity element imparting one conductivity type is made to have a concentration gradient, the concentration is made low at a side of a channel formation region, and the concentration is made high at the side of an end portion of a semiconductor layer.

Abstract: Forming a back-illuminated type CMOS image sensor, includes process for formation of a registration mark on the wiring side of a silicon substrate during formation of an active region or a gate electrode. A silicide film using an active region may also be used for the registration mark. Thereafter, the registration mark is read from the back side by use of red light or near infrared rays, and registration of the stepper is accomplished. It is also possible to form a registration mark in a silicon oxide film on the back side (illuminated side) in registry with the registration mark on the wiring side, and to achieve the desired registration by use of the registration mark thus formed.

Abstract: A method of fabricating a semiconductor device. The method produces a device that includes a plurality of first topographic structures comprising conductive lead lines deposited on a semiconductor substrate, and a plurality of second topographic structures comprising fill patterns such that the top surfaces of the second topographic structures are generally coplanar with the top surfaces of the plurality of first topographic structures. The plurality of first and second topographic structures are arranged in a generally repeating array on the substrate. A planarization layer is deposited on top of the substrate such that it fills the space between the plurality of first and second topographic structures, with its top surface generally coplanar with that of the top surfaces of the first and second topographic structures.

Abstract: A reticle for manufacturing a semiconductor device. The reticle includes cutouts that permit material deposited through the reticle and onto a surface of a semiconductor device being manufactured to form the shape of the cutouts. Shapes defined in the cutouts and produced on the semiconductor device include first and second topographic structures, where the first are made up of conductive lead lines, and the second made up of fill patterns such that the top surfaces of the second topographic structures are generally coplanar with the top surfaces of the first topographic structures. The first and second topographic structures can be arranged in a generally repeating array on the substrate.

Abstract: A fill pattern for a semiconductor device. The device includes a plurality of first topographic structures comprising conductive lead lines deposited on a semiconductor substrate, and a plurality of second topographic structures comprising fill patterns such that the top surfaces of the second topographic structures are generally coplanar with the top surfaces of the plurality of first topographic structures. The plurality of first and second topographic structures are arranged in a generally repeating array on the substrate. A planarization layer is deposited on top of the substrate such that it fills the space between the plurality of first and second topographic structures, with its top surface generally coplanar with that of the top surfaces of the first and second topographic structures.