Patents Examined by William Vesperman
  • Patent number: 6528338
    Abstract: The present invention provides a method of manufacturing a polarization-insensitive waveguide structure. The method comprises: depositing a buffer layer on a substrate; depositing a core layer on the buffer layer and etching the core layer so as to form a waveguide core; and depositing a silica-based cladding layer over the core by means of plasma-enhanced chemical vapor deposition (PECVD) in the absence of nitrogen or nitrogen-containing gases so as to complete the waveguide structure, wherein the cladding layer is deposited in a manner which substantially prevents polarization sensitivity in the waveguide structure. The cladding layer can be deposited with an intrinsic stress which cancels out any thermal stresses. The stress can be controlled by controlling the PECVD deposition conditions, such as power and ion bombardment.
    Type: Grant
    Filed: July 25, 2001
    Date of Patent: March 4, 2003
    Assignee: Redfern Integrated Optics Pty LTD
    Inventor: Michael Bazylenko
  • Patent number: 6521968
    Abstract: A photodiode that is used in an optical communication system using two different wavelengths, &lgr;1 and &lgr;2(&lgr;1<&lgr;2), and that enables a reduction in the optical crosstalk caused by outgoing light having a longer wavelengths, &lgr;2. A photodiode that receives light having a shorter wavelengths, &lgr;1, is provided with an absorption layer made of a material having a bandgap wavelength, &lgr;g (&lgr;1<&lgr;g<&lgr;2), to detect the light having &lgr;1. A filter layer that absorbs unwanted light having &lgr;2 is provided over the absorption layer so that the light having &lgr;2 cannot return to the absorption layer after passing through it once.
    Type: Grant
    Filed: August 1, 2001
    Date of Patent: February 18, 2003
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Yoshiki Kuhara, Yasuhiro Iguchi
  • Patent number: 6504179
    Abstract: A white-emitting luminescence conversion LED uses a chlorosilicate phosphor which, in addition to Ca and Mg, contains a europium doping, and also a garnet phosphor of the rare earths, in particular Y and/or Tb. In this way, it is possible to achieve a high color rendering and a high constancy of the lighting properties under differing temperature conditions.
    Type: Grant
    Filed: January 17, 2002
    Date of Patent: January 7, 2003
    Assignees: Patent-Treuhand-Gesellschaft fur elektrische Gluhlampen mbH, OSRAM Opto Semiconductors GmbH & Co. OHG
    Inventors: Andries Ellens, Frank Jermann, Franz Kummer, Michael Ostertag, Franz Zwaschka
  • Patent number: 6479313
    Abstract: Compound semiconductor material is irradiated with x-ray radiation to activate a dopant material. Active carrier concentration efficiency may be improved over known methods, including conventional thermal annealing. The method may be employed for III-V group compounds, including GaN-based semiconductors, doped with p-type material to form low resistivity p-GaN. The method may be further employed to manufacture GaN-based LEDs, including blue LEDs, having improved forward bias voltage and light-emitting efficiency.
    Type: Grant
    Filed: May 25, 2001
    Date of Patent: November 12, 2002
    Assignee: Kopin Corporation
    Inventors: Jinlin Ye, Jyh-Chia Chen, Shirong Liao, Hong K. Choi, John C. C. Fan
  • Patent number: 6452248
    Abstract: A programmable fuse structure using an MOS transistor. A voltage potential is switched across the gate of the MOS transistor, with the gate resistance causing it to heat the MOS structure. This causes a short at one or more of a number of locations in the MOS structure, thereby programming the MOS transistor. A programming circuit with the MOS transistor in a feedback path is provided. This feedback provides a self-timing feature, such that immediately after the fuse is programmed, its programming operation ceases.
    Type: Grant
    Filed: August 14, 2000
    Date of Patent: September 17, 2002
    Assignee: Exar Corporation
    Inventor: Hung Pham Le
  • Patent number: 6423608
    Abstract: A capacitor in a semiconductor integrated circuit, and a method for fabricating the capacitor is disclosed. A method of an embodiment of the invention includes first providing a semiconductor substrate having disposed thereon an interlayer insulating layer. A lower sacrificial insulating layer and an upper etching stopper layer then are sequentially formed on the interlayer insulating layer on the semiconductor substrate. The upper etching stopper layer and the lower sacrificial insulating layer then are sequentially patterned to form a storage electrode hole, and to expose a predetermined portion of the interlayer insulating layer. The method then includes forming an outer cylindrical storage electrode in the storage electrode hole, a conductive liner surrounded by the outer cylindrical storage electrode, and an inner storage electrode surrounded by the conductive liner.
    Type: Grant
    Filed: November 3, 2000
    Date of Patent: July 23, 2002
    Assignee: Samsung Electronics Co. Ltd.
    Inventor: Yun-Ki Kim