Abstract: Methods of fabricating a thick oxide feature on a semiconductor wafer include forming a oxide layer having a thickness of at least six micrometers and depositing a photoresist layer on the oxide layer. The oxide layer has a first etch rate of X with a given etchant, the photoresist layer has a second etch rate of Y with the given etchant and the ratio of X:Y is less than 4:1. Prior to etching the photoresist layer and the oxide layer, the photoresist layer is patterned with a grayscale mask that creates a photoresist layer having a sidewall that forms an angle with the horizontal that is less than or equal to 10 degrees.

Abstract: Devices and techniques including process steps make use of recesses in conductive interconnect structures to form reliable low temperature metallic bonds. A fill layer is deposited into the recesses prior to bonding. The fill layer is composed of noble metal (such as copper) and active metal (such as Zn). Then the fill metal layer is turned into a metal alloy after annealing. A dealloying is performed to the metal alloy to remove the active metal from the metal alloy while the noble metal remains to self-assemble into porous (nanoporous) structure metal. First conductive interconnect structures are bonded at ambient temperatures to second metallic interconnect structures using dielectric-to-dielectric direct bonding techniques, with the fill nanoporous metal layer in the recesses in one of the first and second interconnect structures.

Abstract: A semiconductor device package and a method for manufacturing the same are provided. The semiconductor device package includes a circuit layer and an antenna module. The circuit layer has a first surface, a second surface opposite to the first surface and a lateral surface. The lateral surface extends between the first surface and the second surface. The circuit layer has an interconnection structure. The antenna module has an antenna pattern layer and is disposed on the first surface of the circuit layer. The lateral surface of the circuit layer is substantially coplanar with a lateral surface of the antenna module.

Abstract: In a method of manufacturing a semiconductor device, a single crystal oxide layer is formed over a substrate. After the single crystal oxide layer is formed, an isolation structure to define an active region is formed. A gate structure is formed over the single crystal oxide layer in the active region. A source/drain structure is formed.

Abstract: Systems, methods, and devices for 3D packaging. In some embodiments, a semiconductor package includes a first die and a second die. The first die includes a first bonding pad on a top of the first die and near a first edge of the first die. The second die includes a second bonding pad on a top of the second die and near a second edge of the second die. A pillar is located on the second bonding pad. The first die is mounted on top of the second die such that the first edge is parallel to the second edge and offset from the second edge such that the pillar is exposed. A wire is bonded to a bonding surface of the pillar and bonded to a bonding surface of the first bonding pad.

Abstract: A method includes disposing a wafer in a cup of a clamshell of an electroplating apparatus. The wafer is clamped using the cup and a cone of the clamshell. A pressure force applied by the cone against the wafer is detected. Stopping clamping the wafer when the pressure force is higher than a predetermined value.

Abstract: In accordance with various embodiments, a method for processing a layer structure is provided, where the layer structure includes a first layer, a sacrificial layer arranged above the first layer, and a second layer arranged above the sacrificial layer, where the second layer includes at least one opening, and the at least one opening extends from a first side of the second layer as far as the sacrificial layer. The method includes forming a liner layer covering at least one inner wall of the at least one opening; forming a cover layer above the liner layer, where the cover layer extends at least in sections into the at least one opening; and wet-chemically etching the cover layer, the liner layer and the sacrificial layer using an etching solution, where the etching solution has a greater etching rate for the liner layer than for the cover layer.

Abstract: A semiconductor device is disclosed including one or more semiconductor dies mounted on substrate. Each semiconductor die may be formed with a ferromagnetic layer on a lower, inactive surface of the semiconductor die. The ferromagnetic layer pulls the semiconductor dies down against each other and the substrate during fabrication to prevent warping of the dies. The ferromagnetic layer also balances out a mismatch of coefficients of thermal expansion between layers of the dies, thus further preventing warping of the dies.

Abstract: A 3D semiconductor device, the device including: a first level, wherein said first level comprises a first layer, said first layer comprising first transistors, and wherein said first level comprises a second layer, said second layer comprising first interconnections; a second level overlaying said first level, wherein said second level comprises a third layer, said third layer comprising second transistors, and wherein said second level comprises a fourth layer, said fourth layer comprising second interconnections; and a plurality of connection paths, wherein said plurality of connection paths provides connections from a plurality of said first transistors to a plurality of said second transistors, wherein said second level is bonded to said first level, wherein said bonded comprises oxide to oxide bond regions, wherein said bonded comprises metal to metal bond regions, wherein said second level comprises at least one Electrostatic discharge (ESD) circuit.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a seed layer to cover a first passivation layer over a semiconductor substrate. The method also includes forming a metal layer to partially cover the seed layer by using the seed layer as an electrode layer in a first plating process and forming a metal pillar bump over the metal layer by using the seed layer as an electrode layer in a second plating process. In addition, the method includes forming a second passivation layer over the metal layer, wherein the second passivation layer includes a protrusion portion extending from a top surface of the second passivation layer and surrounding the sidewall of the metal pillar bump.

Abstract: Novel integrated circuits (SOI ICs), and methods for making and mounting the ICs are disclosed. In one embodiment, an IC comprises a first circuit layer of the IC formed from an active layer of an SOI wafer. The first circuit layer is coupled to a first surface of buffer layer, and a second surface of the buffer layer is coupled to a selected substrate comprising an insulating material. The selected substrate may be selected, without limitation, from the following types: sapphire, quartz, silicon dioxide glass, piezoelectric materials, and ceramics. A second circuit layer of the IC are formed, coupled to a second surface of the selected substrate. In one embodiment of a mounted IC, the first circuit layer is coupled to contact pads on a package substrate via solder bumps or copper pillars. The second circuit layer is coupled to contact pads on the package substrate via wire bonds.

Abstract: A production method for a double-membrane MEMS component includes: providing a layer arrangement on a carrier substrate, wherein the layer arrangement comprises a first membrane structure, a sacrificial material layer adjoining the first membrane structure, and a counterelectrode structure in the sacrificial material layer and at a distance from the first membrane structure, wherein at least one through opening is formed in the sacrificial material layer as far as the first membrane structure; forming a filling material structure in the at least one through opening by applying a first filling material layer on the wall region of the at least one through opening; applying a second membrane structure on the layer arrangement with the sacrificial material; and removing the sacrificial material from an intermediate region to expose the filling material structure in the intermediate region.

Abstract: There is provided a solid-state imaging device including first, second, and third substrates stacked in this order. The first substrate includes a first semiconductor substrate and a first wiring layer. A pixel unit is formed on the first semiconductor substrate. The second substrate includes a second semiconductor substrate and a second wiring layer. The third substrate includes a third semiconductor substrate and a third wiring layer. A first coupling structure couples two of the first, second, and third substrates to each other includes a via. The via has a structure in which electrically-conductive materials are embedded in one through hole and another through hole, or a structure in which films including electrically-conductive materials are formed on inner walls of the through holes. The one through hole exposes a first wiring line in one of the wiring layers. The other through hole exposes a second wiring line in another wiring layer.

Abstract: An adhesive, and an encapsulated product and method of encapsulating an organic electronic device (OED) using the same are provided. The adhesive film serves to encapsulate the OED and includes a curable resin and a moisture absorbent, and the adhesive includes a first region coming in contact with the OED upon encapsulation of the OED and a second region not coming in contact with the OED. Also, the moisture absorbent is present at contents of 0 to 20% and 80 to 100% in the first and second regions, respectively, based on the total weight of the moisture absorbent in the adhesive.

Abstract: Methods and systems for estimating values of process parameters, structural parameters, or both, based on x-ray scatterometry measurements of high aspect ratio semiconductor structures are presented herein. X-ray scatterometry measurements are performed at one or more steps of a fabrication process flow. The measurements are performed quickly and with sufficient accuracy to enable yield improvement of an on-going semiconductor fabrication process flow. Process corrections are determined based on the measured values of parameters of interest and the corrections are communicated to the process tool to change one or more process control parameters of the process tool. In some examples, measurements are performed while the wafer is being processed to control the on-going fabrication process step. In some examples, X-ray scatterometry measurements are performed after a particular process step and process control parameters are updated for processing of future devices.

Abstract: A semiconductor chip (2) includes a surface electrode (3). A conductive bonding member (8) includes first and second bonding members (8a,8b) provided on the surface electrode (3). A lead electrode (9) is bonded to a part of the surface electrode (3) via the first bonding member (8a) and has no contact with the second bonding member (8b). A signal wire (11) is bonded to the surface electrode (3). The second bonding member (8b) is arranged between the first bonding member (8a) and the signal wire (11). A thickness of the first bonding member (8a) is larger than a thickness of the second bonding member (8b).

Abstract: A semiconductor device includes a substrate and at least one bump structure disposed over the substrate. The at least one bump structure includes a pillar formed of a metal having a lower solderability than copper or a copper alloy to a solder alloy disposed over the substrate. A solder alloy is formed directly over and in contact with an upper surface of the metal having the lower solderability than copper or a copper alloy. The pillar has a height of greater than 10 ?m.

Abstract: Disclosed is a magnetic memory device including a line pattern on a substrate, a magnetic tunnel junction pattern on the line pattern, and an upper conductive line that is spaced apart from the line pattern across the magnetic tunnel junction pattern and is connected to the magnetic tunnel junction pattern. The line pattern provides the magnetic tunnel junction pattern with spin-orbit torque. The line pattern includes a chalcogen-based topological insulator.

Abstract: A semiconductor device includes a semiconductor portion, a first insulating film, a second insulating film, a first contact, a second contact, and a gate electrode. The first insulating film is provided on the semiconductor portion. The second insulating film is contacting the first insulating film, is provided on the semiconductor portion, and is thicker than the first insulating film. A through-hole is formed in the second insulating film. The first contact has a lower end connected to the semiconductor portion. The second contact has a lower portion disposed inside the through-hole and a lower end connected to the semiconductor portion. The gate electrode is positioned between the first contact and the second contact, is provided on the first insulating film, and is provided on a portion of the second insulating film other than the through-hole.

Abstract: Hybrid microelectronic substrates, and related devices and methods, are disclosed herein. In some embodiments, a hybrid microelectronic substrate may include a low-density microelectronic substrate having a recess at a first surface, and a high-density microelectronic substrate disposed in the recess and coupled to a bottom of the recess via solder.