Abstract: A diode is provided with a pillar region formed so as to extend between a barrier region and an anode electrode, contact the barrier region, and made of a first conductivity type semiconductor having a concentration higher than that of the barrier region; and a barrier height adjusting region formed so as to be located between the pillar region and the anode electrode, and contact the pillar region and the anode electrode. The barrier height adjusting region includes at least one component selected from the group consisting of a second conductivity type semiconductor having a concentration lower than that of an anode region, the first conductivity type semiconductor having a concentration lower than that of the pillar region, and an i-type semiconductor. The barrier height adjusting region and the anode electrode are connected through a Schottky junction.

Abstract: A semiconductor device is disclosed. A substrate of a first conductivity type is provided. The substrate has a first area and a second area. An epitaxial layer of a second conductivity type is disposed on the front side of the substrate. A first doped region of the first conductivity type is disposed in the epitaxial layer in the first area, wherein a doping depth of the first doped region is gradually decreased away from the second area. At least one second doped region of the second conductivity type is disposed in the first doped region, wherein a doping depth of the at least one second doped region is gradually increased away from the second area. A dielectric layer is disposed on the epitaxial layer. A first conductive layer is disposed on the dielectric layer.

Abstract: An LED mounting substrate includes a lead frame, a base, and a residue of injection molding material. The base is placed on the lead frame, and includes a cavity. The bottom of the cavity includes an opening for exposing portion of the lead frame. The cross-sectional area of the cavity increases along the direction from the lead frame to the top surface of the base. The residue of injection molding material is remained on one of outer walls of the base surrounding the cavity. The cross-sectional area of the residue of injection molding material decreases along the direction from the lead frame to the top surface of the base.

Abstract: A semiconductor device includes a resistance variable element including a free magnetic layer, a tunnel barrier layer and a pinned magnetic layer; and a magnetic correction layer disposed over the resistance variable element to be separated from the resistance variable element, and having a magnetization direction which is opposite to a magnetization direction of the pinned magnetic layer.

Abstract: Embodiments of the present invention provide an array substrate, a manufacturing method thereof, and a display device. The array substrate comprises: a pixel region, a data-line pad region and a gate-line pad region; the pixel region comprises: a pixel electrode, a gate electrode of a TFT, source and drain electrodes of the TFT, a connection electrode, and a common electrode; the data-line pad region comprises: an insulating layer, a semiconductor layer, a data line, and a data-line connection pad; the data line and the source and drain electrodes are of a same layer and a same material; and the gate-line pad region comprises: a gate line, an insulating layer, and a gate-line connection pad; the gate line and the gate electrode are of a same layer and a same material; and the gate-line connection pad and the source and drain electrodes are of a same layer and a same material.

Abstract: Integrated circuits with multi-level memory cells and methods for producing the same are provided. A method for producing an integrated circuit with a multi-level memory cell includes forming a gate insulator overlying a substrate. A select gate is formed overlying the gate insulator such that one multi-level memory cell includes one select gate. A thin film storage layer with nanocrystals is formed overlying the select gate and the substrate, and a left and right control gate are formed on opposite sides of the select gate such that the thin film storage layer is between the substrate and each of the control gates. A left implant and a right implant are formed in the substrate such that the select gate, the left control gate, and the right control gate are positioned between the left and right implants.

Abstract: An organic EL element including: pixel electrode on a section of TFT substrate corresponding to pixel region; auxiliary connector on a section of TFT substrate corresponding to auxiliary region; hole injection layer on pixel electrode and auxiliary connector; and light-emitting layer on a section of hole injection layer corresponding to pixel region. The organic EL element additionally includes: electron injection layer on light-emitting layer and a section of hole injection layer corresponding to auxiliary region; and seamless common electrode on electron injection layer. Hole injection layer contains WOx. Electron injection layer contains NaF. Common electrode contains Al that causes the reduction of NaF contained in electron injection layer.

Abstract: A method of forming a three-dimensional memory is provided. A stacked structure including semiconductor layers and insulating layers arranged alternately is formed on a substrate. The stacked structure is patterned to form a mesh structure having first strips extending in a first direction and second strips extending in a second direction. The first strips and the second strips intersect with each other. The mesh structure has first holes. A dielectric layer is formed in each first hole. At least a portion of the first strips of the mesh structure is removed to form second holes and bit line stacked structures separated from each other. A charge storage layer is formed on sidewall and bottom of each second hole. A gate pillar extending in a third direction is formed on each charge storage layer in the second hole. Word lines extending in the first direction are formed on the gate pillars.

Abstract: An electrical device includes an insulating substrate and a magnetically doped TI quantum well film. The insulating substrate includes a first surface and a second surface. The magnetically doped topological insulator quantum well film is located on the first surface of the insulating substrate. A material of the magnetically doped topological insulator quantum well film is represented by a chemical formula of Cry(BixSb1-x)2-yTe3, wherein 0<x<1, 0<y<2, and values of x and y satisfies that an amount of a hole type charge carriers introduced by a doping with Cr is substantially equal to an amount of an electron type charge carriers introduced by a doping with Bi, the magnetically doped topological insulator quantum well film is in 3 QL thickness to 5 QL thickness.

Abstract: A topological insulator structure includes an insulating substrate and a magnetically doped TI quantum well film located on the insulating substrate. A material of the magnetically doped TI quantum well film is represented by a chemical formula of Cry(BixSb1-x)2-yTe3. 0.05<x<0.3, 0<y<0.3, and 1:2<x:y<2:1. The magnetically doped TI quantum well film is in 3 QL to 5 QL.

Abstract: Systems and methods are disclosed involving a resistive memory with a small electrode, relating to the field of semiconductor resistive memory in ULSI. An illustrative resistive memory may include an Al electrode layer, a SiO2 layer, a Si layer, a resistive material layer and a lower electrode layer in sequence, wherein the Al electrode layer and the resistive material layer are electrically connected through one or more conductive channel and the conductive channel is formed by penetrating Al material into the Si layer via defects in the SiO2 layer and dissolving Si material into the Al material. Methods may include forming a lower electrode layer, a resistive layer, a Si layer and a SiO2 layer over a substrate; fabricating a Al electrode layer over the SiO2 layer; and performing an anneal process to the resultant structure. Consistent with innovations herein, a small electrode may be obtained via a conventional process.

Abstract: Provided is a broadband photomixer technology that is a core to generate continuous frequency variable and pulsed terahertz waves. It is possible to enhance light absorptance by applying the transmittance characteristic of a 2D light crystal structure and it is possible to increase the generation efficiency of terahertz waves accordingly. Moreover, it is possible to implement a wide area array type terahertz photomixer by applying an interdigit structure and spatially properly arranging a light crystal structure having various cycles. Accordingly, it is possible to solve difficulty in thermal characteristic and light alignment by mitigating the high light density of a light absorption unit and low photoelectric conversion efficiency is drastically improved. In addition, the radiation pattern of terahertz waves may be electrically controlled through the present invention.

Abstract: The present application discloses a display panel including flexible substrates on which first power lines are mounted to supply power; a substrate including a first surface provided with a display area, a second surface opposite to the first surface, and second power lines for connecting the first power lines to the display pixels; a thermal conduction member partially covering the second surface and conducting heat in an in-plane direction; and a thermal conduction seal covering a periphery of the thermal conduction member. The first surface includes an arrangement area to arrange the second power lines between the flexible substrates and the display area. The second surface includes a first area opposite to the display area and a second area opposite to the arrangement area. The thermal conduction member covers at least the first area. The thermal conduction seal covers the second area.

Abstract: An electrooptic device substrate includes a scan line that is provided on an element substrate, a foundation insulating layer, a semiconductor layer provided on the foundation insulating layer, a gate insulating layer, recesses that are provided at both sides of the semiconductor layer so as to penetrate through the foundation insulating layer and the gate insulating layer, a gate electrode that is provided on the gate insulating layer and is electrically connected to the scan line in the recesses, an insulating interlayer that covers the gate insulating layer, the gate electrode, and the recesses, and a data line that is provided on the insulating interlayer so as to overlap with the scan line, the semiconductor layer, the gate electrode, and the recesses. The recesses include first recesses that overlap with the scan line and second recesses that extend to outer sides of the scan line.

Abstract: A photoelectric conversion device includes a light-absorbing layer including a compound semiconductor capable of photoelectric conversion, the compound semiconductor containing a group Ib element including Cu, a group IIIb element and a group VIb element; and a semiconductor layer on one surface-side of the light-absorbing layer, the semiconductor layer having a plane orientation different from that of the light-absorbing layer, the semiconductor layer containing a group Ib element including Cu, at least one element selected from Cd, Zn and In, and a group VIb element. The photoelectric conversion device includes a region in which Cu content decreases from the light-absorbing layer to the semiconductor layer across a junction interface.