Abstract: Techniques for forming Ga-doped source drain contacts in Ge-based transistors are provided. In one aspect, a method for forming Ga-doped source and drain contacts includes the steps of: depositing a dielectric over a transistor; depositing a dielectric over the transistor; forming contact trenches in the dielectric over, and extending down to, source and drain regions of the transistor; depositing an epitaxial material into the contact trenches; implanting gallium ions into the epitaxial material to form an amorphous gallium-doped layer; and annealing the amorphous gallium-doped layer under conditions sufficient to form a crystalline gallium-doped layer having a homogenous gallium concentration of greater than about 5×1020 at./cm3. Transistor devices are also provided utilizing the present Ga-doped source and drain contacts.

Abstract: Disclosed herein is a UV light emitting device. The UV light emitting device includes a first conductive type semi-conductor layer, an anti-cracking layer disposed on the first conductive type semiconductor layer, an active layer disposed on the anti-cracking layer, and a second conductive type semiconductor layer disposed on the active layer, wherein the anti-cracking layer includes first lattice points and second lattice points disposed at an interface between the first conductive type semiconductor layer and the anti-cracking layer, the first lattice points are connected to lattices of the first conductive type semiconductor layer, and the second lattice points are not connected to the lattices of the first conductive type semiconductor layer.

Abstract: A 3-D semiconductor device comprising a plurality of memory cells and a plurality of selection transistors, each of said plurality of memory cells comprises: a channel layer, distributed along a direction perpendicular to the substrate surface; a plurality of inter-layer insulating layers and a plurality of gate stack structures, alternately laminating along the sidewall of the channel layer; a plurality of floating gates, located between the plurality of inter-layer insulating layers and the sidewall of the channel layer; a plurality of drains, located at the top of the channel layer; and a plurality of sources, located in the said substrate between two adjacent memory cells of the said plurality of memory cells.

Abstract: A method for forming a semiconductor device includes providing a substrate structure, which has a semiconductor substrate and a semiconductor fin on the substrate. The method also includes forming a catalytic material layer overlying the semiconductor fins, and forming an isolation region covering the catalytic material layer in a lower portion of the semiconductor fins. Next, a graphene nanoribbon is formed on the catalytic material layer on an upper portion of the semiconductor fin, and a gate structure is formed on the graphene nanoribbon.

Abstract: An organic light-emitting diode (OLED) display device includes a substrate, a first gate electrode on the substrate, a second gate electrode on the first gate electrode and at least partially overlapping the first gate electrode, a semiconductor pattern between the first gate electrode and the second gate electrode and at least partially overlapping the first and second gate electrodes, a connecting electrode on the second gate electrode and electrically connected to the semiconductor pattern, and a pixel electrode on the connecting electrode and electrically connected to the connecting electrode.

Abstract: A display device includes a display substrate including at least one step portion, and a thin film encapsulation layer above the display substrate, the thin film encapsulation layer including a buffer layer configured to reduce a height difference due to the at least one step portion and a barrier layer above the buffer layer, the buffer layer including a plurality of sub-layers and interfaces between the plurality of sub-layers, and the interfaces including a curved surface changing from a concave shape to a convex shape toward a portion overlapping the step portion from an outer portion of the step portion.

Abstract: An organic light emitting display device includes a substrate including a pixel region and a peripheral region, a first wiring, a second wiring, a third wiring, and an electrostatic protection structure including electrostatic protection diodes coupled to the first, second, and third wirings. The electrostatic protection diodes each include an active pattern, a gate electrode pattern, and a connection pattern. The active pattern is at the peripheral region of the substrate, and has a first region, a second region spaced apart from the first region, and a third region between the first and second regions. The gate electrode pattern is at the third region on the active pattern. The connection pattern is coupled to the gate electrode pattern and the active pattern and is on the gate electrode pattern, and overlaps a portion of the first region of the active pattern and a portion of the third region.

Abstract: A display unit including a first substrate and a second substrate that are disposed to face each other, a first organic insulating layer on the first substrate, a plurality of light-emitting elements arrayed in a display region, the display region on the first organic insulating layer and facing the second substrate and a first moisture-proof film covering the first organic insulating layer in a peripheral region, in which the peripheral region is provided on the first substrate and surrounds the display region.

Abstract: The present disclosure relates to a flexible panel and the manufacturing method thereof. The method includes: coating photosensitive adhesive on a substrate to form a photosensitive layer; forming a scattering layer and an ultraviolet (UV) blocking layer on the photosensitive layer in sequence; forming a flexible substrate layer on the UV blocking layer; forming electronic components, lighting components, and an encapsulation layer on the flexible substrate layer in sequence; and irradiating the photosensitive layer from one side of the substrate by UV rays such that a peeling strength of the photosensitive layer being reduced, and the scattering layer being separated from the substrate to form the flexible panel. By configuring the photosensitive layer, the scattering layer, and the UV blocking layer on the substrate, the scattering layer may be easily separated from the substrate.

Abstract: In accordance with some embodiments of the disclosure, an array substrate and a related liquid crystal display device are provided. The array substrate can include a plurality of pixel electrodes arranged on a base substrate, and a conductive opaque line arranged between two neighboring pixel electrodes and overlapping with each of the two neighboring pixel electrodes along a width direction of the conductive opaque line.

Abstract: A patterning method employing a half tone mask includes the steps of: successively forming a first thin film layer, a second thin film layer and a photoresist thin film layer on a substrate; exposing and developing the photoresist thin film layer by using a half tone mask plate; performing a first etching on the substrate that is exposed and developed; performing a second etching on the substrate that has been subject to the first etching; passivating the substrate that has been subject to the first etching; ashing the substrate that has been passivated; performing a third etching on the substrate that has been subject to the ashing and the second etching; and, stripping the substrate that has been subject to the third etching.

Abstract: An organic light emitting diode display includes a substrate and a first red organic light emitting element disposed on the substrate. The first red organic light emitting element may include a first light emission region and a second light emission region, wherein the first light emission region emits a first red light having a first peak wavelength, and the second light emission region emits a second red light having a second peak wavelength different from the first peak wavelength.

Abstract: A method is presented for creating an asymmetrical split-gate structure. The method includes forming a first device, forming a second device, forming a first gate stack between a first set of spacers of the first device, and a second gate stack between a second set of spacers of the second device. The method further includes depositing a hard mask over the first and second gate stacks, etching a first section of the first gate stack to create a first gap and a second section of the second gate stack to create a second gap, and forming a third gate stack within the first gap of the first gate stack and within the second gap of the second gate stack such that dual gate stacks are defined for each of the first and second devices. The method further includes annealing the dual gate stacks to form replacement metal gate stacks.

Abstract: A method forming a semiconductor device that in one embodiment includes forming a gate structure on a channel region of fin structures, and forming a flowable dielectric material on a source region portion and a drain region portion of the fin structures. The flowable dielectric material is present at least between adjacent fin structures of the plurality of fin structures filling a space between the adjacent fin structures. An upper surface of the source region portion and the drain region portion of fin structures is exposed. An epitaxial semiconductor material is formed on the upper surface of the source region portion and the drain region portion of the fin structures.

Abstract: III-N semiconductor heterostructures on III-N epitaxial islands laterally overgrown from a mesa of a silicon substrate. An IC may include a III-N semiconductor device disposed on the III-N epitaxial island overhanging the silicon mesa and may further include a silicon-based MOSFET monolithically integrated with the III-N device. Lateral epitaxial overgrowth from silicon mesas may provide III-N semiconductor regions of good crystal quality upon which transistors or other active semiconductor devices may be fabricated. Overhanging surfaces of III-N islands may provide multiple device layers on surfaces of differing polarity. Spacing between separate III-N islands may provide mechanical compliance to an IC including III-N semiconductor devices. Undercut of the silicon mesa may be utilized for transfer of III-N epitaxial islands to alternative substrates.

Abstract: A display substrate includes a gate line extending in a first direction, a floating electrode disposed on the same layer as the gate line, and a data line. Opposite ends of the floating electrode are electrically connected with the data line. The floating electrode extends in a second direction that crosses the first direction. The data line includes a recess disposed adjacent to the gate line. The data line overlaps with the floating electrode and also extends in the second direction.

Abstract: A nitride semiconductor device of the present invention has a source-electrode-side insulator protection film layer disposed between a source electrode and a drain electrode on a second nitride semiconductor layer and formed at least partially covering the source electrode, a drain-electrode-side insulator protection film layer disposed separately from the source-electrode-side insulator protection film layer and formed at least partially covering the drain electrode, and a gate layer formed in contact with the second nitride semiconductor layer between the source-electrode-side insulator protection film layer and the drain-electrode-side insulator protection film layer and made of a p-type metal oxide semiconductor, and the gate layer has regions opposite to the second nitride semiconductor layer across each of the source-electrode-side insulator protection film layer and the drain-electrode-side insulator protection film layer and a region in contact with the second nitride semiconductor layer.

Abstract: A method for applying a magnetic shielding layer to a substrate is provided, wherein a first magnetic shielding layer is adhered to a first surface of the substrate. A first film layer is adhered to the first magnetic shielding layer and the first magnetic shielding layer is more adherent to the first surface than the film layer to the first magnetic shielding layer.

Abstract: According to an exemplary embodiment, a method of forming a MIM capacitor is provided. The method includes the following operations: providing a first metal layer; providing a dielectric layer over the first metal layer; providing a second metal layer over the dielectric layer; etching the second metal layer to define the metal-insulator-metal capacitor; and oxidizing a sidewall of the second metal layer. According to an exemplary embodiment, a MIM capacitor is provided. The MIM capacitor includes a first metal layer; a dielectric layer over the first metal layer; a second metal layer over the dielectric layer; and an oxidized portion in proximity to the second metal layer and made of oxidized second metal layer.

Abstract: A display device includes: an organic layer arranged in plural pixels which are arranged in a display area in a matrix; a first electrode that is formed on a surface of the organic layer opposite to a substrate, and transmits a visible light; a second electrode that holds the organic layer in cooperation with the first electrode, and is lower in the transmittance of the visible light, and higher in the reflectance than the first electrode; an insulating layer that holds the second electrode in cooperation with the organic layer, and higher in the transmittance of the visible light, and lower in the reflectance than the second electrode; and a third electrode that holds the insulating layer in cooperation with the second electrode, is formed across adjacent pixels of the plural pixels, and lower in the transmittance of the visible light, and higher in the reflectance than the second electrode.