Patents Examined by Xiaoming Liu
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Patent number: 11777006Abstract: In a gate electrode of a nonvolatile memory device of an embodiment, a tunnel insulating film covers a channel region. A first current collector file is disposed on the side opposite to the channel region with respect to the tunnel insulating film. An ion conductor film is disposed between the tunnel insulating film and the first current collector film. A first electrode film is disposed between the tunnel insulating film and the ion conductor film. The first electrode film is in contact with the ion conductor film. A second electrode film is disposed between the ion conductor film and the first current collector film. The second electrode film is in contact with the ion conductor film. A second current collector film is disposed between the tunnel insulating film and the second electrode film.Type: GrantFiled: August 30, 2021Date of Patent: October 3, 2023Assignee: Kabushiki Kaisha ToshibaInventors: Koichi Mizushima, Takao Marukame, Yoshifumi Nishi, Kumiko Nomura
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Patent number: 11777010Abstract: A semiconductor structure includes a gate stack over a substrate and a blocking layer disposed between the gate stack and the substrate. The gate stack includes an upper electrode, a lower electrode, a ferroelectric layer disposed between the upper electrode and the lower electrode, and a first seed layer disposed between the ferroelectric layer and the lower electrode. The blocking layer includes doped hafnium oxide.Type: GrantFiled: April 23, 2021Date of Patent: October 3, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yen-Chieh Huang, Hai-Ching Chen, Yu-Ming Lin, Chung-Te Lin
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Patent number: 11776763Abstract: The present disclosure provides a printable curved-surface perovskite solar cell, including a curved-surface conductive substrate, a porous electron transport layer, a porous insulation layer, a porous back electrode layer and a perovskite filler. The curved-surface conductive substrate includes a curved-surface transparent substrate and a conductive layer deposited on the curved-surface transparent substrate. The porous electron transport layer, the porous insulation layer and the porous back electrode layer are sequentially deposited on the conductive layer from bottom to top. The perovskite filler is filled in pores of the porous electron transport layer, the porous insulation layer and the porous back electrode layer. The present disclosure further provides a method for preparing the printable curved-surface perovskite solar cell.Type: GrantFiled: March 7, 2022Date of Patent: October 3, 2023Assignee: HUBEI WONDER SOLAR LIMITED LIABILITY COMPANYInventors: Yusong Sheng, Jiakun Dai
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Patent number: 11769670Abstract: Methods for forming a rhenium-containing film on a substrate by a cyclical deposition are disclosed. The method may include: contacting the substrate with a first vapor phase reactant comprising a rhenium precursor; and contacting the substrate with a second vapor phase reactant. Semiconductor device structures including a rhenium-containing film formed by the methods of the disclosure are also disclosed.Type: GrantFiled: October 12, 2021Date of Patent: September 26, 2023Assignee: ASM IP Holding B.V.Inventor: Varun Sharma
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Patent number: 11765910Abstract: The disclosed technology relates to a selector device for a memory array, and a method of forming the selector device. In some embodiments, the selector device comprises a first electrode layer embedded in an oxide; a second electrode layer arranged above the first electrode layer and separated from the first electrode layer by the oxide; and a semiconductor material forming a semiconductor layer on the top surface of the second electrode layer, and extending through the second electrode layer and the oxide onto the top surface of the first electrode layer, wherein the semiconductor material contacts the first electrode layer and the second electrode layer. In some embodiments, the selector device helps to solve the sneak path problem in the memory array it is inserted into.Type: GrantFiled: November 6, 2020Date of Patent: September 19, 2023Assignee: IMEC vzwInventors: Gaspard Hiblot, Shamin Houshmand Sharifi, Luka Kljucar
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Patent number: 11757011Abstract: A manufacturing method of a semiconductor device, includes providing a substrate; forming a stacked gate, including a floating gate and a control gate, on the substrate; forming a stacked gate by a deposition of a select gate conductive layer on the stacked gate; forming a trench in the stacked gate by etching the stacked gate to separate a first select gate pattern and a second select gate pattern; and forming a first select gate, a second select gate, a first transistor, and a second transistor simultaneously through an etch-back process of the stacked gate.Type: GrantFiled: November 18, 2021Date of Patent: September 12, 2023Assignee: KEY FOUNDRY CO., LTD.Inventors: Min Kuck Cho, Jae Hoon Kim, Seung Hoon Lee
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Patent number: 11749510Abstract: There is provided a plasma generating device that includes a first electrode connected to a high-frequency power supply, and a second electrode to be grounded, a buffer structure configured to form a buffer chamber that accommodates the first and second electrodes wherein the first electrode and the second electrode are alternately arranged such that a number of electrodes of the first electrode and the second electrode are in an odd number of three or more in total, and wherein the second electrode is used in common for two of the first electrode being respectively adjacent to the second electrode used in common, and wherein a gas supply port that supplies gas into a process chamber is installed on a wall surface of the buffer structure.Type: GrantFiled: March 12, 2021Date of Patent: September 5, 2023Assignee: KOKUSAI ELECTRIC CORPORATIONInventors: Akihiro Sato, Tsuyoshi Takeda, Yukitomo Hirochi
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Patent number: 11740559Abstract: Apparatuses and methods are described for removing edge bead on a wafer associated with a resist coating comprising a metal containing resist compositions. The methods can comprise applying a first bead edge rinse solution along a wafer edge following spin coating of the wafer with the metal based resist composition, wherein the edge bead solution comprises an organic solvent and an additive comprising a carboxylic acid, an inorganic fluorinated acid, a tetraalkylammonium compound, or a mixture thereof. Alternatively or additionally, the methods can comprise applying a protective composition to the wafer prior to performing an edge bead rinse. The protective composition can be a sacrificial material or an anti-adhesion material and can be applied only to the wafer edge or across the entire wafer in the case of the protective composition. Corresponding apparatuses for processing the wafers using these methods are presented.Type: GrantFiled: October 11, 2021Date of Patent: August 29, 2023Assignee: Inpria CorporationInventors: Mollie Waller, Brian J. Cardineau, Kai Jiang, Alan J. Telecky, Stephen T. Meyers, Benjamin L. Clark
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Patent number: 11735506Abstract: In an example, an apparatus comprises a lead frame that includes a first row of leads, a first pad coupled to the first row of leads, and a second row of leads parallel to the first row of leads. The lead frame also includes a second pad coupled to the second row of leads. The first and second pads are separated by a gap, and each of the first and second pads has a substantially uniform thickness. The apparatus also includes a device coupled to the first and second pads. The first and second pads are exposed to an exterior of the apparatus.Type: GrantFiled: November 30, 2018Date of Patent: August 22, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Hung-Yu Chou, Bo-Hsun Pan, Yuh-Harng Chien, Fu-Hua Yu, Steven Alfred Kummerl, Jie Chen, Rajen M. Murugan
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Patent number: 11728438Abstract: A substrate in a split-gate memory device has a memory cell region including a connecting subregion and a functional subregion. A source region is formed in the substrate, and first and second gate structures mirrored to each other are formed on the substrate on opposing sides of the source region. In the connecting subregion, control gates of the first and second gate structures and the source region are electrically connected by electrical connections. In the split-gate memory device, the arrangement of the functional and connecting subregions in the memory cell region and external connection of the control gates in the first and second gate structures and the source region in the connecting subregion, which are exposed by etching, by the electrical connections in the connecting subregion result in area savings of the memory cell region.Type: GrantFiled: April 21, 2021Date of Patent: August 15, 2023Assignee: Shanghai Huahong Grace Semiconductor Manufacturing CorporationInventors: Tao Yu, Binghan Li
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Patent number: 11728399Abstract: A flash memory device includes a floating gate electrode formed within a substrate semiconductor layer having a doping of a first conductivity type, a pair of active regions formed within the substrate semiconductor layer, having a doping of a second conductivity type, and laterally spaced apart by the floating gate electrode, an erase gate electrode formed within the substrate semiconductor layer and laterally offset from the floating gate electrode, and a control gate electrode that overlies the floating gate electrode. The floating gate electrode may be formed in a first opening in the substrate semiconductor layer, and the erase gate electrode may be formed in a second opening in the substrate semiconductor layer. Multiple instances of the flash memory device may be arranged as a two-dimensional array of flash memory cells.Type: GrantFiled: October 8, 2021Date of Patent: August 15, 2023Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Yu-Chu Lin, Chia-Ming Pan, Chi-Chung Jen, Wen-Chih Chiang, Keng-Ying Liao, Huai-jen Tung
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Patent number: 11715784Abstract: A semiconductor substrate is provided. A trench isolation region is formed in the semiconductor substrate. A resist pattern having an opening exposing the trench isolation region and partially exposing the semiconductor substrate is disposed adjacent to the trench isolation region. A first ion implantation process is performed to implant first dopants into the semiconductor substrate through the opening, thereby forming a well region in the semiconductor substrate. The trench isolation region is within the well region. A second ion implantation process is performed to implant second dopants into the semiconductor substrate through the opening, thereby forming an extended doped region contiguous with the well region. The resist pattern is then removed. After removing the resist pattern, a gate dielectric layer is formed on the semiconductor substrate. A gate is then formed on the gate dielectric layer. The gate overlaps with the extended doped region.Type: GrantFiled: May 26, 2022Date of Patent: August 1, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Zhi-Cheng Lee, Wei-Jen Chen, Kai-Lin Lee, Tai-Ju Chen
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Patent number: 11705495Abstract: Provided is a memory device including a plurality of stack structures disposed on a substrate; and a dielectric layer. Each stack structure includes a first conductive layer, a second conductive layer, an inter-gate dielectric layer, a metal silicide layer, and a barrier layer. The second conductive layer is disposed on the first conductive layer. The inter-gate dielectric layer is disposed between the first and second conductive layers. The metal silicide layer is disposed on the second conductive layer. The barrier layer is disposed between the metal silicide layer and the second conductive layer. The dielectric layer laterally surrounds a lower portion of the plurality of stack structures to expose a portion of the metal silicide layer of the plurality of stack structures.Type: GrantFiled: May 20, 2021Date of Patent: July 18, 2023Assignee: Winbond Electronics Corp.Inventors: Yi-Tsung Tsai, Chih-Hao Lin
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Patent number: 11700729Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material comprises longitudinally-alternating first and second regions that individually have a vertically-elongated seam therein. The vertically-elongated seam in the first regions are taller than in the second regions. Additional embodiments, including method, are disclosed.Type: GrantFiled: November 12, 2021Date of Patent: July 11, 2023Assignee: Micron Technology, Inc.Inventors: Yi Hu, Ramey M. Abdelrahaman, Narula Bilik, Daniel Billingsley, Zhenyu Bo, Joan M. Kash, Matthew J. King, Andrew Li, David Neumeyer, Wei Yeeng Ng, Yung K. Pak, Chandra Tiwari, Yiping Wang, Lance Williamson, Xiaosong Zhang
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Patent number: 11700771Abstract: A bonded body includes a supporting substrate, silicon oxide layer provided on the supporting substrate, and a piezoelectric material substrate provided on the silicon oxide layer and composed of a material selected from the group consisting of lithium niobate, lithium tantalate and lithium niobate-lithium tantalite. A nitrogen concentration at an interface between the piezoelectric material substrate and silicon oxide layer is higher than a nitrogen concentration at an interface between the silicon oxide layer and the supporting substrate.Type: GrantFiled: March 30, 2020Date of Patent: July 11, 2023Assignee: NGK INSULATORS, LTD.Inventors: Yuji Hori, Takahiro Yamadera, Tatsuro Takagaki
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Patent number: 11685648Abstract: Microelectromechanical systems (MEMS) packages and methods of manufacture thereof are described. In an embodiment, a method of manufacturing a MEMS package may include attaching a MEMS structure having a capping structure thereon to a device wafer comprising a plurality of first devices formed therein to form a wafer level MEMS package; and singulating the device wafer having the MEMS structure attached thereto to form a plurality of chip scale MEMS packages.Type: GrantFiled: July 19, 2021Date of Patent: June 27, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Hua Yu, Kuo-Chung Yee
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Patent number: 11682736Abstract: In some implementations, one or more semiconductor processing tools may deposit a first dielectric layer on a substrate of a semiconductor device. The one or more semiconductor processing tools may deposit a floating gate on the first dielectric layer. The one or more semiconductor processing tools may deposit a second dielectric layer on the floating gate and on the substrate of the semiconductor device. The one or more semiconductor processing tools may deposit a first control gate on a first portion of the second dielectric layer. The one or more semiconductor processing tools may deposit a second control gate on a second portion of the second dielectric layer, wherein a third portion of the second dielectric layer is between the first control gate and the floating gate and between the second control gate and the floating gate.Type: GrantFiled: January 7, 2021Date of Patent: June 20, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chun Shen, Chi-Chung Jen, Ya-Chi Hung, Yu-Chu Lin, Wen-Chih Chiang
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Patent number: 11682590Abstract: A semiconductor structure includes a first semiconductor fin and a second semiconductor fin adjacent to the first semiconductor fin, a first epitaxial source/drain (S/D) feature disposed over the first semiconductor fin, a second epitaxial S/D feature disposed over the second semiconductor fin, an interlayer dielectric (ILD) layer disposed over the first and the second epitaxial S/D features, and an S/D contact disposed over and contacting the first epitaxial S/D feature, where a portion of the S/D contact laterally extends over the second epitaxial S/D feature, and the portion is separated from the second epitaxial S/D feature by the ILD layer.Type: GrantFiled: August 2, 2021Date of Patent: June 20, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yi-Hsiung Lin, Yi-Hsun Chiu, Shang-Wen Chang
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Patent number: 11682718Abstract: A vertical bipolar junction transistor may include an intrinsic base epitaxially grown on a first emitter or collector, the intrinsic base being compositionally graded, a second collector or emitter formed on the intrinsic base, and an extrinsic base formed all-around the intrinsic base. The extrinsic base may be isolated from the first emitter or collector by a first spacer. The extrinsic base may be isolated from the second collector or emitter by a second spacer. The extrinsic base may have a larger bandgap than the intrinsic base. The intrinsic base may be doped with a p-type dopant, and the first emitter or collector, and the second collector or emitter may be doped with an n-type dopant. The first emitter or collector, the intrinsic base, and the second collector or emitter may be made of a III-V semiconductor material.Type: GrantFiled: April 15, 2021Date of Patent: June 20, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alexander Reznicek, Bahman Hekmatshoartabari, Tak H. Ning, Liying Jiang
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Patent number: 11677015Abstract: In a method of manufacturing a semiconductor device, a fin structure having a channel region protruding from an isolation insulating layer disposed over a semiconductor substrate is formed, a cleaning operation is performed, and an epitaxial semiconductor layer is formed over the channel region. The cleaning operation and the forming the epitaxial semiconductor layer are performed in a same chamber without breaking vacuum.Type: GrantFiled: December 2, 2020Date of Patent: June 13, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ya-Wen Chiu, Yi Che Chan, Lun-Kuang Tan, Zheng-Yang Pan, Cheng-Po Chau, Pin-Ju Liang, Hung-Yao Chen, De-Wei Yu, Yi-Cheng Li