Abstract: An electronic device can include a NVM cell. The NVM cell can include a drain/source region, a source/drain region, a floating gate electrode, a control gate electrode, and a select gate electrode. The NVM cell can be fabricated using a process flow that also forms a power transistor, high-voltage transistors, and low-voltage transistors on the same die. A relatively small size for the NVM can be formed using a hard mask to define a gate stack and spacer between gate stack and select gate electrode. A gate dielectric layer can be used for the select gate electrode and transistors in a low-voltage region and allows for a fast read access time.

Abstract: A method includes forming a first through-via from a first conductive pad of a first device die, and forming a second through-via from a second conductive pad of a second device die. The first and second conductive pads are at top surfaces of the first and the second device dies, respectively. The first and the second conductive pads may be used as seed layers. The second device die is adhered to the top surface of the first device die. The method further includes encapsulating the first and the second device dies and the first and the second through-vias in an encapsulating material, with the first and the second device dies and the first and the second through-vias encapsulated in a same encapsulating process. The encapsulating material is planarized to reveal the first and the second through-vias. Redistribution lines are formed to electrically couple to the first and the second through-vias.

Abstract: An evaporating mask plate, an evaporating mask plate set and an evaporating system are provided. The evaporating mask plate includes a mask pattern plate. The evaporating mask pattern plate includes an evaporating area and a test area located around the evaporating area. The test area is provided with at least two test element groups located in different regions of the test area, and each test element group includes at least one test hole for alignment.

Abstract: A semiconductor module including a cooling apparatus and a semiconductor device mounted on the cooling apparatus is provided. The cooling apparatus includes a cooling fin arranged below the semiconductor device, a main-body portion flow channel through which a coolant flows in a predetermined direction to cool the cooling fin, a first coolant flow channel that is connected to one side of the main-body portion flow channel and has a first inclined portion upwardly inclined toward the main-body portion flow channel, and a conveying channel that, when seen from above, lets the coolant into the first coolant flow channel from a direction perpendicular to the predetermined direction or lets the coolant out of the first coolant flow channel in the direction perpendicular to the predetermined direction.

Abstract: A display device comprises a display panel substrate and a glass substrate over said display panel substrate, wherein said display panel substrate comprises multiple contact pads, a display area, a first boundary, a second boundary, a third boundary and a fourth boundary, wherein said display area comprises a first edge, a second edge, a third edge and a fourth edge, wherein said first boundary is parallel to said third boundary and said first and third edges, wherein said second boundary is parallel to said fourth boundary and said second and fourth edges, wherein a first least distance between said first boundary and said first edge, wherein a second least distance between said second boundary and said second edge, a third least distance between said third boundary and said third edge, a fourth distance between said fourth boundary and said fourth edge, and wherein said first, second, third and fourth least distances are smaller than 100 micrometers, and wherein said glass substrate comprising multiple meta

Abstract: A method includes forming a first through-via from a first conductive pad of a first device die, and forming a second through-via from a second conductive pad of a second device die. The first and second conductive pads are at top surfaces of the first and the second device dies, respectively. The first and the second conductive pads may be used as seed layers. The second device die is adhered to the top surface of the first device die. The method further includes encapsulating the first and the second device dies and the first and the second through-vias in an encapsulating material, with the first and the second device dies and the first and the second through-vias encapsulated in a same encapsulating process. The encapsulating material is planarized to reveal the first and the second through-vias. Redistribution lines are formed to electrically couple to the first and the second through-vias.

Abstract: According to an embodiment, provided is a semiconductor device including: a first electrode; a second electrode; and a silicon carbide layer disposed between the first electrode and the second electrode, the silicon carbide layer including: a first silicon carbide region of an n-type; and a second silicon carbide region disposed between the first silicon carbide region and the first electrode, the second silicon carbide being in contact with the first electrode, and the second silicon carbide containing one oxygen atom bonding with four silicon atoms.

Abstract: Provided is a semiconductor device whose performance is improved. A p type body region is formed in an n type semiconductor layer containing silicon carbide, and a gate electrode is formed on the body region with a gate insulating film interposed therebetween. An n type source region is formed in the body region on a side surface side of the gate electrode, and the body region and a source region are electrically connected to a source electrode. A p type field relaxation layer FRL is formed in the semiconductor layer on the side surface side of the gate electrode, and the source electrode is electrically connected to the field relaxation layer FRL. The field relaxation layer FRL constitutes a part of the JFET 2Q which is a rectifying element, and a depth of the field relaxation layer FRL is shallower than a depth of the body region.

Abstract: A ferroelectric thin-film structure includes at least one first atomic layer and at least one second atomic layer. The first atomic layer includes a first dielectric material that is based on an oxide, and the second atomic layer includes both the first dielectric material and a dopant that has a bandgap greater than a bandgap of the dielectric material.

Abstract: A read-only memory cell array includes a first storage state memory cell and a second storage state memory cell. The first storage state memory cell includes a first transistor and a second transistor. The first transistor is connected to a source line and a word line. The second transistor is connected to the first transistor and a first bit line. The second storage state memory cell includes a third transistor and a fourth transistor. The third transistor is connected to the source line and the word line. The fourth transistor is connected to the third transistor and a second bit line. A gate terminal of the fourth transistor is connected to a gate terminal of the third transistor.

Abstract: In an embodiment, a method includes: forming a fin extending from a substrate; forming a first gate mask over the fin, the first gate mask having a first width; forming a second gate mask over the fin, the second gate mask having a second width, the second width being greater than the first width; depositing a first filling layer over the first gate mask and the second gate mask; depositing a second filling layer over the first filling layer; planarizing the second filling layer with a chemical mechanical polish (CMP) process, the CMP process being performed until the first filling layer is exposed; and planarizing the first filling layer and remaining portions of the second filling layer with an etch-back process, the etch-back process etching materials of the first filling layer, the second filling layer, the first gate mask, and the second gate mask at the same rate.

Abstract: A memory device includes a well, a first gate layer, a second gate layer, a doped region, a blocking layer and an alignment layer. The first gate layer is formed on the well. The second gate layer is formed on the well. The doped region is formed within the well and located between the first gate layer and the second gate layer. The blocking layer is formed to cover the first gate layer, the first doped region and a part of the second gate layer and used to block electrons from excessively escaping. The alignment layer is formed on the blocking layer and above the first gate layer, the doped region and the part of the second gate layer. The alignment layer is thinner than the blocking layer, and the alignment layer is thinner than the first gate layer and the second gate layer.

Abstract: A hafnium oxide-based ferroelectric field effect transistor includes a substrate, an isolation region arranged around the substrate; a gate structure including a buffer layer, a floating gate electrode, a hafnium oxide-based ferroelectric film layer, a control gate electrode and a film electrode layer which are sequentially stacked from bottom to top at a middle part of an upper surface of the substrate, a side wall arranged outside the gate structure, a source region and a drain region arranged oppositely at two sides of the gate structure and are formed by extending from an inner side of the isolation region to the middle part of the substrate, a first metal silicide layer formed by extending from the inner side of the isolation region to the side wall, and a second metal silicide layer arranged on an upper surface of the gate structure.

Abstract: A double Schottky-barrier diode includes a semi-insulating substrate, a left mesa formed by growth and etching on the semi-insulating substrate, a middle mesa formed by growth and etching on the semi-insulating substrate, a right mesa formed by growth and etching on the semi-insulating substrate, two anode probes and two air-bridge fingers. The two Schottky contacts are closely fabricated on the same mesa (middle mesa) in a back-to-back manner to obtain even symmetric C-V characteristics and odd symmetric I-V characteristics from the device level. The output of a frequency multiplier fabricated using the double Schottky-barrier diode only has odd harmonics, but no even harmonics, which is suitable for the production of high-order frequency multipliers. The cathodes of the two Schottky contacts are connected by the buffer layer without ohmic contact.

Abstract: A semiconductor device constituting a non-volatile memory includes a semiconductor portion of a first conductivity type, a first well of a second conductivity type, a second well of the second conductivity type, an insulating film, and a conductive layer. The first well includes a trench extending from the surface of the semiconductor portion to an inside of the first well. The insulating film extends on a surface inside the trench. A conductive portion formed continuous with the conductive layer is disposed on the insulating film inside the trench.

Abstract: The present disclosure relates to thin-form-factor reconstituted substrates and methods for forming the same. The reconstituted substrates described herein may be utilized to fabricate homogeneous or heterogeneous high-density 3D integrated devices. In one embodiment, a silicon substrate is structured by direct laser patterning to include one or more cavities and one or more vias. One or more semiconductor dies of the same or different types may be placed within the cavities and thereafter embedded in the substrate upon formation of an insulating layer thereon. One or more conductive interconnections are formed in the vias and may have contact points redistributed to desired surfaces of the reconstituted substrate. The reconstituted substrate may thereafter be integrated into a stacked 3D device.

Abstract: Methods of forming memory structures are discussed. Specifically, methods of forming 3D NAND devices are discussed. Some embodiments form memory structures with a metal nitride barrier layer, an ?-tungsten layer, and a bulk metal material. The barrier layer comprises a TiXN or TaXN material, where X comprises a metal selected from one or more of aluminum (Al), silicon (Si), tungsten (W), lanthanum (La), yttrium (Yt), strontium (Sr), or magnesium (Mg).

Abstract: There is provided a substrate processing apparatus that includes a substrate support configured to support one or more substrates, a process chamber in which the one or more substrates are processed, a gas supplier configured to supply gas, and a plasma generator including a plurality of first rod-shaped electrodes connected to a high-frequency power supply; and a second rod-shaped electrode installed between two first rod-shaped electrodes is grounded; and a buffer structure configured to accommodate the plurality of first rod-shaped electrodes and the second rod-shaped electrode, and having a first wall surface on which a gas supply port that supplies gas into the process chamber is installed. Wherein the plasma generator is configured to convert gas into plasma by the plurality of first rod-shaped electrodes and the second rod-shaped electrode to supply the plasma-converted gas to the process chamber from the gas supply port.

Abstract: There is provided a plasma generating device that includes a first electrode connected to a high-frequency power supply, and a second electrode to be grounded, wherein the first electrode and the second electrode are alternately arranged such that a number of electrodes of the first electrode and the second electrode are in an odd number of three or more in total, and wherein the second electrode is used in common for two of the first electrode being respectively adjacent to the second electrode used in common.

Abstract: An object of the present invention is to provide a Schottky barrier diode less apt to cause dielectric breakdown due to concentration of an electric field. A Schottky barrier diode includes a semiconductor substrate 20 made of gallium oxide, a drift layer 30 made of gallium oxide and provided on the semiconductor substrate 20, an anode electrode 40 brought into Schottky contact with the drift layer 30, and a cathode electrode 50 brought into ohmic contact with the semiconductor substrate 20. The drift layer 30 has an outer peripheral trench 10 that surrounds the anode electrode 40 in a plan view, and the outer peripheral trench 10 is filled with a semiconductor material 11 having a conductivity type opposite to that of the drift layer 30. An electric field is dispersed by the presence of the thus configured outer peripheral trench 10. This alleviates electric field concentration on the corner of the anode electrode 40, making it less apt to cause dielectric breakdown.