Abstract: A right-angled electrical connector (30) has a one-piece electrically insulating body (32) molded over a subassembly (10) that includes a first electrically conductive member 12 with a hollow end (16) and an electrical contact (18a) mounted within the hollow end (16). In the mold the contact pin (18a) is electrically isolated from the member (12) and electrically insulating material of the body 32 flows around the contact pin (18a).

Abstract: An onboard connector is mounted on a circuit board. The onboard connector includes a plurality of terminals, each of which having a first electrical contact portion formed at one end portion thereof so as to be electrically connected to a mating connector and a second electrical contact portion formed at the other end portion thereof so as to be press-fitted into the corresponding through-hole land to electrically contact an inner peripheral surface of the through-hole land, the second electrical contact portion being plated, and a connector housing including a plurality of terminal receiving chambers which are open to a lower face of the connector housing. The terminals are received in the connector housing so that the second electrical contact portions project from the lower surface of the connector housing through openings of the respective terminal receiving chambers.

Abstract: A dielectric connector, for coupling radio-frequency signals from a signal generating device disposed inside an explosion-proof housing to a signal receiving device arranged outside the housing. The connector is configured to be sealingly inserted in an opening in the housing, and adapted to receive, from the inside of the housing, at least one internal conducting member, and receive, from the outside of the housing, at least one external conducting member. At least one of the conducting members is partly inserted in the connector and reactive (capacitive and/or inductive) coupling and galvanic separation is provided between the signal generating device and the signal receiving device. A combination of strong reactive coupling and secure operation in hazardous environments is enabled through the dielectric connector according to the present invention.

Abstract: A closing lever is provided for housing-shaped cable connectors having an upper and a lower component on one of the housing components. This closing lever operates to close both housing components in conjunction with a cam on the other housing component. This configuration ensures reliable closing without special exertion of force for the purpose of virtually automatically connecting two cables to each other.

Abstract: A detachable lamp socket includes a top cover, a mounting plate secured on the top cover, a housing detachably mounted on the mounting plate, a base secured in the housing, a circuit board mounted in the housing and supported by the base, and a locking rod movably mounted in the base and having a first end extended through the circuit board and the housing and retractably extended into the mounting plate to lock the housing onto the mounting plate. Thus, the housing can be rotated relative to the mounting plate to detach the housing from the mounting plate for maintenance of the lamp socket.

Abstract: A data flow control mechanism for a bus supporting two- and three-agent transactions includes a control logic to place an indication of a request onto a computer system bus. The agent placing the indication on the bus then waits to place data corresponding to the request onto the bus until it has received an indication from another agent coupled to the bus that the other agent is ready to receive the data.

Abstract: A PCI bus arbiter is provided as an additional PCI bus in PCI peer-to-peer bus bridge system. A bus control system having the PCI bus arbiter is also provided. The bus control system includes bus masters, a first PCI bus bridge, a second PCI bus bridge, an EISA/ISA bus bridge for changing structures of signals from the bus masters to be suitable for corresponding bus, a first arbiter in a main chip set, and a second arbiter for arbitration process. The second arbiter includes an edge detecting state machine which detects whether a PCI bus is accessed by a bus master, and produces a frame-signal which changes a logic state thereof according to an access condition of the PCI bus. The second arbiter may also include a priority resolve state machine which receives the frame-signal and produces priority values which determine an order of bus masters to use the PCI bus, wherein the priority values are changed according to the frame-signal.

Abstract: An communication system such as a host signal processing modem includes a host computer and a device that is coupled to communication lines and a host processor in the host computer. In a normal operating mode, the device generates periodic interrupts that cause the host processor to execute a software portion of the communication system. The software portion communicates with the device and implements protocols required to maintain communications with a remote system via communication lines. In a wait mode of the device, interrupts from the device to the host processor are suspended and selection logic in the device selects a communication signal such as a ring signal from the telephone lines as an interrupt to the host processor. While in wait mode, a power management system can place the system in a sleep mode because the periodic interrupts are suspended and do not indicate system activity that would prevent use of the sleep mode.

Abstract: An expansion port for a processing system peripheral device provides for a system power down prior to connection of another device to the port. A number of devices in a processing system are connected in a daisy chain. One of the devices includes a power supply for supplying power to each of the devices. Each of the devices includes a segment of an enable circuit for enabling or disabling the power supply. Each of the devices further includes an expansion port for connecting the enable circuit and other signals to another device in the daisy chain. An access panel is provided to cover the expansion port when the port is not in use. When the access panel is closed a switch located at the expansion port and coupled to the enable circuit of the device is actuated in order to enable the power supply. When the access panel is not in place and no other device is connected to the expansion port, the switch is in a different position which causes the power supply to be disabled.

Abstract: A method and apparatus for ordering data transfers includes an identifier of a critical portion of data being received from a requesting agent along with a request for data. Writeback data corresponding to the requested data is then transferred to the bus as a plurality of portions and ordered to ensure that a first portion which includes the critical portion of the data is transferred to the bus first.

Abstract: A method and apparatus for configuring a centralized arbitration scheme for a commonly accessed communication bus using arbiter devices with arbitration control circuitry included therein. The arbiter devices, each of which is associated with a separate bus master device, include arbitration control circuitry and are coupled to an arbitration control bus over which signals for arbitrating control to the commonly accessed communications bus are provided. During a configuration mode of operation, the same arbiter device connections to the arbitration control bus provide signals which are decoded via arbitration configuration circuitry on each device to provide a configuration status indicating whether other devices requiring arbitration are connected to the arbitration control bus and whether the arbitration control circuitry included on the particular device will be enabled to perform the required arbitration.

Abstract: A method and system for controlling access to a shared resource in a data processing system are described. According to the method, a number of requests for access to the resource are generated by a number of requestors that share the resource. Each of the requestors is dynamically associated with a priority weight in response to events in the data processing system. The priority weight indicates a probability that the associated requestor will be assigned a highest current priority. Each requester is then assigned a current priority that is determined substantially randomly with respect to previous priorities of the requestors. In response to the current priorities of the requestors, a request for access to the resource is granted.

Abstract: A hotel reservation system receives hotel reservations from a travel agent or other authorized user and enters information relating to the traveler and the reservation into a hotel reservation terminal. The reservation information is transferred to transaction processor via a communications link, where the processor automatically generates transaction documents related to the traveler, the travel agent and the hotel accommodations. These transaction documents are then sequentially transmitted by the processor using a facsimile to various parties having an interest in the reservation transaction. A confirmation document is sent to the hotel for which the accommodations have been reserved. The banking institution through which the transaction has been financed is notified to pay the hotel and others, and the travel agent is also sent a confirming transaction document.

Abstract: A multiple use core logic chip set is provided in a computer system that may be configured either as a bridge between an accelerated graphics port ("AGP") bus and host and memory buses, as a bridge between a 32 bit additional peripheral component interconnect ("PCI") bus and the host and memory buses, or as a bridge between a primary PCI bus and an additional PCI bus. The function of the multiple use chip set is determined at the time of manufacture of the computer system or in the field whether an AGP bus bridge or an additional 32 bit PCI bus bridge is to be implemented. The multiple use core logic chip set has an arbiter having Request ("REQ") and Grant ("GNT") signal lines for each PCI device utilized on the additional 32 bit PCI bus. Selection of the type of bus bridge (AGP or PCI) in the multiple use core logic chip set may be made by a hardware signal input, software during computer system configuration or power on self test ("POST").

Abstract: A system management mode address correction system for a computer provides correct address values on the address bus when the computer is in system management mode. Conventionally, bit 20 of the microprocessor's address outputs may be masked by asserting the FORCE A20 signal. The computer system also operates in a system management mode, which requires all of the address bits to be available for proper access to the system management interrupt vector. When the computer is in system management mode, the computer's microprocessor asserts a system management interrupt active (SMIACT*) signal. This signal is provided to a circuit which also receives the FORCE A20 signal. While the SMIACT signal is deactivated, the control circuit provides the true FORCE A20 signal to the computer system. When an SMI occurs, the SMIACT signal is activated and the FORCE A20 signal is disabled. As a result, the address generated by the microprocessor is asserted on the address bus.

Abstract: A system and method for determining which of plurality of peripheral components will have access to a peripheral component interconnect (PCI) bus when none of the plurality of peripheral components is currently requesting access to the PCI bus. In one embodiment a history buffer records all requests by a plurality of peripheral components for access to the PCI bus. The present invention then determines which of the plurality of peripheral components requests access to the PCI bus most often. Next, the present invention grants the peripheral component which requests access to the PCI bus most often access to the PCI bus when no other peripheral component is requesting access to the PCI bus. In so doing, the present invention "parks" the PCI bus on the peripheral component which has, in the past, requested access to the PCI bus most often.

Abstract: Accordingly, the preferred embodiment includes an improved computer-implemented method and apparatus for interfacing a STREAMS processing path of a local machine to a network communications protocol of a network having at least one remote machine connected thereon. The method includes the addition of information to the primitives defined for the NPI as well as the steps of examining the primitives received from an application and processing them according to their information. If the primitive is a bind primitive, the method determines if the primitive contains a TRANSPAC option. If the TRANSPAC option is set, the method stores this information in the NPI context or data structure. If the primitive contains a PVC option, the method sets a PVC option in the context. The method then builds an X.25 listen primitive and sends it to the network to establish a listen for a connection.

Abstract: A delay gate is provided within a control unit to delay the reset signal by a predetermined period of time to monitor the time at which the reset signal passes through the busline. If the busline length exceeds a prescribed length, then an LED is turned on. Or a resistance proportional to the length of a duplex bus signal line is connected to each connecting portion, a reference resistance is provided internally of the control unit and one of the duplex signal buslines of the connecting portion is grounded while the other is connected through the reference resistance to a reference power supply to compare the potential difference between the reference resistance and the connecting point of the duplex signal busline with a reference signal so that, when the busline length exceeds a prescribed value, the LED is turned on.

Abstract: An information processing apparatus having a work suspend/resume function which allows operator to use a main memory shared by different processings even when work suspension information is saved therein. A system for allowing a same operational environment as that set up in one information processing apparatus to be easily implemented in another information processing apparatus. A main memory used by a CPU for execution of processings has a function for storing information concerning the state of the information processing apparatus prevailing at a time point when execution of a given processing is suspended by a CPU for allowing the suspended processing to be performed in continuation later on. When the suspension state information has already been stored in the main memory by a former user, the suspension state information is transferred to a removable nonvolatile storage device so that the CPU can perform other processing than the suspended one by using the main memory.

Abstract: A method for translating information of balancing loads among bus segments to provide a load balanced bus system. The method includes the steps of displacing bus connection balancing loads from a least significant bit location of a digital device bus by an offset factor and translating information between the balancing load and a the digital device bus within a switch by circularly shifting the information by a number of bits equivalent to the offset factor.