Abstract: A high multiplexing degree or interleaving factor is achieved in a memory having banks of different capacities. A group judging circuit generates the relevant interleave group and addresses in such group on the basis of the start address and sub-bank number of each interleave. A bank selection circuit generates a sub-bank number and addresses in the sub-bank on the basis of the address in the group. A multiplier and adder generate addresses in the bank on the basis of the addresses in the sub-bank.

Abstract: An integrated processor/memory device comprising a main memory, a CPU, a victim cache, and a primary cache. The main memory comprises main memory banks. The victim cache stores victim cache sub-lines of words. Each of the victim cache sub-lines has a corresponding memory location in the main memory. When the CPU issues an address in the address space of the main memory, the victim cache determines whether a victim cache hit or miss has occurred in the victim cache. And, when a victim cache miss occurs, the victim cache replaces a selected victim cache sub-line of the victim cache sub-lines in the victim cache with a new victim cache sub-line. The primary cache comprises primary cache banks. Each of the primary cache banks stores one or more cache lines of words. Each cache line has a corresponding memory location in the corresponding main memory bank.

Abstract: A data processing system includes at least a first processor and a second processor that each have a respective translation lookaside buffer (TLB). In response to detection by the second processor of a TLB entry invalidation request, the second processor marks at least one memory referent instruction that is being processed by the second processor and invalidates a TLB entry in the TLB of the second processor. In response to receipt of a synchronization request at the second processor, the second processor indicates to the first processor that the second processor has invalidated the TLB entry if the second processor has completed processing the marked instruction. During the interval between receipt of the synchronization request and indicating to the first processor that the second processor has invalidated the TLB entry, the second processor continues to process instructions, including fetching instructions for processing.

Abstract: In order to store plural compressed records into a cache memory of a disk storage system in an easy-to-read manner, data to be stored in the cache memory is divided into plural data blocks each having two cache blocks in association with track blocks to which the data belongs and are compressed. The respective data blocks after the compression are stored in one or plural cache blocks. Information for retrieving each cache block from an in-track address for the data block is stored as part of retrieval information for the cache memory. When the respective data blocks in a record is read, the cache block storing the compressed data block is determined based on the in-track address of the data block and the retrieval information.

Abstract: In a data processing system having few initiators or several initiators with the same parameters, support for all initiators is provided by storing sets of parameters and corresponding lists of initiator IDs in cache entries. Based on the initiator ID in a selection command, the target selects the appropriate parameters and automatically transitions to data transfer mode. Low cost support for all initiators is thus provided.

Abstract: A backup system and method provides for creation of a reconciled snapshot backup image of a database while the database, residing on a disk array system, is in use by users. A backup computer running a commercial backup utility is connected between the array system and a tape storage system. While the backup is underway, write requests to the database are suspended until the data currently in those data blocks is copied and stored in an original data cache. The disk system address of the copied block and a pointer to the location of the block in the cache are stored in a map. The backup utility incrementally reads portions of the database from the disk system and forwards those portions to the tape system. Prior to each portion being forwarded to the tape system, all data blocks in the portion which have an address that corresponds to the address of a block in the cache are discarded and replaced with the data from the cache for that address.

Abstract: The invention is directed to a method of operating a control system which includes a nonvolatile memory unit having memory banks and a volatile memory unit for storing programs and data. Access is permitted to only a single one of the memory banks of the nonvolatile memory unit at a given time point and the memory bank permitting the access is addressable by using addresses which are located within a memory bank address space. The memory bank address space is common to all memory banks and adapted to the size of the memory banks. The nonvolatile memory and the volatile memory are driven in such a manner that the memory bank permitting the access is only accessible in part. When an addressing attempt is made via an address, which is assigned to that part of the particular memory bank which is not accessible, the volatile memory unit is shifted into a state permitting an access and the volatile memory is addressed via the address.

Abstract: There is provided a disc array control method and apparatus for controlling access to a disc drive consisting of a plurality of second data obtained by dividing a first data and a plurality of discs for storing the error correction data for the second data. Particularly, the disc array control method and apparatus of the present invention determines the information consisting of disc storing a plurality of the second data and address on the disc, data size of a plurality of second data and disc storing the error correction data and address on the disc to make equal the time required for access to a plurality of second data and error correction data and executes the access to the disc drive on the basis of the determined information. Thereby, the time required for access to the error correction data and sub-blocks can be set to equal time and the real-time property can be assured while maintaining high reliability.

Abstract: A user configurable RAID system designed to provide RAID functions as well as mass storage functions in a non-RAID mode. Flexibility is built into the system to allow the user to configure the SCSI bus to which removable drive modules are connected into one or more channels to define some of the drive modules in a RAID set and others as stand-alone drives which are independently operated or logically grouped and operated in a non-RAID mode. Removable internal SCSI bridges allow the SCSI bus to be configured into one or more channels. In the RAID mode, the system is configured to prevent a wrong drive from being removed from the system in the event of a drive failure. The system automatically unlatches only the failed drive. The RAID system includes an intelligent control unit ("ICU"), a RAID controller and a modem. The ICU allows the system administrator to access the RAID system Monitor Utility so that the status of the system may be monitored and its configuration changed.

Abstract: For a data processing device having a main memory comprised of a non-volatile memory and a CPU, memory protection and security are ensured for its programs and so forth. An auxiliary memory for storing security bit data is provided, for example, in an EPROM that comprises the main memory. Assuming that the result read by the CPU is "0" when a current flows between a drain and a source of a transistor in the EPROM, and "1" when the current does not flow, then the security bit data read from two transistors A and B are A=1 and B=1, which means they are set so that access to the main memory and a write to the auxiliary memory are prohibited. With A=0 and B=0, security is set, but a write to the auxiliary memory is permitted; with A=1 (0) and B=0 (1), security is reset.

Abstract: A method for processing memory requests and a memory controller that implements the method are disclosed. The method includes the steps of (a) receiving a first memory request from a first bus, (b) issuing a first coherency request on a second bus in order to process the first memory request, (c) storing the first coherency request in a storage area of the memory controller that is configured to receive memory requests from the second bus, and (d) processing the first coherency request from the storage area.

Abstract: A cache memory system connected between an input/output system having an input/output processor and a computer system having a system bus and a main memory with an input/output portion is provided in which data requested by the input/output processor is retrieved from the input/output portion of the main memory, a memory stores the requested data, and the data in the memory is updated either when the processor is not requesting data or when the processor is requesting data already in the memory. A method for replacing memory pages within a cache memory system is also provided.

Abstract: A computer system includes one or more microprocessors. The microprocessors assign a priority level to each memory operation as the memory operations are initiated. In one embodiment, the priority levels employed by the microprocessors include a fetch priority level and a prefetch priority level. The fetch priority level is higher priority than the prefetch priority level, and is assigned to memory operations which are the direct result of executing an instruction. The prefetch priority level is assigned to memory operations which are generated according to a prefetch algorithm implemented by the microprocessor. As memory operations are routed through the computer system to main memory and corresponding data transmitted, the elements involved in performing the memory operations are configured to interrupt the transfer of data for the lower priority memory operation in order to perform the data transfer for the higher priority memory operation.

Abstract: A circuit suitable for use in electronic systems which utilize Synchronous Dynamic Random Access Memory (SDRAM), and method according to the present invention comprises an application-specific integrated circuit. When a burst command is initiated by the memory controller, causing the SDRAM to perform a data transfer into or out of memory which require many consecutive clock cycles to complete, the circuit recognizes the SDRAM commands as those commands appear on the instruction bus. The circuit then analyzes other operations which are pending and which might be performed during otherwise unusable time periods while the burst operation is being performed by the SDRAM. The circuit issues instructions to initiate and complete these operations prior to the SDRAM command being completed.

Abstract: In order to generate internal addresses from an external address in a burst operation in a synchronous dynamic random access memory (SDRAM), an external address is latched in response to an external clock signal. First and second control signals are generated in synchronous with the external clock signal. An internal address for a first clock cycle of a burst operation is generated from the latched external address in a sequential mode in response to the first control signal using a first transfer path. An internal address for each of a second clock cycle and subsequent clock cycles of the burst operation in the sequential mode is generated in response to a second control signal using a second transfer path such that the internal address for each of the second clock cycle and subsequent clock cycles has substantially the same delay time as that of the internal address for the first clock cycle with respect to the external clock signal.

Abstract: An operating system has a file system which supports writing data to a file in a logical loop of clusters of storage locations. Writing can be performed in looped or unlooped modes, and a transition between looping and non-looped recording may be supported. Recording prior to occurrence of an asynchronous event is performed in a looped mode. After occurrence of the asynchronous event, the data collected in the looped portion is seamlessly merged with subsequently collected data by manipulation of pointers to the clusters by the operating system. By providing such a general structure for use in a file system of a computer, a substantially larger amount of memory is available for looped recording. In fact, several minutes of full motion broadcast quality video may be captured. In addition, by using the file system to handle the storage of data, an application does not need to arrange recorded information on a physical recording medium.

Abstract: Inconsistencies between cache and memory in a memory system operating in a computer are traced and corrected. A cache entry is checked against a counterpart memory entry to trace inconsistencies between the cache entry and the memory entry and to correct the cache entry. A page table entry in memory with a zero mapping mark is checked against a counterpart page entry in a translation lookaside buffer. Inconsistencies between the page table entry with a zero mapping mark and the existence of a counterpart page entry in the translation lookaside buffer is traced. The inconsistency is corrected by deleting the counterpart page entry in the translation lookaside buffer. Address mapping is checked comparing a page entry in the translation lookaside buffer against a counterpart page table entry in the memory. Inconsistencies between the page entry and the page table entry are traced and corrected.

Abstract: A method and apparatus for performing memory array/row scoreboarding in a dynamic access memory (DRAM) having dual bank access. The DRAM of the present invention allows dual simultaneous memory accesses into a memory divided into a plurality of arrays (e.g., 48 arrays). Each array of the DRAM contains a plurality of rows (e.g., 256). Each row of the DRAM contains storage for a certain amount of data bits (e.g., 1024). The DRAM in one configuration contains 1.5 Megabytes of memory. During a dual bank DRAM access, the system allows a first access for pre-opening a row (e.g., a page) of DRAM memory within a first array while simultaneously allowing a second access for reading/writing data to an opened row of another array aside from the first array. The present invention scoreboarding system tracks the rows that are currently open so that immediate read/write accesses can take place.

Abstract: Burst memory transfer from a memory to a microprocessor (CPU) is accomplished using analysis including determining first and second conditions. If an output enable is consecutively activated for more than one consecutive system clock cycle, following the address phase, the memory will initiate a burst transfer sequence. The addresses of subsequent data bytes or words following the first byte or word are determined by the memory advancing or incrementing its internal address counter until the burst transfer has been suspended or terminated. If the output enable pin is deactivated prior to the next address phase requested by the CPU, burst transfer will be suspended until the output enable pin is activated again. If the CPU requests the next address phase (chip enable activated) from the memory while the output enable is activated, the burst in progress will be terminated.

Abstract: An electrically rewritable nonvolatile semiconductor memory device made in accordance with a preferred embodiment of this invention, includes CAM data setting means for storing CAM data electrically written therein, wherein the CAM data is received from an external source; address fixing means for fixing a signal level of a portion of an internal address corresponding to an external address input from an external source based on the CAM data set in the CAM data setting means; and address switch means for switching a corresponding relationship between a portion of the external address input from an external source and a portion of the internal address based on the CAM data set in the CAM data setting means.