Abstract: A sampling frequency converting device. A memory unit stores an input signal D.sub.si having an input sampling frequency Fsi. An interpolation unit interpolates the readout signal from the storage unit. A sampling frequency ratio detection unit detects the current sampling frequency ratio R.sub.n between the input sampling frequency Fsi and the output sampling frequency F.sub.so and detects a new sampling frequency ratio R.sub.n NEW. based on the current sampling frequency ratio R.sub.n and a past detected value R.sub.n-1 preceding the current detected value by one detection period. A control unit having the sampling frequency detection unit controls the storage unit and the interpolating unit from the new sampling frequency ratio R.sub.n NEW.

Abstract: The present invention comprises two IDE disk drives for connection to an IDE bus, configured as a master drive and a slave drive. In the present invention, both drives are capable of receiving commands from a host computer connected to the IDE bus. Depending on the type of conunand which is received, the drive which receives the command determines the appropriate response to the command and initiates a sequence which, in cooperation with the other drive, ensures that the command is executed properly. Thus, the host sends commands over the IDE bus thinking that only one drive is present, and the drives handle between themselves how to respond to the command in a way that mimics the response of a single drive.

Abstract: Execution memory for use in processing a program unit for a database is allocated by inspecting an execution memory area pool for a previously allocated execution memory area. If a previously allocated execution memory area is found, then the previously allocated execution memory area is established as the execution memory area for executing the program unit. On the other hand, if a previously allocated execution memory area is not found, then a new execution memory area is allocated and configured for executing the program unit.

Abstract: A system for caching texel information in a cache data store, for use in a graphics rendering system which uses interpolative sampling to compute texture color values. The system includes a texel memory storing texel information, a graphics application program for using interpolative sampling to compute dynamic texture values, a first cache data storage for a number of the most-recently-retrieved texels, a second cache data storage for a previously-retrieved adjacent line of texels, cache tag blocks for determining whether the texels needed by the graphics accelerator system are cached in either of the first or second cache data stores, and a memory request generator for retrieving texels from texel memory upon indication of a miss by the cache tag blocks.

Abstract: When the OS judges that a read request to the secondary storage device from the user process is the sequential access, the OS judges whether prefetching is to be stopped before the data succeeding to the data designated by the request is prefetched, so as to decrease replacement of data prefetched to the main memory by other data before the data is used. The judgment is executed to prevent that succeeding data from being replaced by other data after the succeeding data is prefetched to the cache area in the main memory. That is, it is judged whether the data requested by the read request has already been prefetched, and has already been replaced by other data before the requested data is used by the user process, if the requested data has been prefetched. When these two conditions are met, prefetch is useless. The prefetching accompanying this read request is not executed, the prefetch stop flag is set, and prefetching is prohibited to the succeeding sequential access by this prefetch stop flag.

Abstract: A system for distributing logical volumes to an HSM system front end by ordering an array of logical volumes so that each volume that is likely to conflict with another volume is significantly separated from that other volume. Ordering is done iteratively, beginning with the disk type, and then iterating through the logical volume level, next through a target level (the physical disk), then SCSI level, then the disk adapter level, then system level until all the disks in all the disk adapters in the HSM system have been ordered. As each iteration occurs, units in a source array from the level being operated on are ordered so that those close to each other are moved apart, within the space available, in the destination array according to a procedure that establishes a gap between them that is based on an approximate ratio of the number of units in the source array to the number of spaces available in the destination array.

Abstract: A method and apparatus for storing a value in a non-volatile memory device is disclosed. The non-volatile memory device includes a plurality of address pins for concurrently receiving the respective bits of an address value while the non-volatile memory device is in a parallel interface mode. In response to one or more signals, the non-volatile memory device is transitioned to a serial interface mode to enable a serial input. A sequence of bits is received in the non-volatile memory device via the serial input. The first portion of the sequence of bits represents a store command and a second portion of the sequence of bits represents a data value. The data value represented by the second portion of the sequence of bits is then stored in the non-volatile memory device in response to the store command represented by the first portion of the sequence of bits.

Abstract: Microprocessor-based cards use application programs contained in a non-volatile user memory (MU), under the control of an operating system in a read-only memory (MSYS). To provide flexibility and security of access to the various memory zones without using a specific rigidly fixed circuitry, it is proposed that the memory access instructions of the application programs (PG1, PG2, PG3) should be interpreted and not performed directly. The interpreter is in the read-only memory (MSYS) or in the user memory and it carries out an access instruction as follows: it explores a reserved zone (ZR) of the user memory to find out if the requested access (access for reading, writing or performance) is cleared for the requested address. It performs the instruction only if the clearance is present. The reserved zone (ZR) which contains these clearances is updated during the writing, in the user memory, of a new application program. The updating can be done only by the operating system.

Abstract: Table walk logic and a second level access logic are tightly coupled to each other in a second level control unit that can operate in one of two modes, a translate mode that uses the table walk logic and an access mode that uses the second level access logic. In the translate mode, the second level control unit uses the table walk logic for automatic translation of a virtual address to a corresponding physical address. In the access mode, the second level control unit allows a word to be loaded from or stored into a given physical address. The second level control unit prioritizes operations in the two modes e.g. performs an operation in the access mode prior to performance of an operation in the translate mode. The table walk logic and the second level access logic can be integrated together into a single state machine, so that operations in the two modes are mutually exclusive and indivisible with respect to each other.

Abstract: Index prediction is used to access data in a memory array. A virtual address is received at an input. The virtual address is translated to a physical address. The memory array is accessed at a predicted address. A portion of the predicted address is compared to a portion of the physical address. If the portion of the predicted address is different from the portion of the physical address, then the predicted address was an incorrect prediction. The memory array is accessed at the physical address.

Abstract: A microprocessor for extracting one or more arbitrary channels of data from an image of any number of multiple channels with substantially minimized processing cycles per byte. Each channel of an image is preferably sampled with a predetermined data length. Subsequently the microprocessor partitions each of said sampled data according to a partitioning criterion into a plurality of partitioned components and combines a plurality of said partitioned components to form a data variable that is formed only with data components indicative of a selected channel of the image.

Abstract: A mapping unit is described for use in a computer system having a multiple bank memory. Each bank of the multiple bank memory includes a plug-in socket defining first and second memory rows. The mapping unit maps a memory control signal for the second row of a first socket adapted to mount one of a single-sided memory element or a double-sided memory element, to the first row of a second socket adapted to mount one of a single-sided memory element or a double-sided memory element, to provide a logical double-sided memory element when single-sided memory elements are plugged into the sockets. A poll routine in the computer system operates to determine the existence of single-sided memory elements in each of the first socket and the second socket, and asserts a select signal when the determination is positive.

Abstract: An improved programmable control sequencer and a method for its map allocation capable of reducing the size of program RAM used in a disk controller of a magnetic disk drive storage system, thereby efficiently reducing a work load of a microcontroller unit in the disk controller. The map allocation method is performed in a program random access memory having a 32.times.2 byte size of data storage area in the disk controller, the program random access memory being provided with the sequencer map allocation including a branch field, a next address/count field, an output field, a gate field, a field region and a data selection field. The branch field is provided with branch condition or count field enable information. The next address/count field selectively has a next address or a count value according to the branch condition.

Abstract: An address translation method for use in a system including a plurality of cluster nodes and including the steps of: at a source node, receiving over a first network a communication with a first destination address having an index portion and an offset portion, wherein the index portion includes a partition number portion; providing an address mapping table which maps a plurality of indexes to a corresponding plurality of node ID's, each of the plurality of node ID's identifying a different one of the plurality of cluster nodes; using the index portion from the first destination address as an index into the address mapping table to identify a node ID, wherein the identified node ID identifies a destination node; appending the identified node ID to the first destination address to generate a second destination address; and using the second destination address to send information to a second network of the destination node.

Abstract: A data processing apparatus having a memory access architecture which utilizes distributed shared-memory multiprocessors, and relates more particularly to a non-inclusive memory access mechanism in said architecture. The local memory in each node of shared memory is utilized as a backing store for blocks discarded from the processor cache to delay the address binding to the local memory until the blocks are discarded from the processor cache. Such avoids enforcement of the inclusion property and long latency due to the inclusion property. The invention further provides a method of maintaining coherency in a system which utilizes a distributed shared-memory multiprocessors architecture.

Abstract: A data storage system in which system activation is performed in cooperation with two host systems sharing a data storage system. A determination unit determines which of the two host systems makes access to the data storage system. A system access control unit controls access to the data storage system from the host systems to prevent competition between the host systems. Each of the host systems indicates completion of system activation to the other host system.

Abstract: An address translation buffer system in which a searching time of an address translation buffer is shortened.

Abstract: An integrated processor/memory device comprising a main memory, a CPU, a victim cache, and a primary cache. The main memory comprises main memory banks. The victim cache stores victim cache sub-lines of words. Each of the victim cache sub-lines has a corresponding memory location in the main memory. When the CPU issues an address in the address space of the main memory, the victim cache determines whether a victim cache hit or miss has occurred in the victim cache. And, when a victim cache miss occurs, the victim cache replaces a selected victim cache sub-line of the victim cache sub-lines in the victim cache with a new victim cache sub-line. The primary cache comprises primary cache banks. Each of the primary cache banks stores one or more cache lines of words. Each cache line has a corresponding memory location in the corresponding main memory bank.

Abstract: Inconsistencies between cache and memory in a memory system operating in a computer are traced and corrected. A cache entry is checked against a counterpart memory entry to trace inconsistencies between the cache entry and the memory entry and to correct the cache entry. A page table entry in memory with a zero mapping mark is checked against a counterpart page entry in a translation lookaside buffer. Inconsistencies between the page table entry with a zero mapping mark and the existence of a counterpart page entry in the translation lookaside buffer is traced. The inconsistency is corrected by deleting the counterpart page entry in the translation lookaside buffer. Address mapping is checked comparing a page entry in the translation lookaside buffer against a counterpart page table entry in the memory. Inconsistencies between the page entry and the page table entry are traced and corrected.

Abstract: A processor and method for translating a nonphysical address into a physical address are disclosed. A determination is made if a first entry set which could contain a particular entry that associates a selected nonphysical address with a corresponding physical address assigned to a device in the data processing system is stored within a first memory of the data processing system. In response to a determination that the first entry set is not stored in the first memory, a determination is made if a second entry set which could contain the particular entry is stored within the first memory. In response to a determination that the second entry set is stored in the first memory, a search of the second entry set is initiated in order to locate the particular entry. In response to locating the particular entry, the selected nonphysical address is translated to the corresponding physical address utilizing the particular entry.