Abstract: A method of fabricating an MRAM device includes forming a bottom electrode over a semiconductor substrate, forming a magnetic tunnel junction (MTJ) structure on the bottom electrode, and forming a top electrode on the MTJ structure. The method also includes forming spacers on sidewalls of the top electrode and the MTJ structure, and depositing a first dielectric layer to surround the spacers. The method further includes selectively depositing a patterned etch stop layer on the first dielectric layer and the spacers. In addition, the method includes depositing a second dielectric layer on the patterned etch stop layer and the top electrode, forming a via hole in the second dielectric layer to expose the top electrode, and forming a top electrode via in the via hole.

Abstract: A method for obtaining semiconducting carbon nanotubes is provided. An insulating substrate comprising hollow portions and non-hollow portions is provided. A plurality of electrodes is formed on a surface of the non-hollow portions. A plurality of carbon nanotubes is formed on a surface of the insulating substrate, and the carbon nanotubes stretches across the hollow portions. The insulating substrate, the plurality of electrodes, and the carbon nanotubes are placed into a cavity, and the cavity is evacuated. A voltage is applied between any two electrodes, and photos of carbon nanotubes suspended between the two electrodes are taken. In the photo, darker ones are the semiconducting carbon nanotubes, and brighter ones are metallic carbon nanotubes. Finally, the metallic carbon nanotubes are removed.

Abstract: Techniques to facilitate visualization of an application associated with an industrial automation environment are disclosed. In at least one implementation, a display composer interface is presented that enables a user to design a customized display layout for the application associated with the industrial automation environment. Data display instructions are received comprising a user selection of at least one data item associated with an operation of a machine in the industrial automation environment. Position information that identifies where to display the at least one data item is also received. The data display instructions and the position information are processed to generate the customized display layout for the application. Based on the customized display layout, a graphical user interface is rendered to the application having the at least one data item positioned according to the position information.

Abstract: Variations provide a metamaterial comprising a plurality of metamaterial repeat units containing a surface-patterned nanoparticle or microparticle that is coated with a metal in a surface pattern. The surface-patterned particle may include a dielectric material or a semiconductor material partially or fully coated with metal(s). In some embodiments, the surface-patterned particles are split ring resonators. Some variations provide a method of making a metamaterial, the method comprising: metallizing surfaces of particles, wherein particles are coated with metal(s) in a surface pattern; dispersing surface-patterned particles in a liquid solution at a starting pH; introducing a triggerable pH-control substance capable of generating an acid or base; and triggering the pH-control substance to generate an acid or base, thereby adjusting the solution pH to a titrated pH.

Abstract: Three-dimensional (3D) nonvolatile memory devices include a substrate having a well region of second conductivity type (e.g., P-type) therein and a common source region of first conductivity type (e.g., N-type) on the well region. A recess extends partially (or completely) through the common source region. A vertical stack of nonvolatile memory cells on the substrate includes a vertical stack of spaced-apart gate electrodes and a vertical active region, which extends on sidewalls of the vertical stack of spaced-apart gate electrodes and on a sidewall of the recess. Gate dielectric layers extend between respective ones of the vertical stack of spaced-apart gate electrodes and the vertical active region. The gate dielectric layers may include a composite of a tunnel insulating layer, a charge storage layer, a relatively high bandgap barrier dielectric layer and a blocking insulating layer having a relatively high dielectric strength.

Abstract: The present invention relates to a method of fabricating an electrode array, in which an underlying handle wafer is removed to provide a planar device having the electrode array. Also provided are wafers including a plurality of planar devices having an electrode array, as well as sensors including such an electrode array.

Abstract: According to one embodiment, a semiconductor memory device includes a stacked body, memory pillars, first and second insulation layers and an isolation region. The stacked body above a substrate includes conductive layers isolated from each other and stacked along a first direction crossing the substrate surface. The memory pillars extend through the stacked body along the first direction. The first insulation layer is provided above the memory pillars. The isolation region is provided higher than upper surfaces of the memory pillars in the stacked body along the first direction, and isolates the stacked body in a second direction crossing the first direction. The second insulation layer is provided on the first insulation layer and a side wall of the isolation region.

Abstract: A lighting apparatus including an organic light emitting diode includes an organic light emitting diode unit which includes an organic layer disposed on a substrate, wherein the organic light emitting diode emits light with an angle with respect to a normal direction of the organic layer; and an external light extracting layer which refracts the light emitted by the organic light emitting diode unit to the normal direction of the organic layer.

Abstract: A piezo-resistor-based sensor, and a method to fabricate such sensor, comprise a sensor having at least a sensing element provided on a flexible structure, such as a membrane or cantilever or the like. The sensing element includes at least one piezo-resistor comprising at least a first region of the flexible structure doped with dopant atoms of a first type. The flexible structure furthermore comprises a second doped region within it, at least partially overlapping the first doped region, forming a shield for shielding the sensing element from external electrical field interference, wherein dopant atoms of the second doped region are of a second type opposite to the dopant atoms of the first doped region, for generating a charge depletion layer within the flexible structure at the overlapping region between the first doped region and the second doped region.

Abstract: A spacer is provided to allow a surface mount device (SMD) to be surface mounted onto a PCB with greater degrees of freedom. The spacer is designed to be surface mountable to the PCB and includes an electrically non-conducting body that has a first surface facing the SMD, a second surface facing the PCB, and through holes and/or indents in the electrically non-conducting body to accommodate electrical conductors that provide electrical connections between the SMD and the PCB. The spacer may provide one or more of: an elevated height (so that the SMD is elevated above the PCB), an offset along the surface of the PCB relative to a designated position for the SMD on the PCB, or a tilt in one or more directions relative to a surface of the PCB.

Abstract: Provided is a light emitting device that includes a substrate; a first electrode formed by a first electrically conductive layer arranged over the substrate; an active light emitting layer arranged over said first electrically conductive layer, and that includes a host matrix and light emitting quantum dots embedded there within; and a second electrode formed by a second electrically conductive layer arranged over the active light emitting layer. The host matrix has charge carrier supplier quantum dots blended with the light emitting quantum dots, forming a binary blend where the charge carrier supplier quantum dots are made and arranged to supply charge carriers to the light emitting quantum dots, and wherein the light emitting quantum dots are made and arranged to accept the supplied charge carriers. Also provided is a spectrometer having the LED and a down-converting film for a LED.

Abstract: A curved array substrate includes a substrate, a first metal layer disposed on the substrate, an insulating layer disposed on the substrate and covering the first metal layer, a semiconductor layer disposed on the insulating layer and a second metal layer disposed on the insulating layer and connected to the semiconductor layer, and a via hole is defined in the insulating layer near a bending center thereof, and the second metal layer is connected to the first metal layer through the via hole.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method of forming a semiconductor device comprises forming a fin over a substrate, wherein the fin comprises a first semiconductor layer and a second semiconductor layer comprising different semiconductor materials, and the fin includes a channel region and a source/drain region; forming a dummy gate structure over the substrate and the fin; etching a portion of the fin in the source/drain region; selectively removing an edge portion of the second semiconductor layer in the channel region of the fin such that the second semiconductor layer is recessed, and an edge portion of the first semiconductor layer is suspended; performing a reflow process to the first semiconductor layer to form an inner spacer, wherein the inner spacer forms sidewall surfaces of the source/drain region of the fin; and epitaxially growing a sour/drain feature in the source/drain region.

Abstract: A semiconductor device includes a plurality of unit transistors that are arranged on a surface of a substrate in a first direction. Input capacitive elements are arranged so as to correspond to the unit transistors. An emitter common wiring line is connected to emitter layers of the unit transistors. A via-hole extending from the emitter common wiring line to a back surface of the substrate is disposed at a position overlapping the emitter common wiring line. A collector common wiring line is connected to collector layers of the unit transistors. The input capacitive elements, the emitter common wiring line, the unit transistors, and the collector common wiring line are arranged in this order in a second direction. Base wiring lines that connect the input capacitive elements to base layers of the corresponding unit transistors intersect the emitter common wiring line without physical contact.

Abstract: An object is to provide a semiconductor device having electrical characteristics such as high withstand voltage, low reverse saturation current, and high on-state current. In particular, an object is to provide a power diode and a rectifier which include non-linear elements. An embodiment of the present invention is a semiconductor device including a first electrode, a gate insulating layer covering the first electrode, an oxide semiconductor layer in contact with the gate insulating layer and overlapping with the first electrode, a pair of second electrodes covering end portions of the oxide semiconductor layer, an insulating layer covering the pair of second electrodes and the oxide semiconductor layer, and a third electrode in contact with the insulating layer and between the pair of second electrodes. The pair of second electrodes are in contact with end surfaces of the oxide semiconductor layer.

Abstract: An LED mounted method includes: providing a circuit substrate having a plurality of conductive pads; through a pick and place module, disposing a plurality of conductors on the conductive pads; disposing a plurality of LED chips on the circuit substrate, with each LED chip being disposed on at least two conductors; projecting a laser source generated by a laser generation module to each LED chip so that the laser source passes through the LED chip and is projected onto at least two conductors; and curing the conductor disposed between the LED chip and the circuit substrate by irradiation of the laser source so that the LED chip is mounted on the circuit substrate.

Abstract: A black matrix, a preparation method therefor, and a system thereof, a display substrate, and a display device are provided. The preparation method includes: forming a black matrix thin film on a substrate; on one side, away from the substrate, of the black matrix thin film, carrying out first exposure processing on the black matrix thin film; on one side, close to the substrate, of the black matrix thin film, carrying out second exposure processing on the black matrix thin film; and developing the black matrix thin film after the first exposure processing and the second exposure processing to form the black matrix.

Abstract: A field emission transistor uses carbon nanotubes positioned to extend along a substrate plane rather than perpendicularly thereto. The carbon nanotubes may be pre-manufactured and applied to the substrate and then may be etched to create a gap between the carbon nanotubes and an anode through which electrons may flow by field emission. A planar gate may be positioned beneath the gap to provide a triode structure.

Abstract: A semiconductor device includes a first composite III-V group compound semiconductor layer disposed on a composite substrate, and a second III-V group compound semiconductor layer disposed on the first composite III-V group compound semiconductor layer. The semiconductor device also includes a gate structure disposed on the second III-V group compound semiconductor layer, and a source electrode and a drain electrode disposed on the second III-V group compound semiconductor layer and at opposite sides of the gate structure. The semiconductor device further includes a field plate disposed between the gate structure and the drain electrode, and a conductive structure penetrating through the second III-V group compound semiconductor layer and the first composite III-V group compound semiconductor layer, wherein the field plate is electrically connected to the composite substrate through the conductive structure.

Abstract: A quantum computing device includes a first chip having a first substrate and one or more qubits disposed on the first substrate. Each of the one or more qubits has an associated resonance frequency. The quantum computing device further includes a second chip having a second substrate and at least one conductive surface disposed on the second substrate opposite the one or more qubits. The at least one conductive surface has at least one dimension configured to adjust the resonance frequency associated with at least one of the one or more qubits to a determined frequency adjustment value.