Patents Examined by Yasser Abdelaziez
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Patent number: 11600488Abstract: There is provided a technique that includes: loading an m-th substrate into a process chamber, wherein m is an integer less than n; forming a film on the m-th substrate by heating the m-th substrate in the process chamber; unloading the m-th substrate from the process chamber; waiting for a predetermined time in the process chamber, in a state where the substrates are not present in the process chamber, after the act of unloading; loading a next substrate, which is one of the n substrates to be processed next, into the process chamber, after the act of waiting; and forming a film on the next substrate by heating the next substrate in the process chamber.Type: GrantFiled: March 5, 2020Date of Patent: March 7, 2023Assignee: KOKUSAI ELECTRIC CORPORATIONInventors: Naofumi Ohashi, Toshiyuki Kikuchi
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Patent number: 11591210Abstract: A transducer assembly can include a base. The transducer assembly can include a stress isolation standoff located on the base. The transducer assembly can include a MEMS die disposed on the stress isolation standoff. The transducer assembly can include a die attach adhesive disposed between the MEMS die and the base. The die attach adhesive can bond the MEMS die to the base. The stress isolation standoff can be embedded in the die attach adhesive between the base and the MEMS die.Type: GrantFiled: October 6, 2020Date of Patent: February 28, 2023Assignee: Knowles Electronics, LLCInventor: Timothy Pachla
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Patent number: 11584639Abstract: A method of manufacturing a plurality of resonators, each formed by a membrane sealing a cavity, includes forming a plurality of cavities starting from one face called the front face of a support substrate, the plurality of cavities comprising central cavities and peripheral cavities arranged around the assembly formed by the central cavities, and forming central membranes and peripheral membranes covering the central cavities and peripheral cavities, respectively, by the transfer of a coverage film on the front face of the support substrate. At least part of the peripheral membranes is removed.Type: GrantFiled: June 3, 2020Date of Patent: February 21, 2023Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Bruno Fain, Caroline Coutier
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Patent number: 11584637Abstract: A system of flexural, actuating, and semiconducting elements of part-types necessary to assemble actuated robotic systems. These parts are joined with a common interface, interlocking with neighboring parts to form a regular lattice structure. Primary considerations for the design of the part interfaces include ease of assembly and the ability to transfer mechanical loads and electronic signals to neighboring parts. The parts are designed to be assembled vertically so structures can he built incrementally one part at a time. They can be easily fabricated at a range of length-scales using a variety of two-dimensional manufacturing processes. These processes include, for example, stamping and laminating, which enable high-throughput production. The simple mechanical interfaces between parts also enable disassembly allowing for reconfigurability and reuse. The interlocking nature of these assemblies allows loads to be distributed through many parallel load-paths.Type: GrantFiled: August 23, 2018Date of Patent: February 21, 2023Assignee: Massachusetts Institute of TechnologyInventors: William Kai Langford, Amanda Ghassaei, Neil Gershenfeld
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Patent number: 11584641Abstract: The purpose of the present invention is to provide a method for manufacturing a three-dimensionally structured member which can be made by a simpler process. The method for manufacturing a three-dimensionally structured member includes shaping a flat plate-shaped base member to produce a three-dimensionally structured member having a plurality of sections that are different from one another in thickness. The manufacturing method comprises: a mask formation step for forming a mask over the whole of at least one main surface of the base member; a mask removal step for removing a part of the mask; and an etching step for etching an exposed part of the base member wherein a combination of the mask removal step and the etching step is performed on the mask and the base member that correspond to each of the plurality of sections of the three-dimensionally structured member, in the order from thinnest to the thickest of thicknesses of the three-dimensionally structured members.Type: GrantFiled: July 16, 2019Date of Patent: February 21, 2023Assignee: TOKYO KEIKl INC.Inventors: Kazuaki Tani, Takayoshi Yamaguchi, Takayuki Tamaki
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Patent number: 11571711Abstract: A method of forming an ultrasonic transducer device includes forming an insulating layer having topographic features over a lower transducer electrode layer of a substrate; forming a conformal, anti-stiction layer over the insulating layer such that the conformal layer also has the topographic features; defining a cavity in a support layer formed over the anti-stiction layer; and bonding a membrane to the support layer.Type: GrantFiled: November 14, 2019Date of Patent: February 7, 2023Assignee: BFLY OPERATIONS, INC.Inventors: Lingyun Miao, Keith G. Fife, Jianwei Liu, Jonathan M. Rothberg
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Patent number: 11554952Abstract: A method for closing openings in a flexible diaphragm of a MEMS element. The method includes: providing at least one opening in the flexible diaphragm, situating sealing material in the area of the at least one opening, melting-on at least the applied sealing material in the area of the at least one opening, and subsequently cooling the melted-on material to close the at least one opening.Type: GrantFiled: December 20, 2018Date of Patent: January 17, 2023Assignee: Robert Bosch GmbHInventors: Bernhard Gehl, Christoph Hermes, Juergen Butz
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Patent number: 11551978Abstract: Disclosed are semiconductor devices and methods of fabricating the same. The method comprises sequentially stacking a lower sacrificial layer and an upper sacrificial layer on a substrate, patterning the upper sacrificial layer to form a first upper sacrificial pattern and a second upper sacrificial pattern, forming a first upper spacer and a second upper spacer on sidewalls of the first upper sacrificial pattern and a second upper sacrificial pattern, respectively, using the first and second upper spacers as an etching mask to pattern the lower sacrificial layer to form a plurality of lower sacrificial patterns, forming a plurality of lower spacers on sidewalls of the lower sacrificial patterns, and using the lower spacers as an etching mask to pattern the substrate. The first and second upper spacers are connected to each other.Type: GrantFiled: November 5, 2020Date of Patent: January 10, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young-Hun Kim, Jaeseok Yang, Haewang Lee
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Patent number: 11542603Abstract: A technique capable of suppressing an adhesion of deposits to an inside of a reaction vessel of a substrate processing apparatus is described. According to one aspect thereof, there is provided a substrate processing apparatus including: a substrate retainer provided with a substrate support region; a heat insulator provided below the substrate support region; and a reaction vessel of a cylindrical shape in which the substrate retainer and the heat insulator are accommodated, wherein the reaction vessel includes: an auxiliary chamber protruding outward in a radial direction of the reaction vessel and extending along an extending direction from at least a position below an upper end of the heat insulator to a position facing the substrate support region; and a first cover provided in the auxiliary chamber along a plane perpendicular to the extending direction of the auxiliary chamber so as to divide an inner space of the auxiliary chamber.Type: GrantFiled: September 15, 2021Date of Patent: January 3, 2023Assignee: Kokusai Electric CorporationInventor: Hirohisa Yamazaki
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Patent number: 11542157Abstract: Provided is a microchip that can achieve a favorable bonding state in the bonding portion between first and second substrates even if the microchip is large in size. A microchip includes a first substrate made of a resin and a second substrate made of a resin, the first substrate and the second substrates being bonded to each other, and a channel surrounded by a bonding portion between the first substrate and the second substrate is formed by a channel forming step formed at least in the first substrate. Further, a noncontact portion is formed to surround the bonding portion, and an angle ?1 formed between a side wall surface of the channel forming step and a bonding surface continuous therewith satisfies ?1>90°.Type: GrantFiled: August 7, 2018Date of Patent: January 3, 2023Assignee: Ushio Denki Kabushiki KaishaInventors: Kenichi Hirose, Makoto Yamanaka, Shinji Suzuki, Kenji Hatakeyama
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Pressure sensor including a microelectromechanical transducer and relating pressure-detection method
Patent number: 11535508Abstract: A pressure sensor including: a structure which delimits a main cavity of a closed type, the structure being at least partially deformable as a function of a pressure external to the structure; and a MEMS device, which is arranged in the main cavity and generates an output signal, which is of an electrical type and is indicative of the pressure inside the main cavity.Type: GrantFiled: February 24, 2020Date of Patent: December 27, 2022Assignee: STMICROELECTRONICS S.r.l.Inventor: Mario Giuseppe Pavone -
Patent number: 11527697Abstract: A quantum computing device includes a first chip having a first substrate and one or more qubits disposed on the first substrate. Each of the one or more qubits has an associated resonance frequency. The quantum computing device further includes a second chip having a second substrate and at least one conductive surface disposed on the second substrate opposite the one or more qubits. The at least one conductive surface has at least one dimension configured to adjust the resonance frequency associated with at least one of the one or more qubits to a determined frequency adjustment value.Type: GrantFiled: December 3, 2020Date of Patent: December 13, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dongbing Shao, Markus Brink, Firat Solgun, Jared Barney Hertzberg
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Patent number: 11508834Abstract: A compound semiconductor device comprises a heterojunction bipolar transistor including a plurality of unit transistors, a capacitor electrically connected between a RF input wire and a base wire for each unit transistor of the unit transistors, and a bump electrically connected to emitters of the unit transistors. The unit transistors are arranged in a first direction. The bump is disposed above the emitters of the unit transistors while extending in the first direction. The transistors include first and second unit transistors, the respective emitters of the first and second unit transistors being disposed on first and second sides, respectively, of a second direction, perpendicular to the first direction, with respect to a center line of the bump extending in the first direction. The capacitor is not covered by the bump, and respective lengths of the respective base wires connected respectively to the first and second unit transistors are different.Type: GrantFiled: November 13, 2020Date of Patent: November 22, 2022Assignee: Murata Manufacturing Co., Ltd.Inventors: Kenji Sasaki, Kingo Kurotani, Takashi Kitahara, Shigeki Koya
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Patent number: 11472698Abstract: A method for producing damper structures on a micromechanical wafer. The method includes: providing an at least partially UV-transparent master mold for molding damper structures; inserting and pressing a micromechanical wafer into the master mold so that micromechanical structures in the wafer are aligned in relation to the damper structures; filling the master mold with UV-curing LSR and subsequent UV irradiation; and mold release and removal of the connected structure of the micromechanical wafer with attached dampers. A method for producing a singulated MEMS chip comprising a UV-cured damper is also described.Type: GrantFiled: April 5, 2021Date of Patent: October 18, 2022Assignee: Robert Bosch GmbHInventors: Michael Stumber, Stefan Apelt
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Patent number: 11456301Abstract: Embodiments of the present disclosure generally relate to a storage device. More specifically, embodiments described herein generally relate to a dynamic random-access memory and the method of making thereof. In one embodiment, a cell array includes at least an active region and a field region adjacent to the active region. The active region includes at least one trench, a dielectric layer disposed in the trench, a first conformal layer disposed on the dielectric layer, and a conductive material disposed on the first conformal layer. The field region includes a trench, a dielectric layer disposed in the trench, a second conformal layer disposed on the dielectric layer, and a conductive material disposed on the second conformal layer. The second conformal layer has a different composition than the first conformal layer.Type: GrantFiled: July 16, 2020Date of Patent: September 27, 2022Assignee: Applied Materials, Inc.Inventors: Arvind Kumar, Mahendra Pakala, Sanjeev Manhas, Satendra Kumar Gautam
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Patent number: 11444107Abstract: A manufacturing method of a display panel includes providing a substrate having a first surface and a second surface opposite to the first surface; forming a high-shielding position layer on the first surface, wherein the light-shielding positioning layer has at least one first alignment pattern; forming a transparent material layer on the second surface; forming a photoresist layer on the transparent material layer; performing an exposure process, such that a light beam passes through the at least one first alignment pattern to penetrate through the substrate and the transparent material layer to the photoresist layer; performing a developing process to pattern the photoresist layer and form a patterned photoresist layer; and performing an etching process to pattern the transparent positioning layer having at least one second alignment pattern. In a direction perpendicular to the substrate, at least one first alignment pattern overlaps with at least one second alignment pattern.Type: GrantFiled: September 30, 2020Date of Patent: September 13, 2022Assignee: AU Optronics CorporationInventors: Peng-Bo Xi, Chun-Cheng Cheng
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Patent number: 11440793Abstract: Described herein is a hydrogen sensor on medium or low temperature solid micro heating platform, comprising: a substrate; a thermal-insulating layer disposed above the substrate; a heating structure disposed above the thermal-insulating layer, and thermally and electrically isolated from the substrate by the thermal-insulating layer; a thermal-conducting layer covering the heating structure; and a sensitive layer disposed on the thermal-conducting layer. The sensitive layer can be heated to a set temperature by the heating structure to improve sensitivity and reduce the response time.Type: GrantFiled: December 24, 2019Date of Patent: September 13, 2022Assignee: Shanghai Jiaotong UniversityInventors: Guifu Ding, Qi Liu, Yan Wang, Yunna Sun
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Patent number: 11437377Abstract: A semiconductor device includes a first semiconductor layer having first and second regions, a plurality of first channel layers spaced apart from each other in a vertical direction on the first region of the first semiconductor layer, a first gate electrode surrounding the plurality of first channel layers, a plurality of second channel layers spaced apart from one another in the vertical direction on the second region of the first semiconductor layer, and a second gate electrode surrounding the plurality of second channel layers, wherein each of the plurality of first channel layers has a first crystallographic orientation, and each of the plurality of second channel layers has a second crystallographic orientation different from the first crystallographic orientation, and wherein a thickness of each of the plurality of first channel layers is different from a thickness of each of the plurality of second channel layers.Type: GrantFiled: September 24, 2020Date of Patent: September 6, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Woo Cheol Shin, Myung Gil Kang, Sadaaki Masuoka, Sang Hoon Lee, Sung Man Whang
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Patent number: 11434130Abstract: Described examples include an apparatus having a substrate with a substrate surface. The apparatus also includes an element with a planar surface facing the substrate surface and with a nonplanar surface opposite the planar surface facing away from the substrate surface.Type: GrantFiled: December 31, 2019Date of Patent: September 6, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Patrick Ian Oden, James Norman Hall
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Patent number: 11417518Abstract: There is included (a) forming a protective film on a surface of a third base by supplying a processing gas to a substrate in which a first base containing no oxygen, a second base containing oxygen, and the third base containing no oxygen and no nitrogen are exposed on a surface of the substrate; (b) modifying a surface of the second base to be fluorine-terminated by supplying a fluorine-containing gas to the substrate after the protective film is formed on the surface of the third base; and (c) selectively forming a film on a surface of the first base by supplying a film-forming gas to the substrate after the surface of the second base is modified.Type: GrantFiled: July 30, 2020Date of Patent: August 16, 2022Assignee: KOKUSAI ELECTRIC CORPORATIONInventors: Takayuki Waseda, Takashi Nakagawa, Kimihiko Nakatani, Motomu Degai, Yoshitomo Hashimoto