Abstract: A semiconductor device is provided. The semiconductor device comprising a first fin pattern and a second fin pattern which are separated by a first isolation trench and extend in a first direction, a third fin pattern which is spaced apart from the first fin pattern in a second direction intersecting the first direction and extends in the first direction, a fourth fin pattern which is separated from the third fin pattern by a second isolation trench, a first gate structure which intersects the first fin pattern and has a portion extending along an upper surface of the first fin pattern, a second gate structure which intersects the second fin pattern and has a portion extending along an upper surface of the second fin pattern and a first element isolation structure which fills the second isolation trench and faces a short side of the first gate structure.

Abstract: An IC structure includes a transistor, a source/drain contact, a metal oxide layer, a non-metal oxide layer, a barrier structure, and a via. The transistor includes a gate structure and source/drain regions on opposite sides of the gate structure. The source/drain contact is over one of the source/drain regions. The metal oxide layer is over the source/drain contact. The non-metal oxide layer is over the metal oxide layer. The barrier structure is over the source/drain contact. The barrier structure forms a first interface with the metal oxide layer and a second interface with the non-metal oxide layer, and the second interface is laterally offset from the first interface. The via extends through the non-metal oxide layer to the barrier structure.

Abstract: Implementations of semiconductor packages may include a first substrate coupled to a first die, a second substrate coupled to a second die, and a spacer included within a perimeter of the first substrate and within a perimeter of a second substrate, the spacer coupled between the first die and the second die, the spacer include a junction cooling pipe therethrough.

Abstract: A capacitor structure includes at least one first layer and at least one second layer that are alternately stacked. The at least one first layer includes first electrodes and second electrodes alternately arranged in a first direction, and the at least one second layer includes third electrodes and fourth electrodes alternately arranged in a second direction intersecting the first direction, the third electrodes and the fourth electrodes being electrically connected to the first electrodes and the second electrodes. Each of the first electrodes and the second electrodes includes a base portion and branch portions protruding from the base portion, and the third electrodes and the fourth electrodes are arranged side by side to correspond to the branch portions.

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a semiconductor substrate comprising an N well region having a semiconductor fin protruding therefrom. A trench isolation layer is on the semiconductor substrate around the semiconductor fin, wherein the semiconductor fin extends above the trench isolation layer. A gate dielectric layer is over the semiconductor fin. A conductive layer is over the gate dielectric layer over the semiconductor fin, the conductive layer comprising titanium, nitrogen and oxygen. A P-type metal gate layer is over the conductive layer over the semiconductor fin.

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to one embodiment includes an active region including a channel region and a source/drain region adjacent the channel region, a gate structure over the channel region of the active region, a source/drain contact over the source/drain region, a dielectric feature over the gate structure and including a lower portion adjacent the gate structure and an upper portion away from the gate structure, and an air gap disposed between the gate structure and the source/drain contact. A first width of the upper portion of the dielectric feature along a first direction is greater than a second width of the lower portion of the dielectric feature along the first direction. The air gap is disposed below the upper portion of the dielectric feature.

Abstract: A semiconductor structure including a first dielectric layer comprising a first conductive metal feature embedded in the first dielectric layer; and a second dielectric layer including a second conductive metal feature embedded in the second dielectric layer, the second conductive metal feature is above and directly contacts the first conductive metal feature, and an interface between the second conductive metal feature and the second dielectric layer includes a repeating scallop shape along its entire length.

Abstract: The present invention may provide an organic electroluminescent device which exhibits low driving voltage as well as high efficiency by including an electron transporting layer material having an improved electron transporting ability.

Abstract: The present disclosure provides a display panel and a manufacturing method thereof, and a display device. The display panel includes a base substrate, a light shielding layer and a pixel definition layer which are provided on the base substrate in turn; the light shielding layer includes an imaging pinhole; the display panel further includes a plurality of fingerprint recognition sensors arranged in an array, the fingerprint recognition sensors are provided on the base substrate; the light shielding layer is provided on a light incoming side of the fingerprint recognition sensors; a minimum distance between the imaging pinhole and the organic light emitting layer in the red sub-pixel is less than a minimum distance between the imaging pinhole and the organic light emitting layer in the green sub-pixel and is also less than a minimum distance between the imaging pinhole and the organic light emitting layer in the blue sub-pixel.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first insulating layer over a substrate. A first metal feature is formed in the first insulating layer and a second insulating layer is formed over the first insulating layer. A first metal via is formed through the second insulating layer to connect the first metal feature. A second metal feature is formed over the second insulating layer. The second metal feature has a convex top surface and a plane bottom surface, and the plane bottom is electrically connected to the first metal feature through the first metal via.

Abstract: A ferromagnetic layer is capped with a metallic oxide (or nitride) layer that provides a perpendicular-to-plane magnetic anisotropy to the layer. The surface of the ferromagnetic layer is treated with a plasma to prevent diffusion of oxygen (or nitrogen) into the layer interior. An exemplary metallic oxide layer is formed as a layer of metallic Mg that is plasma treated to reduce its grain size and enhance the diffusivity of oxygen into its interior. Then the plasma treated Mg layer is naturally oxidized and, optionally, is again plasma treated to reduce its thickness and remove the oxygen rich upper surface.

Abstract: A method for fabricating a shield gate MOSFET includes forming an epitaxial layer having a first conductivity type, forming a plurality of trenches in the epitaxial layer, forming a first and a second doped regions in the epitaxial layer at a bottom of each of the trenches, wherein the first doped region has a second conductivity type, and the second doped region has the first conductivity type. An insulating layer and a conductive layer as a shield gate are orderly formed in each of the trenches, and a portion of the conductive layer and the insulating layer are removed to expose a portion of the epitaxial layer in the trenches. An inter-gate oxide layer and a gate oxide layer are formed in the trenches, and a control gate is formed on the inter-gate oxide layer in the plurality of trenches.

Abstract: An integrated circuit device is provided. The integrated circuit device includes: a bit line on a substrate, the bit line including a lower conductive layer and an upper conductive layer; an insulating capping pattern on the bit line; and a main insulating spacer on a sidewall of the bit line and a sidewall of the insulating capping pattern, the main insulating spacer including an extended portion that is convex toward the upper conductive layer.

Abstract: A substrate processing liquid is used to etch a substrate in which at least either a bottom wall or a side wall forming a trench structure is an etched layer made of metal or a metal compound. The substrate processing liquid includes a chemical liquid containing H2O2 molecules or HO2? functioning as an etchant for etching the metal, and a complex forming agent containing NH4+ and forming a complex with ions of the metal and is adjusted to a pH of 5 or more.

Abstract: A semiconductor structure includes a power rail on a back side of the semiconductor structure, a first interconnect structure on a front side of the semiconductor structure, and a source feature, a drain feature, a first semiconductor fin, and a gate structure that are between the power rail and the first interconnect structure. The first semiconductor fin connects the source feature and the drain feature. The gate structure is disposed on a front surface and two side surfaces of the first semiconductor fin. The semiconductor structure further includes an isolation structure disposed between the power rail and the drain feature and between the power rail and the first semiconductor fin and a via penetrating through the isolation structure and connecting the source feature to the power rail.

Abstract: A device includes a fin extending from a semiconductor substrate; a gate stack over the fin; a first spacer on a sidewall of the gate stack; a source/drain region in the fin adjacent the first spacer; an inter-layer dielectric layer (ILD) extending over the gate stack, the first spacer, and the source/drain region, the ILD having a first portion and a second portion, wherein the second portion of the ILD is closer to the gate stack than the first portion of the ILD; a contact plug extending through the ILD and contacting the source/drain region; a second spacer on a sidewall of the contact plug; and an air gap between the first spacer and the second spacer, wherein the first portion of the ILD extends across the air gap and physically contacts the second spacer, wherein the first portion of the ILD seals the air gap.

Abstract: A chip-package-antenna integrated structure based on an SIW multi-feed network. A plurality of output terminals of the chip are connected to the SIW multi-feed network through the impedance matching network, to achieve the impedance matching between the chip and the SIW multi-feed network. The output terminal of the SIW multi-feed network is directly connected to the antenna terminals, and two or more input signals experience power combining in the substrate integrated waveguide are combined for power combining. Then the combined millimeter-wave signal is radiated by the antenna, finally realizing the power combining in the chip-package-antenna integrated structure. At the same time, the SIW multi-feed network is composed of a SIW structure, in which a plurality of via holes are arranged spaced apart to form a cavity structure.

Abstract: A method of manufacturing a semiconductor device includes providing a carrier, disposing a first pad on the carrier, forming a post on the first pad, and disposing a joint adjacent to the post and the first pad to form a first entire contact interface between the first pad and the joint and a second entire contact interface between the first pad and the post. The first entire contact interface and the second entire contact interface are flat surfaces.

Abstract: The present disclosure provides an organic compound of the following formula and an organic light emitting diode and an OLED device including the same.

Abstract: Disclosed herein are organic light emitting diode (OLED) devices and methods of use thereof. In one embodiment, an organic light emitting diode (OLED) device includes an emitting layer including: a host and an emitter, wherein the host exhibits triplet-triplet annihilation up-conversion, wherein the emitter has a band gap and exhibits triplet-triplet annihilation up-conversion, wherein the host and the emitter are different, and wherein the emitter has a concentration of 5% or more in the emitting layer.