Abstract: A semiconductor device includes a semiconductor fin. The semiconductor device includes a gate spacer over the semiconductor fin. A lower portion of the gate spacer surrounds a first region and an upper portion of the gate spacer surrounds a second region. The semiconductor device includes a gate dielectric within the first region. The semiconductor device includes a metal gate within the first region. The semiconductor device includes a dielectric protection layer, in contact with the gate dielectric layer, that includes a first portion within the second region and a second portion lining a top surface of the metal gate.

Abstract: A method includes forming an active channel region, forming a dummy channel region, forming a first gate dielectric layer over the active channel region, forming a second gate dielectric layer over the dummy channel region, removing the second gate dielectric layer from the dummy channel region, forming a gate isolation region over and contacting the dummy channel region, and forming a first gate stack and a second gate stack. The first gate stack is on the active channel region. The gate isolation region separates the first gate stack from the second gate stack.

Abstract: A method to form a transistor device with a recessed gate structure is provided. In one embodiment, a gate structure is formed overlying a device region and an isolation structure. The gate structure separates a device doping well along a first direction with a pair of recess regions disposed on opposite sides of the device region in a second direction perpendicular to the first direction. A pair of source/drain regions in is formed the device region on opposite sides of the gate structure. A sidewall spacer is formed extending along sidewalls of the gate structure, where a top surface of the sidewall spacer is substantially flush with the top surface of the gate structure. A resistive protection layer is then formed on the sidewall spacer and covering the pair of recess regions.

Abstract: A method includes receiving a semiconductor structure having a source contact feature electrically connected to a source feature and a drain contact feature electrically connected to a drain feature. The method includes etching to form a drain via trench over the drain contact feature and forming a drain via in the drain via trench. After forming the drain via, the method further includes etching to form a source via trench over the source contact feature and forming a source via in the source via trench. The drain via has a first dimension along a first direction, the source via has a second dimension along the first direction, and the second dimension is greater than the first dimension.

Abstract: A field-effect transistor structure includes a semiconductor substrate, a metal gate, a metal trench for source, a metal trench for drain, an etching-stop layer, and a gate contact. The etching-stop layer is overlaid on the metal trench for source and the metal trench for drain. The gate contact is above an active region.

Abstract: A package structure and a method of forming the same are provided. The package structure includes an integrated circuit die and a redistribution structure bonded to the integrated circuit die. The redistribution structure includes a first insulating layer, a second insulating layer interposed between the first insulating layer and the integrated circuit die, and a first metallization pattern in the first insulating layer and the second insulating layer. The first metallization pattern includes a first conductive line and a first conductive via coupled to the first conductive line. The first conductive line is in the second insulating layer. The first conductive via is in the first insulating layer. The first conductive line includes a first conductive pad coupled to the first conductive via, a second conductive pad, and a curved portion connecting the first conductive pad to the second conductive pad.

Abstract: A device includes a first channel layer over a semiconductor substrate, a second channel layer over the first channel layer, and a third channel layer over the second channel layer. The channel layers each connects a first and a second source/drain along a first direction. The device also includes a first gate portion between the first and second channel layers; a second gate portion between the second and third channel layers; a first inner spacer between the first and second channel layers and between the first gate portion and the first source/drain; and a second inner spacer between the second and third channel layers and between the second gate portion and the first source/drain. The first and second gate portions have substantially the same gate lengths along the first direction. The first inner spacer has a width along the first direction that is greater than the second inner spacer has.

Abstract: A semiconductor package includes a semiconductor chip including a chip pad; a lower redistribution structure on the semiconductor chip, the lower redistribution structure including a lower redistribution insulating layer and a lower redistribution pattern electrically connected to the chip pad of the semiconductor chip; a molding layer on at least a portion of the semiconductor chip; and a conductive post in the molding layer, the conductive post having a bottom surface and a top surface, the bottom surface of the conductive post being in contact with the lower redistribution pattern of the lower redistribution structure and the top surface of the conductive post having a concave shape.

Abstract: The present disclosure relates to a semiconductor device including a substrate and a pair of spacers on the substrate. Each spacer of the pair of spacers includes an upper portion having a first width and a lower portion under the upper portion and having a second width different from the first width. The semiconductor device further includes a gate structure between the pair of spacers. The gate structure has an upper gate length and a lower gate length that is different from the upper gate length.

Abstract: Semiconductor structures and fabrication methods are provided. The semiconductor includes a substrate; a plurality of discrete fins on the substrate; a gate structure on the substrate, and across the plurality of discrete fins by covering portions of sidewall surfaces and top surfaces of the plurality of discrete fins; a plurality of doped source/drain layers in the plurality of discrete fins and at both sides of the gate structure; a conductive layer, formed at one or two sides of the gate structure, connecting multiple doped source/drain layers of the plurality of doped source/drain layers, and with a top surface lower than a top surface of the gate structure; and a conductive plug on the conductive layer and in contact with a portion of a surface of the conductive layer.

Abstract: An image sensor that includes a sensor substrate provided with a sensor surface on which a photodiode is arranged in a planar manner, a sealing resin applied to a side of the sensor surface of the sensor substrate, sealing glass bonded to the sensor substrate via the sealing resin, and a reinforcing resin made of a resin material having higher rigidity than the sealing resin and formed on an outer periphery of the sealing resin to bond the sensor substrate and the sealing glass. The sealing resin is formed to have a smaller area than each of the sensor substrate and the sealing glass, so that the reinforcing resin is formed to fill a gap provided on the outer periphery of the sealing resin, the sensor substrate and the sealing glass facing each other through the gap.

Abstract: A semiconductor device and methods of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure with a fin top surface disposed on the substrate, a source/drain (S/D) region disposed on the fin structure, a gate structure disposed on the fin top surface, and a gate spacer with first and second spacer portions disposed between the gate structure and the S/D region. The first spacer portion extends above the fin top surface and is disposed along a sidewall of the gate structure. The second spacer portion extends below the fin top surface and is disposed along a sidewall of the S/D region.

Abstract: A method includes forming a dummy gate stack over a semiconductor region, removing the dummy gate stack to form a trench between gate spacers, forming a replacement gate dielectric extending into the trench, and forming a replacement gate electrode on the replacement gate dielectric. The forming the replacement gate electrode includes depositing a metal-containing layer. The depositing the metal-containing layer includes depositing a lower layer having a first average grain size, and depositing an upper layer over the lower layer. The lower layer and the upper layer are formed of a same material, and the upper layer has a second average grain size greater than the first average grain size. Source and drain regions are formed on opposing sides of the replacement gate electrode.

Abstract: An organic light emitting device including, in sequence, an anode, a light emitting layer, a first electron transport layer, a second electron transport layer, and a cathode, wherein the second electron transport layer includes a first material and a second material different from the first material, and the first electron transport layer includes a third material and a fourth material different from the third material.

Abstract: A semiconductor package includes a first semiconductor chip; an encapsulant covering at least a portion of the first semiconductor chip; insulating layers provided on the encapsulant, each of the insulating layers being transparent or translucent; and wiring layers provided on the encapsulant, the wiring layers being partially covered by the insulating layers, wherein an outermost insulating layer of the insulating layers comprises a first region and a second region, a color of the first region is different from a color of the second region, the second region surrounds the first region, and at least one marking pattern comprising at least one step portion is provided in the first region of the outermost insulating layer.

Abstract: A semiconductor includes a gate stack over a substrate. The semiconductor device further includes an interlayer dielectric (ILD) at least partially enclosing the gate stack. The ILD includes a portion doped with a large species material, wherein the portion includes a first sidewall substantially perpendicular to a top-most surface of the ILD, and the portion includes a second sidewall having a positive angle with respect to the first sidewall.

Abstract: A fuse structure and a method for manufacturing the same are provided. The fuse structure includes a substrate; a fin, located on the substrate and including a first fin region; and a gate stack structure, surrounding the top and side walls of the first fin region. The gate stack structure includes a first gate stack and a second gate stack. The first gate stack covers the first fin region, the second gate stack covers the first gate stack. The first gate stack is configured to receive a first gate voltage, the second gate stack is configured to receive a second gate voltage, and the first gate voltage is greater than the second gate voltage. The fuse structure reduces the area of the fuse unit and increase the integration level of the fuse circuit.

Abstract: A semiconductor package may include: a first redistribution substrate; a first die above the first redistribution substrate; a second redistribution substrate on the first die; a first bump formed on the first die, and connecting the first die to the second redistribution substrate; a first molding portion enclosing the first die and surrounding the first bump; and an outer terminal on a bottom surface of the first redistribution substrate, wherein the second redistribution substrate comprises an insulating pattern and a conductive pattern in the insulating pattern to be in contact with the first bump, and wherein, at an interface of the second redistribution substrate and the first bump, the conductive pattern of the second redistribution substrate and the first bump are formed of the same material to form a single body or structure.

Abstract: A method includes forming a semiconductor fin over a substrate; forming a gate structure over the semiconductor fin; forming a helmet layer lining the gate structure and the semiconductor fin; etching the helmet layer to remove portions of the helmet layer from opposite sidewalls of the gate structure, wherein the remaining helmet layer comprises a first remaining portion on a top surface of the gate structure and a second remaining portion on a top surface of the semiconductor fin; forming a spacer layer covering the gate structure, wherein the spacer layer is in contact with the first remaining portion and the second remaining portion of the remaining helmet layer; etching the spacer layer and the remaining helmet layer to form gate spacers, wherein each of the gate spacers has a stepped sidewall; and forming source/drain epitaxy structures on opposite sides of the gate structure.

Abstract: The present application discloses a vertical UMOSFET device with a high channel mobility and a preparation method thereof. The vertical UMOSFET device with a high channel mobility includes an epitaxial structure, and a source, a drain and a gate which match the epitaxial structure, where the epitaxial structure includes a first semiconductor, and a second semiconductor and a third semiconductor which are sequentially disposed on the first semiconductor, a groove structure matching the gate is also disposed in the epitaxial structure, and the groove structure continuously extends into the first semiconductor from a first surface of the epitaxial structure; a fourth semiconductor is also disposed at least between an inner wall of the groove structure and the second semiconductor, and the fourth semiconductor is a high resistivity semiconductor.