Abstract: A semiconductor device includes: a substrate having a groove formed on a main surface; a drift region of a first conductivity type, the drift region having a portion disposed at a bottom part; a well region of a second conductivity type, the well region being disposed in one sidewall to be connected to the drift region; a first semiconductor region of the first conductivity type, the first semiconductor region being disposed on a surface of the well region in the sidewall to be away from the drift region; a second semiconductor region of the first conductivity type, the second semiconductor region being disposed to be opposed to the well region via the drift region; and a gate electrode opposed to the well region, the gate electrode being disposed in a gate trench that has an opening extending over the upper surfaces of the well region and the first semiconductor region.

Abstract: An integrated circuit structure includes a lower interconnect structure, a first semiconductor fin, a lower gate structure, first source/drain structures, an upper gate structure, and an upper interconnect structure. The first semiconductor fin is above the lower interconnect structure. The lower gate structure is under the first semiconductor fin and extends across the first semiconductor fin. The first source/drain structures are in the first semiconductor fin and on opposite sides of the lower gate structure. The first source/drain structures forms a lower transistor with the lower gate structure. The upper gate structure is above the first semiconductor fin and extends across the first semiconductor fin. The upper gate structure forms an upper transistor with the first source/drain structures. The upper interconnect structure is above the upper gate.

Abstract: A semiconductor package includes a first die, a second die, an encapsulant, a first inductor and a second inductor. The second die is stacked on the first die along a first direction. The encapsulant encapsulates the second die over the first die. The first inductor is disposed in the encapsulant and has a first spiral structure, wherein the first spiral structure has a plurality of first coils around a first axis, and the first axis is substantially perpendicular to the first direction. The second inductor is disposed in the encapsulant and having a second spiral structure, wherein the first inductor and the second inductor are disposed at opposite sides of the second die.

Abstract: Field effect transistor and manufacturing method thereof are disclosed. The field effect transistor includes a substrate, fins, a gate structure, a first spacer and a second spacer. The fins protrude from the substrate and extend in a first direction. The gate structure is disposed across and over the fins and extends in a second direction perpendicular to the first direction. The first spacer is disposed on sidewalls of the gate structure. The second spacer is disposed on the first spacer and surrounds the gate structure. The first spacer is fluorine-doped and includes fluorine dopants.

Abstract: Self-aligned gate endcap (SAGE) architectures with gate-all-around devices above insulator substrates, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices above insulator substrates, are described. In an example, an integrated circuit structure includes a semiconductor nanowire above an insulator substrate and having a length in a first direction. A gate structure is around the semiconductor nanowire, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included. The first of the pair of gate endcap isolation structures is directly adjacent to the first end of the gate structure, and the second of the pair of gate endcap isolation structures is directly adjacent to the second end of the gate structure.

Abstract: An inductor includes a core and a conductive spiral wound around the core. The core includes a buffer layer, an etch stop layer, and a core material layer sequentially stacked. The core material layer includes a ferromagnetic material. A total area of a vertical projection of the core material layer is smaller than an area occupied by the etch stop layer. The vertical projection of the core material layer falls entirely on the etch stop layer. The etch stop layer horizontally protrudes with respect to the core material layer.

Abstract: Generally, examples are provided relating to conductive features that include a barrier layer, and to methods thereof. In an embodiment, a metal layer is deposited in an opening through a dielectric layer(s) to a source/drain region. The metal layer is along the source/drain region and along a sidewall of the dielectric layer(s) that at least partially defines the opening. The metal layer is nitrided, which includes performing a multiple plasma process that includes at least one directional-dependent plasma process. A portion of the metal layer remains un-nitrided by the multiple plasma process. A silicide region is formed, which includes reacting the un-nitrided portion of the metal layer with a portion of the source/drain region. A conductive material is disposed in the opening on the nitrided portions of the metal layer.

Abstract: Apparatuses, methods, and systems related to electrode formation are described. A first portion of a top electrode is formed over a dielectric material of a storage node. A metal oxide is formed over the first portion of the electrode. A second portion of the electrode is formed over the metal oxide.

Abstract: A test site includes: at least one test module that tests a device under test; and a waveform data acquisition module that converts an electrical signal relating to the DUT into a digital signal with a predetermined sampling rate so as to acquire waveform data in the form of a digital signal sequence. The higher-level controller controls the at least one test module and the waveform data acquisition module, and collects the waveform data acquired by the waveform data acquisition module in a form associated with the operation state of the at least one test module.

Abstract: The present disclosure provides a semiconductor structure comprising one or more fins formed on a substrate and extending along a first direction; one or more gates formed on the one or more fins and extending along a second direction substantially perpendicular to the first direction, the one or more gates including an first isolation gate and at least one functional gate; source/drain features formed on two sides of each of the one or more gates; an interlayer dielectric (ILD) layer formed on the source/drain features and forming a coplanar top surface with the first isolation gate. A first height of the first isolation gate is greater than a second height of each of the at least one functional gate.

Abstract: A first pixel circuit has a plurality of photodiodes of different sizes. A second pixel circuit is connected to the first pixel circuit, and has a holding portion that holds a first optical signal and a second optical signal. The peripheral circuit drives and controls the second pixel circuit, and determines whether a voltage value of the first optical signal is equal to or greater than a predetermined value. When it is determined that the voltage value of the first optical signal is equal to or greater than the predetermined value, a signal obtained by adding the second optical signal to the first optical signal is set as an output signal. When it is determined that the voltage value of the first optical signal is less than the predetermined value, the first optical signal is set as an output signal.

Abstract: A semiconductor device includes a gate pattern crossing over a substrate, the gate pattern including a gate insulating layer, a gate electrode, and a gate capping pattern sequentially stacked on the substrate, a gate spacer covering a sidewall of the gate pattern, a source/drain pattern on the substrate, the source/drain pattern being adjacent to the sidewall of the gate pattern, a contact pad on the source/drain pattern, a top surface of the contact pad being lower than a top surface of the gate electrode, a source/drain contact plug on the contact pad, and a protection spacer between the gate spacer and the source/drain contact plug, the protection spacer having a ring shape enclosing the source/drain contact plug.

Abstract: Signal isolation for module with ball grid array. In some embodiments, a packaged module can include a packaging substrate having an underside, and an arrangement of conductive features implemented on the underside of the packaging substrate to allow the packaged module to be capable of being mounted on a circuit board. The arrangement of conductive features can include a signal feature implemented at a first region and configured for passing of a signal, and one or more shielding features placed at a selected location relative to the signal feature to provide an enhanced isolation between the signal feature and a second region of the underside of the packaging substrate.

Abstract: A method of manufacturing a semiconductor device includes forming an active region on a substrate, forming a gate structure on the substrate intersecting the active region, removing an upper portion of the gate structure and forming a gate capping layer, forming a preliminary contact plug electrically connected to a portion of the active region, the preliminary contact plug including first and second portions, forming a mask pattern layer including a first pattern layer covering an upper surface of the gate capping layer, and a second pattern layer extending from the first pattern layer to cover the second portion of the preliminary contact plug, and forming a contact plug using the mask pattern layer as an etch mask by recessing the first portion of the preliminary contact plug exposed by the mask pattern layer to a predetermined depth from an upper surface of the preliminary contact plug.

Abstract: The present disclosure provides a method for preparing a semiconductor device structure. The method includes preparing a substrate having a pattern-dense region and a pattern-loose region; forming a first conductive layer disposed over the substrate; forming a first dielectric layer disposed over the first conductive layer; etching the first dielectric layer to form a first opening and a second opening exposing the first conductive layer; forming a first lining layer and a first conductive plug in the first opening and a second conductive plug in the second opening, wherein the first lining layer comprises manganese (Mn), the first conductive plug comprises copper (Cu), and the first conductive plug and the second plug are surrounded by the first lining layer; and forming a second conductive layer over the first dielectric layer, the first lining layer and the first conductive layer, wherein the second conductive layer comprises copper (Cu).

Abstract: A semiconductor package includes; a wiring structure including signal wiring and heat transfer wiring, an active chip on the wiring structure, a signal terminal disposed between the wiring structure and the active chip, a first heat transferring terminal disposed between the wiring structure and the active chip and connected to the heat transfer wiring, a passive chip on the wiring structure, a second heat transferring terminal disposed between the wiring structure and the passive chip and connected to the heat transfer wiring, and a heat spreader on the passive chip.

Abstract: A wiring structure includes first to third metal patterns on a substrate. The first metal pattern extends in a second direction and has a first width in a third direction. The second metal pattern extends in the third direction to cross the first metal pattern and have a second width in the second direction. The third metal pattern is connected to the first and second metal patterns at an area where the first and second metal patterns cross each other, and has a substantially rectangular shape with concave portions in each quadrant. The third metal pattern has a third width defined as a minimum distance between opposite ones of the concave portions in a fourth direction having an acute angle to the second and third directions, which is less or equal to than a smaller of the first and second widths.

Abstract: A semiconductor chip according to an embodiment includes a body portion with a front surface and a rear surface, the body portion being oriented in such a way that the rear surface is above the front surface, first and second through electrodes penetrating the body portion with protrusions that protrude above the rear surface of the body portion, a wiring portion formed under the front surface of the body portion, a power pattern formed over the rear surface of the body portion and spaced apart from the protrusions, an interlayer insulating layer filling spaces between the power pattern and the protrusions, and first and second rear connection electrodes formed over the interlayer insulating layer and respectively connected to the first and second through electrodes, wherein the first rear connection electrode is simultaneously connected to the first through electrode and a part of the power pattern that is adjacent to the first through electrode.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes channel members vertically stacked over a substrate, a gate structure engaging the channel members, a gate spacer layer disposed on sidewalls of the gate structure, an epitaxial feature abutting the channel members, an inner spacer layer interposing the gate structure and the epitaxial feature, and a semiconductor layer interposing the inner spacer layer and the epitaxial feature.

Abstract: A method for forming a semiconductor structure and a semiconductor structure. The method includes: a semiconductor base which has a substrate and a first oxide material layer arranged on the substrate is provided. Pattern etching is performed on the first oxide material layer, to remove the first oxide material layer in the second region and that in a part of the first region, and the remaining first oxide material layer forms oxide line structures on both sides of each bit line structure; a second material is backfilled, to form an isolation line structure in the first region and a dummy isolation structure in the second region; remove the oxide line structures are removed, the bit line structures and the isolation line structures on both sides jointly form through hole structures exposing the substrate; and a conductive material layer is formed in the through hole structures to form the semiconductor structure.