Patents Examined by Yu Chen
  • Patent number: 10319119
    Abstract: Methods and apparatus for automatically visualizing 3D medical image data to provide accelerated reading of the 3D medical image data are disclosed. A 3D medical volume is received. A synopsis volume or a tapestry image is generated from the 3D medical volume. A synopsis volume is a spatially compact volume that is created from the 3D medical image volume and contains target anatomical structures related to a particular clinical task. A tapestry image is a single 2D image that visualizes a combination of multiple 2D views of one or more target anatomical objects related to a particular clinical task.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: June 11, 2019
    Assignee: Siemens Healthcare GmbH
    Inventor: Shaohua Kevin Zhou
  • Patent number: 10317595
    Abstract: An organic light emitting device includes a display panel including a plurality of pixels and a circular polarizing plate disposed opposite to the display panel, where the circular polarizing plate has a plurality of retardations corresponding to the pixels of the display panel. A method of manufacturing an organic light emitting device includes preparing a display panel including a plurality of pixels, preparing a circular polarizing plate having a plurality of retardations, and assembling the display panel and the circular polarizing plate, where the display panel and the circular polarizing plate are assembled so that the retardations of the circular polarizing plate respectively correspond to the pixels of the display panel.
    Type: Grant
    Filed: July 1, 2015
    Date of Patent: June 11, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tsuyoshi Ohyama, Eun Sung Lee, Nobuo Hamamoto
  • Patent number: 10304859
    Abstract: The stability of a step of processing a wiring formed using copper, aluminum, gold, silver, molybdenum, or the like is increased. Moreover, the concentration of impurities in a semiconductor film is reduced. Moreover, the electrical characteristics of a semiconductor device are improved. In a transistor including an oxide semiconductor film, an oxide film in contact with the oxide semiconductor film, and a pair of conductive films being in contact with the oxide film and including copper, aluminum, gold, silver, molybdenum, or the like, the oxide film has a plurality of crystal parts and has c-axis alignment in the crystal parts, and the c-axes are aligned in a direction parallel to a normal vector of a top surface of the oxide semiconductor film or the oxide film.
    Type: Grant
    Filed: April 8, 2014
    Date of Patent: May 28, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichi Koezuka, Yasutaka Nakazawa, Yukinori Shima, Masami Jintyou, Masayuki Sakakura, Motoki Nakashima
  • Patent number: 10303945
    Abstract: A display method is for a display apparatus to display an image, and includes: obtaining a captured display image and a decode target image by an image sensor capturing an image of a subject; obtaining a light ID by decoding the decode target image; transmitting the light ID to a server; obtaining, from the server, an AR image and recognition information which are associated with the light ID; recognizing a region according to the recognition information as a target region from the captured display image; and displaying the captured display image in which the AR image is superimposed on the target region.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: May 28, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Hideki Aoyama, Mitsuaki Oshima, Koji Nakanishi, Toshiyuki Maeda, Akihiro Ueki, Kengo Miyoshi, Tsutomu Mukai
  • Patent number: 10304159
    Abstract: A computer displays a plurality of edge lines extracted from a shot image of a spatial structure that has been shot by an image shooting apparatus, and a plurality of ridge lines included in a model image represented by model information of the spatial structure, in a manner such that the edge lines and the ridge lines are selectable. Then, the computer accepts a selection instruction indicating an edge line and a ridge line of an overlay target. Finally, in accordance with the accepted selection instruction, the computer displays a superimposition image in which the model image has been superimposed onto the shot image in a manner such that the edge line and the ridge line of the overlay target overlap each other.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: May 28, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Tomohiro Aoyagi, Yojiro Numata
  • Patent number: 10297594
    Abstract: A high density trench-gated MOSFET array and method are disclosed. It comprises semiconductor substrate partitioned into MOSFET array area and gate pickup area; epitaxial region, body region and source region; numerous precisely spaced active nitride-capped trench gate stacks (ANCTGS) embedded till the epitaxial region. Each ANCTGS comprises a stack of polysilicon trench gate with gate oxide shell and silicon nitride cap covering top of polysilicon trench gate and laterally registered to gate oxide shell. The ANCTGS forms, together with the source, body, epitaxial region, a MOSFET device in the MOSFET array area. Over MOSFET array area and gate pickup area, a patterned dielectric region atop the MOSFET array and a patterned metal layer atop the patterned dielectric region. Thus, the patterned metal layer forms, with the MOSFET array and the gate pickup area, self-aligned source and body contacts through the inter-ANCTGS separations.
    Type: Grant
    Filed: August 6, 2015
    Date of Patent: May 21, 2019
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Yeeheng Lee, Jongoh Kim, Hong Chang
  • Patent number: 10297610
    Abstract: An array of memory stack structures extends through an alternating stack of insulating layers and electrically conductive layers over a substrate. An array of drain select level assemblies including cylindrical electrode portions is formed over the alternating stack with the same periodicity as the array of memory stack structures. A drain select level isolation strip including dielectric materials can be formed between a neighboring pair of drain select level assemblies employing the drain select level assemblies as a self-aligning template. Alternatively, cylindrical electrode portions can be formed around an upper portion of each memory stack structure. Strip electrode portions are formed on the cylindrical electrode portions after formation of the drain select level isolation strip.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: May 21, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: James Kai, Johann Alsmeier, Shinsuke Yada, Akihisa Sai, Sayako Nagamine, Takashi Orimoto, Tong Zhang
  • Patent number: 10297663
    Abstract: A method of forming a semiconductor structure includes forming outer spacers surrounding a dummy gate, the dummy gate being disposed over a channel stack comprising two or more nanosheet channels and sacrificial layers formed above and below each of the two or more nanosheet channels. The method also includes forming an oxide surrounding the outer spacers, the oxide being disposed over source/drain regions surrounding the channel stack. The method further includes removing the dummy gate, removing the outer spacers, and performing a channel release to remove the sacrificial layers in the channel stack following removal of the outer spacers. The method further includes performing conformal deposition of a dielectric layer and a work function metal on exposed portions of the oxide, and filling a gate metal over the channel stack, the gate metal being surrounded by the work function metal.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: May 21, 2019
    Assignee: International Business Machines Corporation
    Inventors: Chun W. Yeung, Chen Zhang
  • Patent number: 10290698
    Abstract: An illustrative method includes, among other things, forming a plurality of fins. A subset of the plurality of fins is selectively removed, leaving at least a first fin to define a first fin portion and at least a second fin to define a second fin portion. A first type of dopant is implanted into a substrate to define a resistor body and the first type of dopant is implanted into the first and second fins. The first fin portion is disposed above a first end of the resistor body and the second fin is disposed above a second end of the resistor body. An insulating layer is formed above the resistor body. At least one gate structure is formed above the insulating layer and above the resistor body.
    Type: Grant
    Filed: February 20, 2017
    Date of Patent: May 14, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Jagar Singh
  • Patent number: 10290792
    Abstract: A thermoelectric element is formed with a thread portion on at least one end in an electromotive force generating direction.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: May 14, 2019
    Assignee: AISIN TAKAOKA CO., LTD.
    Inventor: Hitoshi Yoshimi
  • Patent number: 10290289
    Abstract: Methods and apparatus relating to an adaptive multibit bus for energy optimization are described. In an embodiment, a 1-bit interconnect of a processor is caused to select between a plurality of operational modes. The plurality of operational modes comprises a first mode and a second mode. The first mode causes transmission of a single bit over the 1-bit interconnect at a first frequency and the second mode causes transmission of a plurality of bits over the 1-bit interconnect at a second frequency based at least in part on a determination that an operating voltage of the 1-bit interconnect is at a high voltage level and that the second frequency is lower than the first frequency. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: April 1, 2017
    Date of Patent: May 14, 2019
    Assignee: Intel Corporation
    Inventors: Sanjeev S. Jahagirdar, Tapan A. Ganpule, Anupama A. Thaploo, Abishek R. Appu, Joydeep Ray, Altug Koker
  • Patent number: 10290120
    Abstract: The present disclosure relates to mobile electronic devices including at least one transparent display screen for comparing and accurately determining the color of a predetermined object for color and texture application. In addition, the present disclosure provides color analysis and control using an electronic mobile device transparent display screen, for a wide variety of applications, including, but not limited to color, shade and coating defect identification applications, including augmented reality applications. Color data for a perceived color stores in a memory and displays images as perceived through the transparent display screen. Image difference values are determined between a first set of optical processing data and a second set of optical processing data. The transparent display screen indicates image difference values from including differences in color, texture, transparency, lighting, etc., especially for augmented reality applications.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: May 14, 2019
    Inventor: Suk K. Kim-Whitty
  • Patent number: 10283073
    Abstract: A video processing system comprises a video processor and an output buffer. When a new frame is to be written to the output buffer, the video processing system determines (12) for at least a portion of the new frame whether the portion of the new frame has a particular property. When it is determined that that the portion of the new frame has the particular property (14), when a block of data representing a particular region of the portion of the new frame is to be written to the output buffer, it is compared to at least one block of data already stored in the output buffer, and a determination is made whether or not to write the block of data to the output buffer on the basis of the comparison. When it is determined that the portion of the new frame does not have the particular property (16), the portion of the new frame is written to the output buffer.
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: May 7, 2019
    Assignee: Arm Limited
    Inventors: Tomas Edsö, Ola Hugosson, Dominic Symes
  • Patent number: 10283667
    Abstract: The present disclosure relates to an electromagnetic energy detector. The detector can include a substrate having a first refractive index; a metal layer; an absorber layer having a second refractive index and disposed between the substrate and the metal layer; a coupling structure to convert incident radiation to a surface plasma wave; additional conducting layers to provide for electrical contact to the electromagnetic energy detector, each conducting layer characterized by a conductivity and a refractive index; and a surface plasma wave (“SPW”) mode-confining layer having a third refractive index that is higher than the second refractive index disposed between the substrate and the metal layer.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: May 7, 2019
    Assignee: STC.UNM
    Inventors: Steven R. J. Brueck, Sanjay Krishna, Seung-Chang Lee
  • Patent number: 10282896
    Abstract: A method for zone analysis. A zone is identified in a three-dimensional physical model of a vehicle. The three-dimensional physical model includes geometry information and location information for physical components. An effect of an undesired operation of a group of components in a zone within the three-dimensional physical model of the vehicle is identified based on the three-dimensional physical model of the vehicle and a logical model of the vehicle including a logical architecture linking logical components to each other. Logical components in the logical model are mapped to the physical components in the three-dimensional physical model of the vehicle.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: May 7, 2019
    Assignee: The Boeing Company
    Inventors: Tyler Junichi Petri, Daniel J. Fogarty, David H. Jones, Roger Keith Nicholson, Lars Fucke, Kimberly Motonaga, Kevin Nicholas King, Chad Richard Douglas
  • Patent number: 10282318
    Abstract: An image processing apparatus includes a plurality of memories and a hardware processor which controls an execution operation of a first function including an image processing function and an execution operation of a second function including a server function, by using the plurality of memories. The hardware processor estimates a required bandwidth which is a memory bandwidth required for the execution operation of the first function on the basis of a current operation mode of the image processing apparatus among a plurality of operation modes of the image processing apparatus, and determines a bandwidth securing channel for first function which is a channel capable of being used for the execution operation of the first function and incapable of being used for the execution operation of the second function, out of a plurality of channels used to access the plurality of memories, on the basis of the required bandwidth.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: May 7, 2019
    Assignee: Konica Minolta, Inc.
    Inventors: Kenichi Takahashi, Kaitaku Ozawa, Masao Hosono, Tomoaki Nakajima, Toshikazu Kawaguchi, Daisuke Nakano
  • Patent number: 10276606
    Abstract: A method for making an array substrate includes the following steps: forming a poly-silicon semiconductor layer on a substrate; forming a buffer layer on the substrate; depositing a first metal layer, and patterning the first metal layer to form gate electrodes for a driving TFT, a switch TFT, and a poly-silicon TFT; forming a first gate insulator layer; forming a second gate insulator layer; defining through holes passing through the buffer layer, the first gate insulator layer, and the second gate insulator layer to expose the poly-silicon semiconductor layer; depositing a metal oxide layer to form a first metal oxide semiconductor layer; and depositing a second metal layer to form source electrodes and drain electrodes for the driving TFT, the switch TFT, and the poly-silicon TFT.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: April 30, 2019
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Hsin-Hua Lin, Yi-Chun Kao
  • Patent number: 10271774
    Abstract: An activity tracking system includes a sensor device and a display device. The sensor device is configured to be carried by the user and includes at least one sensor configured to obtain the activity data for the user. The display device includes a display screen. The display device is configured to receive the activity data obtained by the sensor device and display the activity data about a circular axis on the display screen. The circular axis is provided as a solitary closed loop circular axis with respect to a defined center point. The activity data includes first data on one side of the circular axis and mutually exclusive second data on an opposite side of the circular axis. The first data includes a first start time and a first end time, the first end time occurring in a selected day and the first start time occurring in a previous day.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: April 30, 2019
    Assignee: Under Armour, Inc.
    Inventors: Kyler Maxwell Eastman, Clifford C. Drane, Jr., William Wiley Fikes
  • Patent number: 10276586
    Abstract: According to one embodiment, a semiconductor device includes a substrate and a semiconductor layer. The device further includes a first electrode layer that is provided on a side surface of the semiconductor layer with a first insulating film interposed therebetween. The device further includes a charge storage layer provided on a side surface of the first electrode layer with the second insulating film interposed therebetween.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: April 30, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Atsushi Murakoshi, Yasuhito Yoshimizu, Tomofumi Inoue, Tatsuya Kato, Yuta Watanabe, Fumitaka Arai
  • Patent number: 10277704
    Abstract: The described technology is directed towards having user interface objects rendered on a client device based upon provider data of at least part of a client provider graph. The client provider graph comprises a plurality of providers (graph nodes), in which each provider has provider data corresponding to user interface object data. The data of one provider has a reference set containing one or more references (e.g., edges) that each identify another provider, thus forming the graph. Client requests for other provider data are made based upon the reference set. The other provider data is received in response to the client requests, and is maintained at the client (e.g., in a client cache) to build the client graph.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: April 30, 2019
    Assignee: Home Box Office, Inc.
    Inventors: Sata Busayarat, Gregory John Bellingham, Brandon C. Furtwangler, Allen Arthur Gay