Abstract: A metal oxide layer may made more highly oxidized by exposing the layer to sulfur trioxide. The leakage current of the layer may thereby be decreased, providing a capacitor containing such a layer with improved performance properties. The capacitor may be incorporated into a dynamic random access memory cell or other structure useful in the semiconductor or other industry.

Abstract: A method for fabricating a capacitor for an integrated circuit, comprising the steps of forming a titanium film for an adhesion layer over a substrate, forming a titanium dioxide film for a diffusion barrier layer by annealing the titanium film after ion-implantation of oxygen ion into a surface region of the titanium film so as to change titanium in the surface region to titanium dioxide, and forming a high dielectric constant capacitor on the titanium dioxide film.

Abstract: A method for bringing up lower level metal nodes of multi-layered IC devices (200) includes a step of boring a passage (210) down through the obstructing or non-target metal layers (220) exposing these layers, through the Inter Layer Dielectric layers (230), stopping at the target metal layer (240), and a step of depositing Gallium implanted insulator (250, 260) forming a node structure (280) with a conductive core (250) and an insulative sheath (260). The conductive core (250) brings up the target metal node or layer (240) and the insulative sheath (260) isolates the exposed non-target metal nodes or layers (220) from the target metal node (240) and the conductive core (250).

Abstract: In a method for forming an interlayer dielectric (ILD) coating on microcircuit interconnect lines of a substrate, the substrate and interconnect lines are annealed prior to deposition of an ILD. A post annealing SiON layer is formed by using plasma-enhanced chemical vapor deposition. The deposition using a plasma formed of nitrogen, nitrous oxide, and silane gases, with the gases being dispensed at regulated flow rates and being energized by a radio frequency power source. The plasma reacts to form SiON which is deposited on a semiconductor substrate. Additionally, during deposition, minor adjustments are made to deposition temperature and process pressure to control the optical characteristics of the SiON layer. The SiON layer is tested for acceptable optical properties and acceptable SiON layers are coated with a SiO2 layer to complete formation of the ILD. Once the ILD is formed the substrate is in readiness for further processing.

Abstract: A method of manufacturing a semiconductor device. First, a plurality of wires are arranged in parallel to one another, on a semiconductor substrate. Then, insulating films of a first group are formed on tops of the wires, respectively. Next, second insulating films of a second group are formed on sides of the wires, respectively. Further, among the wires there are formed insulating films of a third group which have upper surfaces located at a level not higher than upper surfaces of the insulating films of the second group. Thereafter, contact holes are formed by subjecting the insulating films of the third group to selectively etching. Finally, the contact holes are filled with electrically conductive material.

Abstract: The formation and/or growth of dendrites emanating from Cu or Cu alloy lines into a bordering open dielectric field are prevented or substantially reduced by chemically removing a portion of the surface from the dielectric field and from between the lines after CMP with a solution comprising acetic acid and ammonium fluoride. Embodiments include removing up to 60 .ANG., e.g. about 10 .ANG. to about 30 .ANG., of silicon oxide by immersing the wafer in a solution containing at least about 90 wt. % acetic acid and up to about 10 wt. % ammonium fluoride.

Abstract: The thickness of a capacitor dielectric layer is reduced by a manufacturing method. A first polysilicon layer is deposited on a substrate that has an isolation structure. Subsequently, nitrogen ions are implanted into the first polysilicon layer. The thickness of an oxide layer formed on the first polysilicon layer is determined by dosage of the implanted nitrogen ions. Next, the first polysilicon layer is patterned, so as to form a bottom electrode of the capacitor and expose a portion of the substrate. A thermal oxidation process is then performed to form an oxide layer, which is used as a gate oxide layer on the substrate and is also used as a dielectric layer in capacitor on the bottom electrode. Subsequently, a second polysilicon layer is deposited and patterned as an upper electrode of the capacitor on the capacitor dielectric layer.

Abstract: In one aspect, the invention includes a method of densifying a silicon nitride layer comprising: after forming the silicon nitride layer, exposing the silicon nitride layer to atomic nitrogen, the exposing not increasing a thickness of the silicon nitride layer by more than about 10 Angstroms. In another aspect, the invention includes a method of densifying a silicon nitride layer comprising: after forming the silicon nitride layer, exposing the silicon nitride layer to atomic nitrogen in the substantial absence of a silicon-containing gas.

Abstract: The invention relates to a method for manufacturing of a titanium self-aligned silicide (Salicide). This process includes of forming a metal layer over the surfaces of the semiconductor substrate and the gate electrode. Then, a rapid thermal process is performed with three stages to form the salicide, for example, titanium silicide, at the interface between the titanium and silicon, namely on the surfaces of the gate electrode and source/drain region. The rapid thermal process with three stages includes using the first stage with the first temperature to form the early titanium silicide having the C49 phase. The temperature is raised to a second temperature and the RTA process is performed with nitrogen gases to transform the high resistance phase C49 of the titanium nitride into a low resistance phase C54 in the second stage. Then, the temperature is rapidly raised to a third temperature to transform the C49 phase into the C54 phase completely and to prevent the agglomeration phenomenon.

Abstract: A structure and method for connecting two levels of interconnect vertically spaced from each other by another level of interconnect by forming a first interconnect region to which contact is to be made, a first insulating layer over the interconnect region, and an etch-stop layer over the first insulating layer, and etching the etch stop layer to form an opening at a position over the first interconnect region. A second interconnect region is formed in contact with the first insulating layer and above the first interconnect region, a second insulating layer is formed over the first insulation layer and the etch stop layer, and an opening is formed in the second insulating layer overlapping the opening in the etch stop layer. The opening in the second insulating layer is extended through the first insulating layer and the openings in the first and second insulating layers are filled with a conductor to create a connection between the first interconnect region and a region above the second insulating layer.

Abstract: Adhesive force on less than all die on a cutting support film after cutting is reduced such that only selected die are readily displaceable from the tape or film. In one embodiment, a semiconductor wafer surface is adhered to an area on radiation sensitive tape. The wafer is processed on the tape. Cutting such wafer into individual die is one example processing. Less than all of the tape area is then exposed to radiation effective to reduce degree of adhesion of the wafer surface to the tape. At least a portion of the processed wafer and at least a portion of the tape which has been exposed to the radiation are then separated from one another.

Abstract: A method for recycling monitoring control wafers includes cleaning the wafers after performing a sheet resistance (Rs) measurement on a bare silicon monitoring control wafer of an ion implanter, and then converting the wafer into a recyclable control wafer. A recyclable control wafer for a thermal wave (TW) measurement of destruction can be obtained by forming a screen layer on the wafer, performing a TW measurement, performing ion implantation by the monitoring recipe, performing TW measurement again, performing ion drive-in to drive implanted ions into the deeper areas of the substrate, removing the screen layer, and then forming another screen layer on the wafer to put the wafer into the recycling process of a TW measurement.

Abstract: Disclosed is a chip stack package having a remarkably short interconnection paths between the semiconductor chips and external device, and between the respective semiconductor chips. The chip stack package comprises: at least two semiconductor chips disposed in series vertically in the package, wherein bonding pads are disposed at both sides of the respective semiconductor chips and vertically open slots are formed in the bonding pads; lead frames inserted into the slots of the respective semiconductor chips so as to electrically connect the respective bonding pads; and an epoxy compound for molding the resultant structure entirely so as to expose an interconnection portion of the respective lead frames.

Abstract: The invention relates to an improvement in formation of a gate electrode. In the invention, there are formed first and second oxides on a surface of a substrate. The second oxides have a top surface higher by a height H than top surfaces of the first oxides. A gate electrode composed of a polysilicon film and a silicide film deposited on the polysilicon film is formed so that the polysilicon film is planarized at a level higher than top surfaces of the first oxides but lower than top surfaces of the second oxides. The invention prevents excessive etching of the polysilicon film without fabrication steps being increased, and thus makes it possible to form a gate electrode having a dimension defined by a mask.

Abstract: A method of performing electron beam lithography on high resistivity substrates including forming semiconductor material on a high resistivity substrate and etching the semiconductor material to form mesas with electrically interconnecting bridges between the mesas. Semiconductor devices are formed in the mesas employing electron beam lithography and charges generated by the electron beam lithography are dispersed along the interconnecting bridges thereby preventing charge accumulation on the mesas. The bridges are removed by etching or sawing during die separation.

Abstract: A substrate has an insulating surface; a fine wire region disposed on the insulating surface of the substrate and extending long in one direction; a first insulating film formed on the fine wire region at least at a partial area along the longitudinal direction of the fine wire region; and a first micro box region formed on the first insulating film over the fine wire region at a partial area along the longitudinal direction of the fine wire region a semiconductor device. The semiconductor device has a fine wire region and a micro box region to realize control of a single electron level. The manufacturing method for the semiconductor device is also disclosed.

Abstract: A semiconductor IC including a resistance element on a circuit substrate. The resistance element includes a resistance layer formed on an insulating layer. The resistance layer is formed using a Si layer obtained by forming an a-Si layer, doping the a-Si layer with impurities, and heating the doped a-Si layer to diffuse the impurities while substantially preserving the fineness of the a-Si layer surface. Preferably, a SiN layer is provided lying beneath the resistance layer. A capacitor may be integrated on the same circuit substrate where the resistance element is formed. In this case, a lower electrode, a SiN dielectric layer, and an upper electrode are formed in this order to constitute a capacitor. The SiN dielectric layer of the capacitor is formed extending from a capacitor formation region to another region, so that the resistance layer of the resistance element is formed on the extending SiN dielectric layer.

Abstract: An SOI device and a method for fabricating the same in which floating body effect is reduced and the performance is thus improved are disclosed, the SOI device including a semiconductor substrate; a first buried insualting film formed on the semiconductor substrate; a first conductivity type silicon layer formed on the first buried insulating film; an active region and a first conductivity type semiconductor layer formed to be isolated on predetermined areas of the first conductivity type silicon layer; second buried insulating films formed to be isolated from one another in the first conductivity type silicon layer to connect the first conductivity type semiconductor layer with the active region through the first conductivity type silicon layer; a gate electrode formed on the active region; impurity region formed in the semiconductor substrate at both sides of the gate electrode; and contact pads formed on the first conductivity type silicon layer.

Abstract: A single crystal silicon film nanostructure capable of optical emission is aterally disposed on an insulating transparent substrate of sapphire. By laterally disposing the nanostructure, adequate support for the structure is provided, and the option of fabricating efficient electrical contact structures to the nanostructure is made possible. The method of the invention begins with the deposition of ultrathin layers of silicon on the substrate. A Solid Phase Epitaxy improvement process is then used to remove crystalline defects formed during the deposition. The silicon is then annealed and thinned using thermal oxidation steps to reduce its thickness to be on the order of five nanometers in height. The width and length of the nanostructure are defined by lithography. The nanometer dimensioned silicon is then spin-coated with a resist with width and length definition in the resist being performed by way of electron beam exposure.

Abstract: A preparation method for an integrated assembly of a microchannel and an element is disclosed. In the preparation method of this invention, an element is prepared between a substrate and a sacrificial layer. Two protection layers, which are resistant to etchant for said substrate and said sacrificial layer, are prepared to isolate said element from its ambient environment. Said sacrificial layer defines an area to be etched off such that a microchannel may be formed. A coating layer with etching windows is then prepared on said sacrificial layer and the assembly is etched in an etchant to etch off said sacrificial layer and an area of said substrate beneath said sacrificial layer. An integrated assembly of a closed microchannel and an element is then accomplished. In the invented method, no bonding process is necessary and the integrated assembly so prepared has a planarization surface. This invention also disclosed a microchannel-element assembly prepared under the method of this invention.