Patents Examined by Zandra V. Smith
  • Patent number: 11145752
    Abstract: A method includes forming a gate dielectric layer, forming a metal gate strip over a bottom portion of the gate dielectric layer, and performing a first etching process on the metal gate strip to remove a portion of the metal gate strip. The first etching process is performed anisotropically. After the first etching process, a second etching process is performed on the metal gate strip to remove a residue portion of the metal gate strip. The second etching process includes an isotropic etching process. A dielectric material is filled into a recess left by the etched portion and the etched residue portion of the metal gate strip.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: October 12, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chieh-Ning Feng, Chih-Chang Hung, Bing-Hung Chen, Yih-Ann Lin
  • Patent number: 11145592
    Abstract: Semiconductor devices and methods of forming the same are provided. A method according to an embodiment includes receiving a substrate including a lower contact feature, depositing a first dielectric layer over a substrate, forming a metal-insulator-metal (MIM) structure over the first dielectric layer, depositing a second dielectric layer over the MIM structure, performing a first etch process to form an opening that extends through the second dielectric layer to expose the MIM structure, performing a second etch process to extend the opening through the MIM structure to expose the first dielectric layer; and performing a third etch process to further extend the opening through the first dielectric layer to expose the lower contact feature. Etchants of the first etch process and the third etch process include fluorine while the etchant of the second etch process is free of fluorine.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: October 12, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsiang-Ku Shen, Jian-Ming Huang, Han-Yi Chen, Ecko Lu, Hsiang-Yu Tsai, Chih-Hung Lu, Wen-Tung Chen
  • Patent number: 11145714
    Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type, an impurity region of a second conductivity type formed in a surface layer portion of the semiconductor layer, a terminal region of the second conductivity type that is formed in the surface layer portion of the semiconductor layer along a peripheral edge of the impurity region and that has a second conductivity type impurity concentration higher than a second conductivity type impurity concentration of the impurity region, and a surface electrode that is formed on the semiconductor layer and that has a connection portion connected to the impurity region and to the terminal region.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: October 12, 2021
    Assignee: ROHM CO., LTD.
    Inventor: Jun Takaoka
  • Patent number: 11145504
    Abstract: A method of forming a film stack with reduced defects is provided and includes positioning a substrate on a substrate support within a processing chamber and sequentially depositing polysilicon layers and silicon oxide layers to produce the film stack on the substrate. The method also includes supplying a current of greater than 5 ampere (A) to a plasma profile modulator while generating a deposition plasma within the processing chamber, exposing the substrate to the deposition plasma while depositing the polysilicon layers and the silicon oxide layers, and maintaining the processing chamber at a pressure of greater than 2 Torr to about 100 Torr while depositing the polysilicon layers and the silicon oxide layers.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: October 12, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Zhijun Jiang, Ganesh Balasubramanian, Arkajit Roy Barman, Hidehiro Kojiri, Xinhai Han, Deenesh Padhi, Chuan Ying Wang, Yue Chen, Daemian Raj Benjamin Raj, Nikhil Sudhindrarao Jorapur, Vu Ngoc Tran Nguyen, Miguel S. Fung, Jose Angelo Olave, Thian Choi Lim
  • Patent number: 11145515
    Abstract: In a manufacturing method of a semiconductor device including a substrate having a front surface and a rear surface, and a film attached to the rear surface, the film is attached on the rear surface, a rear surface side groove is provided by half-cutting the substrate from the rear surface together with the film, a protective member is attached to the film after the rear surface side groove is provided, and a front surface side groove connected to the rear surface side groove is provided by dicing the substrate from the front surface after the protective member is attached.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: October 12, 2021
    Assignee: DENSO CORPORATION
    Inventors: Shuntaro Yamada, Akinori Kanda, Tetsuo Yoshioka, Takashige Nagao, Kouichi Miyashita
  • Patent number: 11139245
    Abstract: In one embodiment, an integrated circuit includes a first pattern metal layer, a second pattern metal layer formed over the first pattern metal layer, wherein the second pattern metal layer comprises a second plurality of metal tracks extending in a first direction and less than 9, a third pattern metal layer disposed between the first pattern metal layer and the second pattern metal layer, the third pattern metal layer including, a first metal track segment, a second metal track segment shifted in a second direction from the first metal track segment, and a third metal track segment shifted in the second direction from the second metal track segment, wherein the second plurality of metal tracks, and at least a portion of each of the first metal track segment, the second metal track segment, and the third metal track segment are within a double cell height in the second direction.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: October 5, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Shih-Wei Peng, Jiann-Tyng Tzeng
  • Patent number: 11139399
    Abstract: A method of forming a vertical transistor is provided. The method includes forming a first set of vertical fins in a first row on a first bottom source/drain layer, and a second set of vertical fins in a second row on a second bottom source/drain layer, wherein the vertical fins in the same row are separated by a spacing with a sidewall-to-sidewall distance, SD, and the vertical fins in the same column of adjacent rows are separated by a gap having a gap distance, GD. The method further includes forming a gate metal layer on the first set of vertical fins and the second set of vertical fins, wherein the gate metal layer does not fill in the gap between vertical fins in the same column, and forming a cover layer plug in the remaining gap after forming the gate metal layer.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: October 5, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Juntao Li, Kangguo Cheng, Ruilong Xie, Chanro Park
  • Patent number: 11139202
    Abstract: Integrated chips and methods of forming the same include forming upper dummy lines over lower conductive lines. The lower conductive lines are recessed to form conductive vias between the lower conductive lines and the upper dummy lines. The upper dummy lines are replaced with upper conductive lines that contact the conductive vias.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: October 5, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chanro Park, Koichi Motoyama, Kenneth C. K. Cheng, Chih-Chao Yang
  • Patent number: 11139419
    Abstract: A method for producing a sealed optical semiconductor device makes it possible to seal an optical semiconductor element using a sealing film. The method includes: placing a sealing film on an optical semiconductor element substrate on which an optical semiconductor element is placed within a pressure reduction chamber, and the pressure within the chamber is reduced; heating the film where at least the periphery of the film is thermally fused to the surface of the optical semiconductor element placement substrate; and a step in which the reduction of pressure within the chamber is released and the optical semiconductor element placement substrate is sealed by the film. The temperature T2 of the optical semiconductor element placement substrate when the reduction of pressure within the chamber is released is a temperature at which the film exhibits a tensile strength of 0.02-0.15 MPa and an elongation at break of 150-450%.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: October 5, 2021
    Assignees: DuPont Toray Specialty Materials Kabushiki Kaisha, Dow Silicones Corporation
    Inventors: Eiji Kitaura, Masaaki Amako, Steven Swier
  • Patent number: 11139256
    Abstract: Systems, apparatus, and methods related to tamper-resistant integrated circuits are described. The tamper-resistant integrated circuits include tamper-resistant features including a tamper-resistant material formulated or configured to exhibit a change in at least one electrical property responsive to exposure to oxygen, electromagnetic radiation, or other environmental conditions. Data located within the integrated circuit may be erased, or at least a portion of the integrated circuit may be destroyed, responsive to a change in the at least one electrical property. In some examples, one or more electrical properties of a tamper-resistant feature may be measured. A change in an electrical property may be an indication that the associated integrated circuit has been tampered with.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: October 5, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Diana C. Majerus, Scott D. Van De Graaff, Matthew N. Rocklein
  • Patent number: 11133438
    Abstract: A light-emitting device incorporates an electrode that includes conductive nanoparticles to increase emission performance. A light-emitting device includes a substrate; a first electrode disposed on the substrate between a viewing side of the light-emitting device and the substrate; a second electrode disposed between the first electrode and the viewing side of the light-emitting device, wherein the second electrode includes a layer of nanoparticles that are electrically conductive; and an emissive layer comprising quantum nanoparticles in electrical contact with the first electrode and the second electrode, wherein the first emissive layer includes a material that emits light when electrically excited. Multiple light-emitting devices may constitute sub-pixels that are combined into a pixel, such as for a display device, wherein each sub-pixel emits light of a different color.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: September 28, 2021
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Edward Andrew Boardman, Tim Michael Smeeton
  • Patent number: 11133328
    Abstract: A semiconductor device includes: a stack structure including horizontal conductive patterns and interlayer insulating layers, which are alternately stacked; gate patterns overlapping with both ends of the stack structure under the stack structure, the gate patterns being spaced apart from each other; and a channel pattern including vertical parts penetrating the stack structure, and a connection part disposed under the stack structure, the connection part connecting the vertical parts.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: September 28, 2021
    Assignee: SK hynix Inc.
    Inventor: Kang Sik Choi
  • Patent number: 11133181
    Abstract: Methods of forming silicon nitride thin films on a substrate in a reaction space under high pressure are provided. The methods can include a plurality of plasma enhanced atomic layer deposition (PEALD) cycles, where at least one PEALD deposition cycle comprises contacting the substrate with a nitrogen plasma at a process pressure of 20 Torr to 500 Torr within the reaction space. In some embodiments the silicon precursor is a silyly halide, such as H2SiI2. In some embodiments the processes allow for the deposition of silicon nitride films having improved properties on three dimensional structures. For example, such silicon nitride films can have a ratio of wet etch rates on the top surfaces to the sidewall of about 1:1 in dilute HF.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: September 28, 2021
    Assignee: ASM IP Holding B.V.
    Inventors: Toshiya Suzuki, Viljami J. Pore, Shang Chen, Ryoko Yamada, Dai Ishikawa, Kunitoshi Namba
  • Patent number: 11127660
    Abstract: Methods are disclosed for forming flat no-leads packages (e.g., QFN packages) with soldering surfaces that are fully coated, e.g., by a tin immersion process, for improved solder connections of the packages to a PCB or other structure. The method includes forming a flat no-leads package structure including a leadframe terminal structure having an exposed top or bottom surface; forming a first coating of a first coating material (e.g., tin) on the exposed top or bottom surface; cutting through a full thickness of the leadframe terminal structure to define an exposed terminal sidewall surface; and forming a second coating of a second coating material (e.g., tin) over the full height of the exposed terminal sidewall surface. The coating (e.g., tin immersion coating) covering the full height of the leadframe terminal sidewall may enhance the flow of solder material, e.g., when soldering to a PCB, to provide an improved solder connection.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: September 21, 2021
    Assignee: Microchip Technology Incorporated
    Inventors: Rangsun Kitnarong, Vichanart Nimibutr, Pattarapon Poolsup, Chanyuth Junjuewong
  • Patent number: 11127755
    Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a gate electrode above the substrate, a blocking layer on the gate electrode, a plurality of charge trapping layers on the blocking layer, a tunneling layer on the plurality of charge trapping layers, and a plurality of channel layers on the tunneling layer. The plurality of charge trapping layers are discrete and disposed at different levels. The plurality of channel layers are discrete and disposed at different levels. Each of the channel layers corresponds to a respective one of the charge trapping layers.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: September 21, 2021
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventor: Hongbin Zhu
  • Patent number: 11127694
    Abstract: A physical unclonable functions (PUF) device including a first copper electrode, a second electrode, and a silicon oxide layer positioned directly between the first copper electrode and the second electrode; a method of producing a PUF device; an array comprising a PUF device; and a method of generating a secure key with a plurality of PUF devices.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: September 21, 2021
    Assignee: ARIZONA BOARD OF REGENTS ON BEHALF OF ARIZONA STATE UNIVERSITY
    Inventors: Michael Kozicki, Wenhao Chen
  • Patent number: 11127668
    Abstract: A semiconductor device comprises a first semiconductor package including a conductive layer. A substrate including an interconnect structure is disposed over the conductive layer. The interconnect structure of the substrate with the conductive layer of the first semiconductor package are self-aligned. A plurality of openings is formed in the substrate. An adhesive is disposed between the substrate and the first semiconductor package and in the openings of the substrate. A redistribution layer (RDL) is formed over the first semiconductor package opposite the substrate. A pitch of the substrate is different from a pitch of the RDL. The adhesive extends to the interconnect structure of the substrate. A second semiconductor package is disposed over the substrate and the first semiconductor package.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: September 21, 2021
    Inventors: Il Kwon Shim, Pandi C. Marimuthu, Won Kyoung Choi, Sze Ping Goh, Jose A. Caparas
  • Patent number: 11127825
    Abstract: A method of forming a semiconductor structure includes forming a first portion of a source/drain contact over a source/drain region of a fin-type field-effect transistor (FinFET), the source/drain region being formed over a fin providing a channel region of the FinFET and being adjacent a gate spacer surrounding a gate region of the FinFET. The method also includes forming a first interlayer dielectric (ILD) layer over the first portion of the source/drain contact, the gate spacer and the gate region, and forming a second ILD layer over the first ILD layer. The method further includes forming a second portion of the source/drain contact over the first portion of the source/drain contact in a first opening in the first ILD layer, and forming a third portion of the source/drain contact over the second portion of the source/drain contact in a second opening in the second ILD layer. The second opening is larger than the first opening.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: September 21, 2021
    Assignee: International Business Machines Corporation
    Inventors: Chanro Park, Kangguo Cheng, Ruilong Xie, Hari Prasad Amanapu
  • Patent number: 11127857
    Abstract: Semiconductor devices and methods of manufacturing semiconductor devices are provided. In embodiments a treatment process is utilized in order to introduce silicon into a p-metal work function layer. By introducing silicon into the p-metal work function layer, subsequently deposited layers which may comprise diffusable materials such as aluminum can be prevented from diffusing through the p-metal work function layer and affect the operation of the device.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: September 21, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Yi Lee, Da-Yuan Lee, Ching-Hwanq Su
  • Patent number: 11121142
    Abstract: A method of manufacturing a memory structure including the following steps is provided. A spacer layer is formed on sidewalls of gate stack structures. A protective material layer covering the spacer layer and the gate stack structures is formed. A mask material layer is formed on the protective material layer. There is a void located in the mask material layer between two adjacent gate stack structures. A first distance is between a top of the protective material layer and a top of the mask material layer. A second distance is between a top of the void and a top of the mask material layer above the void. A third distance is between a bottom of the void and a bottom of the mask material layer below the void. The first distance is greater than a sum of the second and third distances.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: September 14, 2021
    Assignee: Winbond Electronics Corp.
    Inventors: Che-Jui Hsu, Chun-Sheng Lu, Ying-Fu Tung, Chen-Wei Liao