Patents Examined by Zandra V. Smith
  • Patent number: 11362311
    Abstract: Substrates are disclosed that include an embedded or partially-embedded microlens array. Devices are disclosed that include an OLED disposed over a substrate having an embedded or partially embedded micro lens array. Devices as disclosed herein redirect up to 100% of the light that otherwise would be confined in organic and electrode layers toward the substrate and thus provide improved light extraction and device efficiency.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: June 14, 2022
    Assignee: THE REGENTS OF THE UNIVERSITY OF MICHIGAN
    Inventors: Stephen R. Forrest, Yue Qu
  • Patent number: 11355378
    Abstract: A method includes forming an adhesive layer over a carrier, forming a sacrificial layer over the adhesive layer, forming through-vias over the sacrificial layer, and placing a device die over the sacrificial layer. The Method further includes molding and planarizing the device die and the through-vias, de-bonding the carrier by removing the adhesive layer, and removing the sacrificial layer.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: June 7, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hsiang Hu, Chung-Shi Liu, Hung-Jui Kuo, Ming-Da Cheng
  • Patent number: 11335617
    Abstract: An electronic component whose reliability is less likely to decrease while its thermal conductivity is maintained. A semiconductor chip is mounted on a substrate. The semiconductor chip is sealed with a sealing resin layer. The sealing resin layer includes a binder and two types of fillers having a plurality of particles dispersed in the binder. As the two types of fillers, fillers at least one of whose physical quantities, which are average particle diameter and density, are different from each other are used. The total volume density of the fillers in the sealing resin layer decreases in an upward direction from the substrate, and a portion of the sealing resin layer in a height direction of the sealing resin layer has an area in which the two types of fillers are present in a mixed manner.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: May 17, 2022
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Hiroaki Tokuya, Yuichi Sano, Toshihiro Tada
  • Patent number: 11315905
    Abstract: A semiconductor package includes a package substrate, a die stack having a first sub-stack part and a second sub-stack part, an interface chip, and a bonding wire structure. The bonding wire structure includes a first signal wire connecting first signal die pads included in the first sub-stack part to each other, a first signal extension wire connecting the first signal wire to the interface chip, a second signal wire connecting second signal die pads included in the first sub-stack part to each other, a second signal extension wire connecting the second signal wire to the interface chip, an interpose wire connecting interpose die pads included in the first and second sub-stack parts to each other and electrically connecting the interpose die pads to the interface chip, and a shielding wire branched from the interpose wire.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: April 26, 2022
    Assignee: SK hynix Inc.
    Inventor: Chul Park
  • Patent number: 11315848
    Abstract: A semiconductor device, includes: a semiconductor element including an element main surface and an element back surface facing opposite sides in a thickness direction; a wiring part electrically connected to the semiconductor element; an electrode pad electrically connected to the wiring part; a sealing resin configured to cover a part of the semiconductor element; and a first metal layer configured to make contact with the element back surface and exposed from the sealing resin, wherein the semiconductor element overlaps the first metal layer when viewed in the thickness direction.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: April 26, 2022
    Assignee: ROHM CO., LTD.
    Inventor: Isamu Nishimura
  • Patent number: 11302592
    Abstract: A semiconductor package includes a package substrate having a top surface and a bottom surface, and a stiffener ring mounted on the top surface of the package substrate. The stiffener ring includes a reinforcement rib that is coplanar with the stiffener ring on the top surface of the package substrate. At least two compartments are defined by the stiffener ring and the reinforcement rib. At least two individual chip packages are mounted on chip mounting regions within the at least two compartments, respectively, thereby constituting a package array on the package substrate.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: April 12, 2022
    Assignee: MediaTek Inc.
    Inventors: Chi-Wen Pan, I-Hsuan Peng, Sheng-Liang Kuo, Yi-Jou Lin, Tai-Yu Chen
  • Patent number: 11296110
    Abstract: A nonvolatile memory device includes a mold structure including a plurality of insulating patterns and a plurality of gate electrodes alternately stacked on a substrate, a semiconductor pattern penetrating through the mold structure and contacting the substrate, a first charge storage film, and a second charge storage film separated from the first charge storage film. The first and second charge storage films are disposed between each of the gate electrodes and the semiconductor pattern. Each of the gate electrodes includes a first recess and a second recess which are respectively recessed inward from a side surface of the gate electrodes. The first charge storage film fills at least a portion of the first recess, and the second charge storage film fills at least a portion of the second recess.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: April 5, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kwang Young Jung, Jong Won Kim, Young Hwan Son, Jee Hoon Han
  • Patent number: 11282987
    Abstract: A method of manufacturing a display device includes preparing a plurality of light-emitting element packages on a substrate, preparing a first solution including first semiconductor nanocrystals, applying a voltage to a part of the plurality of light-emitting element packages to transport the first semiconductor nanocrystals to a region overlapped with the part of the plurality of light-emitting element packages, and forming a first color conversion layer with the first semiconductor nanocrystals.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: March 22, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Deukseok Chung, Tae Gon Kim
  • Patent number: 11280558
    Abstract: A composite sheet, including: a buffer sheet; and a heat dissipation sheet on one surface of the buffer sheet. One surface of the heat dissipation sheet facing the one surface of the buffer sheet may have a smaller area than the one surface of the buffer sheet. A display device includes a display panel and a composite sheet on one surface of the display panel.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: March 22, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventors: Won Il Lee, Min Seop Kim
  • Patent number: 11282854
    Abstract: A semiconductor device is provided. The semiconductor device includes a channel structure that extends from a side of a substrate. The channel structure has sidewalls and a bottom region. The channel structure includes a bottom channel contact that is positioned at the bottom region, and a channel layer that is formed along the sidewalls and over the bottom channel contact. The channel structure further includes a high-k layer that is formed over the channel layer along the sidewalls of the channel structure and over the bottom channel contact.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: March 22, 2022
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Yingjie Ouyang, Zhiliang Xia, Lei Jin, Qiguang Wang, Wenxi Zhou, Zhongwang Sun, Rui Su, Yueqiang Pu, Jiwei Cheng
  • Patent number: 11282856
    Abstract: A semiconductor device may include a substrate, an electrode structure including electrodes stacked on the substrate, an upper semiconductor pattern penetrating at least a portion of the electrode structure, and a lower semiconductor pattern between the substrate and the upper semiconductor pattern. The upper semiconductor pattern includes a gap-filling portion and a sidewall portion extending from the gap-filling portion in a direction away from the substrate, the lower semiconductor pattern includes a concave top surface, the gap-filling portion fills a region enclosed by the concave top surface, a top surface of the gap-filling portion has a rounded shape that is deformed toward the substrate, and a thickness of the sidewall portion is less than a thickness of the gap-filling portion.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: March 22, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-Hoon Choi, Sunggil Kim, Seulye Kim, HongSuk Kim, Phil Ouk Nam, Jaeyoung Ahn
  • Patent number: 11282743
    Abstract: The present application discloses a semiconductor device with the multi-layered connecting structure and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a single-layered connecting structure positioned above the substrate, and a multi-layered connecting structure positioned above the substrate and including a plurality of first conductive layers and a plurality of second conductive layers alternatively stacked. A top surface of the multi-layered connecting structure is substantially coplanar with a top surface of the single-layered connecting structure and a width of the multi-layered connecting structure is less than a width of the single-layered connecting structure.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: March 22, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Cheng-Hsiang Fan
  • Patent number: 11282944
    Abstract: In a method, a first dielectric layer is formed over semiconductor fins, a second dielectric layer is formed over the first dielectric layer, the second dielectric layer is recessed below a top of each of the semiconductor fins, a third dielectric layer is formed over the recessed second dielectric layer, and the third dielectric layer is recessed below the top of the semiconductor fin, thereby forming a wall fin. The wall fin includes the recessed third dielectric layer and the recessed second dielectric layer disposed over the recessed third dielectric layer. The first dielectric layer is recessed below a top of the wall fin, a fin liner layer is formed, the fin liner layer is recessed and the semiconductor fins are recessed, and source/drain epitaxial layers are formed over the recessed semiconductor fins, respectively. The source/drain epitaxial layers are separated by the wall fin from each other.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: March 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Chi Yu, Jui Fu Hseih, Yu-Li Lin, Chih-Teng Liao, Yi-Jen Chen
  • Patent number: 11276608
    Abstract: A semiconductor structure and a forming method thereof are provided.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: March 15, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventors: Wang Wei, Su Bo, Hu You Cun
  • Patent number: 11276609
    Abstract: A semiconductor structure and a method for forming the same, and a transistor are provided. In one form, a method includes: providing a base, where a dummy gate layer is formed on the base, a spacer is formed on a side wall of the dummy gate layer, an interlayer dielectric layer is formed on the base exposed from the dummy gate layer and the spacer, and the interlayer dielectric layer exposes a top of the dummy gate layer and a top of the spacer; removing a portion of a height of the dummy gate layer to form a remaining dummy gate layer, where the remaining dummy gate layer and the spacer enclose a trench; thinning a spacer exposed from the remaining dummy gate layer along a direction perpendicular to a side wall of the trench; after the thinning, removing the remaining dummy gate layer to form a gate opening within the interlayer dielectric layer; and forming a metal gate structure in the gate opening. Through the thinning, a gate opening whose side wall is provided with a remaining spacer is T-shaped.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: March 15, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fei Zhou
  • Patent number: 11271011
    Abstract: Inventive concepts describe a method for high performance standard cell design techniques in FinFET based library using LLE. Inventive concepts describe a fabrication process using a standard FinFET cell layout having double diffusion breaks (DDBs) and single diffusion breaks (SDBs). According to one example embodiment, the method comprises of removing one or more fingers of a P-type FinFet (PFET) from a standard FinFET cell layout. After removing the one or more fingers, a Half-Double Diffusion Break (Half-DDB) is introduced on a N-type FinFET (NFET) side inside a cell boundary using a cut-poly layer. The cut-poly layer not only isolates the PFET and NFET gates and also becomes an integral part of hybrid structure. Further, the removed one or more fingers of PFET gates are converted to two floating PFET gates by shorting a drain terminal and a source terminal of the PFET gate to a common power net.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: March 8, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Shyam Agarwal, Abhishek Ghosh, Parvinder Kumar Rana
  • Patent number: 11271087
    Abstract: In a method for manufacturing a semiconductor device, a substrate is provided. A dummy gate is formed on the substrate. A first dielectric layer is formed to peripherally enclose the dummy gate over the substrate. A second dielectric layer is formed to peripherally enclose the first dielectric layer over the substrate. The second dielectric layer and the first dielectric layer are formed from different materials. An implant operation is performed on the first dielectric layer to form a first doped portion in the first dielectric layer. The dummy gate is removed to form a hole in the first dielectric layer. An operation of removing the dummy gate includes removing a portion of the first doped portion to form the hole having a bottom radial opening area and a top radial opening area which is greater than the bottom radial opening area. A metal gate is formed in the hole.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: March 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
  • Patent number: 11264272
    Abstract: The present technology relates to Provided are a semiconductor device in which an air gap structure can be formed in any desired region regardless of the layout of metallic wiring lines, a method for manufacturing the semiconductor device, and an electronic apparatus. A first wiring layer and a second wiring layer including a metallic film are stacked via a diffusion preventing film that prevents diffusion of the metallic film. The diffusion preventing film is formed by burying a second film in a large number of holes formed in a first film. At least the first wiring layer includes the metallic film, an air gap, and a protective film formed with the second film on the inner peripheral surface of the air gap, and the opening width of the air gap is equal to the opening width of the holes formed in the first film or is greater than the opening width of the holes.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: March 1, 2022
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Suguru Saito, Nobutoshi Fujii, Masaki Haneda, Kazunori Nagahata
  • Patent number: 11264236
    Abstract: A substrate processing method includes: providing a substrate having a pattern formed on a surface layer thereof; setting a temperature of the substrate such that a change in the pattern becomes a predetermined change amount; forming a reaction layer having a thickness corresponding to the temperature set in the setting on the surface layer of the substrate; and applying energy to the substrate formed with the reaction layer thereby removing the reaction layer from the surface layer of the substrate.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: March 1, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Toru Hisamatsu, Takayuki Katsunuma, Shinya Ishikawa, Yoshihide Kihara, Masanobu Honda
  • Patent number: 11264393
    Abstract: A semiconductor device includes a fin structure. A source/drain region is formed on the fin structure. A first gate structure is disposed over the fin structure. A source/drain contact is disposed over the source/drain region. The source/drain contact has a protruding segment that protrudes at least partially over the first gate structure. The source/drain contact electrically couples together the source/drain region and the first gate structure.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: March 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jui-Lin Chen, Chao-Yuan Chang, Ping-Wei Wang, Fu-Kai Yang, Ting Fang, I-Wen Wu, Shih-Hao Lin