Patents Examined by Zandra V. Smith
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Patent number: 12217964Abstract: A method of obtaining a doped semiconductor layer, including the successive steps of: a) performing, in a first single-crystal layer made of a semiconductor alloy of at least a first element A1 and a second element A2, an ion implantation of a first element B which is a dopant for the alloy and of a second element C which is not a dopant for the alloy, to make an upper portion of the first layer amorphous and to preserve the crystal structure of a lower portion of the first layer; and b) performing a solid phase recrystallization anneal of the upper portion of the first layer, resulting in transforming the upper portion of the first layer into a doped single-crystal layer of the alloy.Type: GrantFiled: November 25, 2020Date of Patent: February 4, 2025Assignee: Commissariat à l'Énergie Atomique et aux Énergies AlternativesInventors: Virginie Maffini Alvaro, Hubert Bono, Julia Simon
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Patent number: 12191213Abstract: An inspection method for a divided wafer includes a wafer lamination step of stacking a transfer wafer on top of a wafer that has been divided into a plurality of chips, a particle transfer step of, after the wafer lamination step is carried out, positioning the transfer wafer on a lower side and the divided wafer on an upper side and applying a vibration to the wafer stacked on the transfer wafer, to drop particles adhering to side surfaces of the chips onto the transfer wafer, and an inspection step of, after the particle transfer step is carried out, inspecting the particles on the transfer wafer.Type: GrantFiled: August 9, 2022Date of Patent: January 7, 2025Assignee: DISCO CORPORATIONInventor: Naoko Yamamoto
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Patent number: 12170326Abstract: A semiconductor device includes a buried power rail (BPR) over a substrate and a semiconductor structure over the BPR. The semiconductor structure is tube-shaped and extends along a vertical direction. The semiconductor structure includes a first source/drain (S/D) region over the BPR, a gate region over the first S/D region, and a second S/D region over the gate region. The semiconductor device includes a first S/D interconnect structure extending from the BPR and further into the semiconductor structure such that a top portion of the first S/D interconnect structure is surrounded by the first S/D region. The semiconductor device includes a gate structure that includes (i) a gate oxide formed along an inner surface of the gate region and (ii) a gate electrode formed along sidewalls of the gate oxide in the gate region. The semiconductor device includes a second S/D interconnect structure positioned over the second S/D region.Type: GrantFiled: November 4, 2021Date of Patent: December 17, 2024Assignee: Tokyo Electron LimitedInventors: Mark I. Gardner, H. Jim Fulford
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Patent number: 12166117Abstract: In an embodiment, a Group III nitride-based transistor device is provided that includes a Group III nitride-based body and a p-type Schottky gate including a metal gate on a p-doped Group III nitride structure. The p-doped Group III nitride structure includes an upper p-doped GaN layer in contact with the metal gate and having a thickness d1, a lower p-doped Group III nitride layer having a thickness d2 and including p-doped GaN that is arranged on and in contact with the Group III nitride-based body, and at least one p-doped AlxGa1-xN layer arranged between the upper p-doped GaN layer and the lower p-doped Group III nitride layer, wherein 0<x<1. The thickness d2 of the lower p-doped Group III nitride layer is larger than the thickness d1 of the upper p-doped GaN layer.Type: GrantFiled: December 22, 2021Date of Patent: December 10, 2024Assignee: Infineon Technologies Austria AGInventor: Luca Sayadi
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Patent number: 12119264Abstract: Embodiments herein include semiconductor structures that may include a first field-effect transistor (FET) stacked above a second FET in a non-step nanosheet structure, and a bottom contact electrically connected to a first bottom source/drain (S/D) of the second FET through a portion of a first top S/D of the first FET.Type: GrantFiled: June 29, 2022Date of Patent: October 15, 2024Assignee: International Business Machines CorporationInventors: Shogo Mochizuki, Gen Tsutsui
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Patent number: 12094819Abstract: A method for forming a package structure is provided. The method includes forming a first interconnect structure over a carrier substrate and disposing a first die structure over the first interconnect structure. The method includes forming a dam structure over the first die structure. The method also includes forming a protection layer over a second interconnect structure. The method further includes bonding the second interconnect structure over the dam structure. In addition, the method includes forming a package layer between the first interconnect structure and the second interconnect structure. The method also includes removing the protection layer.Type: GrantFiled: August 18, 2021Date of Patent: September 17, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Po-Hao Tsai, Techi Wong, Meng-Liang Lin, Yi-Wen Wu, Po-Yao Chuang, Shin-Puu Jeng
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Patent number: 12094726Abstract: The present disclosure relates to semiconductor core assemblies and methods of forming the same. The semiconductor core assemblies described herein may be utilized to form semiconductor package assemblies, printed circuit board (PCB) assemblies, PCB spacer assemblies, chip carrier assemblies, intermediate carrier assemblies (e.g., for graphics cards), and the like. In one embodiment, a substrate core (e.g., a core structure) is implanted with dopants to achieve a desired bulk resistivity or conductivity. One or more conductive interconnections are formed in the substrate core and one or more redistribution layers are formed on surfaces thereof. The substrate core may thereafter be utilized as a core structure for a semiconductor package, PCB, PCB spacer, chip carrier, intermediate carrier, or the like.Type: GrantFiled: December 13, 2021Date of Patent: September 17, 2024Assignee: Applied Materials, Inc.Inventors: Mukhles Sowwan, Samer Banna, Nirmalya Maity, Omkaram Nalamasu, Gary E. Dickerson
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Patent number: 12069913Abstract: A display device includes a substrate, a first conductive layer disposed on the substrate, a first insulating layer disposed on the first conductive layer, a semiconductor layer disposed on the first insulating layer, a second insulating layer disposed on the semiconductor layer, a second conductive layer disposed on the second insulating layer and overlapping the semiconductor layer, and a third insulating layer disposed on the second conductive layer, wherein the first conductive layer includes two end portions separated by cutting a region of the first conductive layer, and the two end portions of the first conductive layer are electrically connected by a first connecting part.Type: GrantFiled: October 19, 2021Date of Patent: August 20, 2024Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Yu Jin Lee, Tae Hui Kim, Yul Kyu Lee, Jung An Lee
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Patent number: 12029063Abstract: The disclosure provides a display panel, a method for manufacturing same, and a displaying device. The display panel is provided with a plurality of display units arranged at intervals and tensile units connecting every two adjacent display units, and the display panel further comprises a substrate; light-emitting elements arranged on one side of the substrate and positioned in the display units; and package structures at least arranged on the surfaces, away from the substrate, of the light-emitting elements and comprising at least one inorganic insulating layer, wherein orthographic projections of at least part of the tensile units on the substrate do not overlap with orthographic projections of the inorganic insulating layers on the substrate.Type: GrantFiled: October 19, 2021Date of Patent: July 2, 2024Assignee: BOE Technology Group Co., Ltd.Inventors: Jingkai Ni, Zhongyuan Sun, Jinxiang Xue, Wenqi Liu, Che An
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Patent number: 11362311Abstract: Substrates are disclosed that include an embedded or partially-embedded microlens array. Devices are disclosed that include an OLED disposed over a substrate having an embedded or partially embedded micro lens array. Devices as disclosed herein redirect up to 100% of the light that otherwise would be confined in organic and electrode layers toward the substrate and thus provide improved light extraction and device efficiency.Type: GrantFiled: November 16, 2018Date of Patent: June 14, 2022Assignee: THE REGENTS OF THE UNIVERSITY OF MICHIGANInventors: Stephen R. Forrest, Yue Qu
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Patent number: 11355378Abstract: A method includes forming an adhesive layer over a carrier, forming a sacrificial layer over the adhesive layer, forming through-vias over the sacrificial layer, and placing a device die over the sacrificial layer. The Method further includes molding and planarizing the device die and the through-vias, de-bonding the carrier by removing the adhesive layer, and removing the sacrificial layer.Type: GrantFiled: March 9, 2020Date of Patent: June 7, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Hsiang Hu, Chung-Shi Liu, Hung-Jui Kuo, Ming-Da Cheng
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Patent number: 11335617Abstract: An electronic component whose reliability is less likely to decrease while its thermal conductivity is maintained. A semiconductor chip is mounted on a substrate. The semiconductor chip is sealed with a sealing resin layer. The sealing resin layer includes a binder and two types of fillers having a plurality of particles dispersed in the binder. As the two types of fillers, fillers at least one of whose physical quantities, which are average particle diameter and density, are different from each other are used. The total volume density of the fillers in the sealing resin layer decreases in an upward direction from the substrate, and a portion of the sealing resin layer in a height direction of the sealing resin layer has an area in which the two types of fillers are present in a mixed manner.Type: GrantFiled: January 16, 2020Date of Patent: May 17, 2022Assignee: Murata Manufacturing Co., Ltd.Inventors: Hiroaki Tokuya, Yuichi Sano, Toshihiro Tada
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Patent number: 11315905Abstract: A semiconductor package includes a package substrate, a die stack having a first sub-stack part and a second sub-stack part, an interface chip, and a bonding wire structure. The bonding wire structure includes a first signal wire connecting first signal die pads included in the first sub-stack part to each other, a first signal extension wire connecting the first signal wire to the interface chip, a second signal wire connecting second signal die pads included in the first sub-stack part to each other, a second signal extension wire connecting the second signal wire to the interface chip, an interpose wire connecting interpose die pads included in the first and second sub-stack parts to each other and electrically connecting the interpose die pads to the interface chip, and a shielding wire branched from the interpose wire.Type: GrantFiled: June 24, 2020Date of Patent: April 26, 2022Assignee: SK hynix Inc.Inventor: Chul Park
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Patent number: 11315848Abstract: A semiconductor device, includes: a semiconductor element including an element main surface and an element back surface facing opposite sides in a thickness direction; a wiring part electrically connected to the semiconductor element; an electrode pad electrically connected to the wiring part; a sealing resin configured to cover a part of the semiconductor element; and a first metal layer configured to make contact with the element back surface and exposed from the sealing resin, wherein the semiconductor element overlaps the first metal layer when viewed in the thickness direction.Type: GrantFiled: December 4, 2019Date of Patent: April 26, 2022Assignee: ROHM CO., LTD.Inventor: Isamu Nishimura
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Patent number: 11302592Abstract: A semiconductor package includes a package substrate having a top surface and a bottom surface, and a stiffener ring mounted on the top surface of the package substrate. The stiffener ring includes a reinforcement rib that is coplanar with the stiffener ring on the top surface of the package substrate. At least two compartments are defined by the stiffener ring and the reinforcement rib. At least two individual chip packages are mounted on chip mounting regions within the at least two compartments, respectively, thereby constituting a package array on the package substrate.Type: GrantFiled: December 11, 2018Date of Patent: April 12, 2022Assignee: MediaTek Inc.Inventors: Chi-Wen Pan, I-Hsuan Peng, Sheng-Liang Kuo, Yi-Jou Lin, Tai-Yu Chen
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Patent number: 11296110Abstract: A nonvolatile memory device includes a mold structure including a plurality of insulating patterns and a plurality of gate electrodes alternately stacked on a substrate, a semiconductor pattern penetrating through the mold structure and contacting the substrate, a first charge storage film, and a second charge storage film separated from the first charge storage film. The first and second charge storage films are disposed between each of the gate electrodes and the semiconductor pattern. Each of the gate electrodes includes a first recess and a second recess which are respectively recessed inward from a side surface of the gate electrodes. The first charge storage film fills at least a portion of the first recess, and the second charge storage film fills at least a portion of the second recess.Type: GrantFiled: February 21, 2020Date of Patent: April 5, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kwang Young Jung, Jong Won Kim, Young Hwan Son, Jee Hoon Han
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Patent number: 11282743Abstract: The present application discloses a semiconductor device with the multi-layered connecting structure and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a single-layered connecting structure positioned above the substrate, and a multi-layered connecting structure positioned above the substrate and including a plurality of first conductive layers and a plurality of second conductive layers alternatively stacked. A top surface of the multi-layered connecting structure is substantially coplanar with a top surface of the single-layered connecting structure and a width of the multi-layered connecting structure is less than a width of the single-layered connecting structure.Type: GrantFiled: July 17, 2020Date of Patent: March 22, 2022Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Cheng-Hsiang Fan
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Patent number: 11282987Abstract: A method of manufacturing a display device includes preparing a plurality of light-emitting element packages on a substrate, preparing a first solution including first semiconductor nanocrystals, applying a voltage to a part of the plurality of light-emitting element packages to transport the first semiconductor nanocrystals to a region overlapped with the part of the plurality of light-emitting element packages, and forming a first color conversion layer with the first semiconductor nanocrystals.Type: GrantFiled: January 30, 2020Date of Patent: March 22, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Deukseok Chung, Tae Gon Kim
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Patent number: 11282944Abstract: In a method, a first dielectric layer is formed over semiconductor fins, a second dielectric layer is formed over the first dielectric layer, the second dielectric layer is recessed below a top of each of the semiconductor fins, a third dielectric layer is formed over the recessed second dielectric layer, and the third dielectric layer is recessed below the top of the semiconductor fin, thereby forming a wall fin. The wall fin includes the recessed third dielectric layer and the recessed second dielectric layer disposed over the recessed third dielectric layer. The first dielectric layer is recessed below a top of the wall fin, a fin liner layer is formed, the fin liner layer is recessed and the semiconductor fins are recessed, and source/drain epitaxial layers are formed over the recessed semiconductor fins, respectively. The source/drain epitaxial layers are separated by the wall fin from each other.Type: GrantFiled: July 31, 2020Date of Patent: March 22, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Chi Yu, Jui Fu Hseih, Yu-Li Lin, Chih-Teng Liao, Yi-Jen Chen
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Patent number: 11280558Abstract: A composite sheet, including: a buffer sheet; and a heat dissipation sheet on one surface of the buffer sheet. One surface of the heat dissipation sheet facing the one surface of the buffer sheet may have a smaller area than the one surface of the buffer sheet. A display device includes a display panel and a composite sheet on one surface of the display panel.Type: GrantFiled: April 8, 2020Date of Patent: March 22, 2022Assignee: Samsung Display Co., Ltd.Inventors: Won Il Lee, Min Seop Kim