Abstract: A chip package includes a semiconductor structure and a redistribution layer. The semiconductor structure has a substrate, a first isolation layer, and a lower ground pad. The substrate has a top surface, a bottom surface opposite to the top surface, a through hole through the top surface and the bottom surface, and a sidewall surrounding the through hole. The first isolation layer is located on the top surface of the substrate, and the lower ground pad is located in the through hole. The redistribution layer extends from the bottom surface of the substrate to the lower ground pad along the sidewall. The redistribution layer covers the entire bottom surface of the substrate and electrically connects the lower ground pad.

Abstract: Embodiments relate to a semiconductor structure and a fabrication method. The method includes: providing a substrate, where a first trench is formed in the substrate; forming a first dielectric layer and a protective material layer in the first trench, where the first dielectric layer is positioned between the protective material layer and the substrate, and an upper surface of the first dielectric layer is lower than an upper surface of the substrate, to expose a portion of a side wall of the first trench; forming a second dielectric layer on the exposed side wall of the first trench; and filling the second trench to form a work function structure, where the work function structure includes a first work function layer and a second work function layer, where the second work function layer is positioned on an upper surface of the first work function layer.

Abstract: A semiconductor structure and method for forming a semiconductor structure includes formation of a recess in a metal layer during the fabrication process to provide process improvements and a conductive via with reduced contact resistance. The semiconductor structure includes a dielectric layer, a metal layer, an etch stop layer, and a conductive via. The top surface of the dielectric layer extends above a top surface of the metal layer, and a bottom surface of the conductive via extends below the top surface of the dielectric layer.

Abstract: A method for manufacturing a pFET transistor, the method for manufacturing the transistor including providing a base structure comprising a silicon channel and a gate structure, the gate structure surrounding the channel leaving two flanks of the channel free; growing a first layer made from silicon-germanium alloy on the flanks of the channel; enriching the channel with germanium atoms from the first layer; and forming a drain region and a source region on either side of the channel.

Abstract: An imaging device according to an embodiment of the present disclosure includes: a first substrate including, in a first semiconductor substrate, a sensor pixel that performs photoelectric conversion; a second substrate including, in a second semiconductor substrate, a readout circuit that outputs a pixel signal based on electric charges outputted from the sensor pixel, the second substrate being stacked on the first substrate; a first insulating layer provided between the first semiconductor substrate and the second semiconductor substrate; and a second insulating layer provided between the first semiconductor substrate and the second semiconductor substrate, and having lower film density than the first insulating layer.

Abstract: A light emitting element includes: a semiconductor structure including an n-side layer, a p-side layer, and an active layer, each being made of a nitride semiconductor, wherein the active layer is positioned between the n-side layer and the p-side layer and is configured to emit ultraviolet light; an n-electrode electrically connected to the n-side layer; and a p-electrode comprising a first metal layer in contact with the p-side layer and electrically connected to the p-side layer. The p-side layer comprises a first layer, a second layer disposed on the first layer, and a third layer disposed on the second layer, each containing a p-type impurity. A surface of the second layer includes an exposed region that is exposed from the third layer. The first layer and the second layer contain Al.

Abstract: A method of wafer bonding includes: forming a first hole in a first insulation layer disposed over a first substrate; performing a first deposition-self-etch process to deposit a first conductive material in the first hole to form a first conductive plug; forming a second hole in a second insulation layer disposed over a second substrate; performing a second deposition-self-etch process to deposit a second conductive material in the second hole to form a second conductive plug; and bonding the first conductive plug with the second conductive plug to form a first grain fusion layer between the first conductive plug and the second conductive plug.

Abstract: A semiconductor device includes an active region and a trapping region positioned peripherally with respect to the active region, the trapping region presenting trapping apertures permitting the passage of particles, the trapping apertures being in fluid communication with at least one trapping chamber for trapping the particles. A method for manufacturing the semiconductor devices from one semiconductor wafer presents semiconductor device regions to be singulated along a dicing portion line.

Abstract: A memory device may include an electrode structure including a plurality of electrode layers and a plurality of interlayer dielectric layers that are alternately stacked on a substrate; a trench in the electrode structure, and having an upper sidewall, a lower sidewall and a horizontal portion that couples the upper sidewall to the lower sidewall and that is parallel to a top surface of the substrate; a dielectric layer in the trench; and a slimming hole in the electrode structure having a sidewall of the trench and a region of the dielectric layer, and having a bottom surface disposed on an electrode layer on which the horizontal portion of the trench is positioned.

Abstract: A method for forming a memory includes: forming a bit line structure and a capacitor contact layer, where the bit line structure includes a bit line, a bit line cap layer and a bit line isolation layer, and the capacitor contact layer covers part of a side wall of the bit line isolation layer; forming a stop layer covering the side wall of the bit line isolation layer; forming a capacitor landing layer covering a top surface of the capacitor contact layer; and etching the bit line isolation layer by using the stop layer as an etch stop layer to form an air gap in the bit line isolation layer. Probability of occurrence of a short circuit between the capacitor landing layer and a bit line is reduced.

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate, having a surface, including a first conductive pathway electrically coupled to a power source; an insulating material on the surface of the package substrate; a first microelectronic component, having a first surface facing the package substrate and an opposing second surface, embedded in the insulating material; a second microelectronic component, having a first surface facing the package substrate and an opposing second surface, embedded in the insulating material; a redistribution layer on the insulating material including a second conductive pathway electrically coupled to the second surface of the second microelectronic component and the second surface of the first microelectronic component; and a wire bond electrically coupling the first and the second conductive pathways.

Abstract: Semiconductor devices with on-pitch vias, and associated systems and methods, are disclosed herein. In one embodiment, the semiconductor device may include a 3-dimensional (3D) cross-point memory array. The semiconductor device also includes access lines for the memory array, which couple with on-pitch vias connected to CMOS circuitry disposed underneath the memory array. In some embodiments, a first access line may be coupled with a first via outside a boundary of the memory array, where the first via is separated from the boundary by a first distance and has a first length longitudinal to the first access line. Further, a second access line may be coupled with a second via outside the boundary, where the second via is separated from the boundary by a second distance greater than the first distance and has a second length longitudinal to the second access line, the second length different from the first length.

Abstract: A semiconductor device includes a stacked structure, first conductive terminals and second conductive terminals. The stacked structure includes a first semiconductor component having a first area and a second semiconductor component stacked on the first semiconductor component and having a second area smaller than the first area, wherein an extending direction of the first area and an extending direction of the second area are perpendicular to a stacking direction of the first semiconductor component and the second semiconductor component. The first conductive terminals are located on the stacked structure, electrically coupled to the first semiconductor component and aside of the second semiconductor component. The second conductive terminals are located on the stacked structure and electrically coupled to the second semiconductor component.

Abstract: This magnetization rotational element includes a spin injection region that extends in a first direction, a first ferromagnetic layer that is laminated on the spin injection region, and a metal region that is adjacent to the spin injection region with an insulator interposed therebetween in a second direction orthogonal to the first direction in a plan view in a lamination direction.

Abstract: A semiconductor structure includes: a transistor structure and a capacitor structure that are arranged along a first direction, where the capacitor structure extends along the first direction; and a wordline staircase structure extending along the first direction, where the wordline staircase structure and the transistor structure are disposed along a second direction intersecting with the first direction. A plane perpendicular to the second direction is used as a reference plane. An orthographic projection of the transistor structure on the reference plane is a first projection. An orthographic projection of the capacitor structure on the reference plane is a second projection. An orthographic projection of the wordline staircase structure on the reference plane is a third projection. The third projection covers the first projection, and the third projection partially overlaps the second projection.

Abstract: A semiconductor device includes a substrate, a lower electrode provided over the substrate, a capacitive insulating film, and an upper electrode provided over the lower electrode, wherein the lower electrode has an upper portion and a lower portion, and at a boundary between the upper portion and the lower portion, the diameter of the upper portion is smaller than the diameter of the lower portion.

Abstract: Semiconductor structures and method of forming the same are provided. A semiconductor structure according to the present disclosure includes a contact feature in a dielectric layer, a passivation structure over the dielectric layer, a conductive feature over the passivation structure, a seed layer disposed between the conductive feature and the passivation structure, a protecting layer disposed along sidewalls of the conductive feature, and a passivation layer over the conductive feature and the protecting layer.

Abstract: A light-emitting element contains negative ions and positive ions, and includes a solid ionic layer, a layer containing quantum dots, and a cathode electrode and an anode electrode. The ionic layer includes a p-type doped region on the anode electrode side containing the negative ions in a higher quantity than the positive ions, an n-type doped region on the cathode electrode side containing the positive ions in a higher quantity than the negative ions, and a junction region between the p-type doped region and the n-type doped region. The layer containing the quantum dots is adjacent to the junction region. Alternatively, the quantum dots are contained in the junction region. Alternatively, the quantum dots are adjacent to the junction region.

Abstract: A vertical memory device includes a substrate having a peripheral circuit structure, first gate patterns having first gate pad regions stacked vertically from the substrate, vertical channel structures penetrating the first gate patterns, first gate contact structures each extending vertically to a corresponding first gate pad region, mold patterns stacked vertically from the substrate, the mold patterns each being positioned at the same height from the substrate with a corresponding gate pattern, peripheral contact structures penetrating the mold patterns to be connected to the peripheral circuit structure, a first, block separation structure disposed between the first gate contact structures and the peripheral contact structures, and a first peripheral circuit connection wiring extending across the first block separation structure to connect one of the first gate contact structures to one of the peripheral contact structures.

Abstract: An imaging device includes a photoelectric converter that converts incident light to charge, a semiconductor substrate that includes an element isolation region and a first impurity region of a first conductivity type, the first impurity region being electrically connected to the photoelectric converter, a plug that includes a first semiconductor, the plug being connected directly to the first impurity region, a pad that includes a second semiconductor, the pad being connected directly to the plug, and a first transistor that includes the first impurity region as one of a source and a drain and includes a first gate. The first impurity region is positioned between the first gate and a first portion of the element isolation region in plan view. The pad overlaps the first gate and the first portion in plan view.