Patents Examined by Zandra V. Smith
  • Patent number: 10811349
    Abstract: An electronic device includes a support wafer, an electronic chip and an encapsulating block for the electronic chip above the support wafer. The support wafer is provided with a first network of electrical connections and a second network of electrical connections formed solely by tracks. First electrical connection elements are interposed between first front electrical contacts of the electronic chip and rear electrical contacts of the first network. Second electrical connection elements are interposed between second front electrical contacts of the electronic chip and internal electrical contact zones of the tracks of the second network. The first network includes front external electrical contacts and the tracks exhibiting external electrical contact zones.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: October 20, 2020
    Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Alps) SAS
    Inventors: David Auchere, Laurent Schwarz, Deborah Cogoni, Eric Saugier
  • Patent number: 10811529
    Abstract: A transistor device comprises at least one gate electrode, a gate runner connected to the at least one gate electrode and arranged on top of a semiconductor body, a plurality of gate pads arranged on top of the semiconductor body, and a plurality of resistor arrangements. Each gate pad is electrically connected to the gate runner via a respective one of the plurality of resistor arrangements, and each of the resistor arrangements has an electrical resistance, wherein the resistances of the plurality of resistor arrangements are different.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: October 20, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Andreas Riegler, Christian Fachmann, Bjoern Fischer, Franz Hirler, Gabor Mezoesi, Hans Weber
  • Patent number: 10811257
    Abstract: A method may include depositing a carbon layer on a substrate using physical vapor deposition, wherein the carbon layer exhibits compressive stress, and is characterized by a first stress value; and directing a dose of low-mass species into the carbon layer, wherein, after the directing, the carbon layer exhibits a second stress value, less compressive than the first stress value.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: October 20, 2020
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Rajesh Prasad, Tzu-Yu Liu, Kyu-Ha Shim, Tom Ho Wing Yu, Zhong Qiang Hua, Adolph Miller Allen, Viabhav Soni, Ravi Rajagopalan, Nobuyuki Sasaki
  • Patent number: 10811496
    Abstract: Techniques are disclosed for forming column IV transistor devices having source/drain regions with high concentrations of germanium, and exhibiting reduced parasitic resistance relative to conventional devices. In some example embodiments, the source/drain regions each includes a thin p-type silicon or germanium or SiGe deposition with the remainder of the source/drain material deposition being p-type germanium or a germanium alloy (e.g., germanium:tin or other suitable strain inducer, and having a germanium content of at least 80 atomic % and 20 atomic % or less other components). In some cases, evidence of strain relaxation may be observed in the germanium rich cap layer, including misfit dislocations and/or threading dislocations and/or twins. Numerous transistor configurations can be used, including both planar and non-planar transistor structures (e.g., FinFETs and nanowire transistors), as well as strained and unstrained channel structures.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: October 20, 2020
    Assignee: Intel Corporation
    Inventors: Glenn A. Glass, Anand S. Murthy
  • Patent number: 10811518
    Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. A lateral end of each of the first semiconductor layers has a V-shape cross section after the first semiconductor layers are laterally etched.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: October 20, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Ching Cheng, Chen-Feng Hsu, Tzu-Chiang Chen, Tung Ying Lee, Wei-Sheng Yun, Yu-Lin Yang
  • Patent number: 10804105
    Abstract: A semiconductor device and its manufacturing method, relating to semiconductor techniques. The semiconductor device manufacturing method comprises: forming a patterned first hard mask layer on a substrate to define a position for buried layers; conducting a first ion implantation using the first hard mask layer as a mask to form a first buried layer and a second buried layer both having a first conductive type and separated from each other at two sides of the first hard mask layer in the substrate; conducting a second ion implantation to form a separation region with a second conductive type opposite to the first conductive type in the substrate between the first and the second buried layers; removing the first hard mask layer; and forming a semiconductor layer on the substrate. This inventive concept reduces an area budget of a substrate and simplifies the manufacturing process.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: October 13, 2020
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Dae Sub Jung, De Yan Chen, Guang Li Yang
  • Patent number: 10805562
    Abstract: The present disclosure relates to an imaging device, a manufacturing method, a semiconductor device, and an electronic device that can further improve image quality. An imaging device includes a photoelectric conversion unit that receives and photoelectrically converts light, a floating diffusion layer that accumulates charge generated by the photoelectric conversion unit, and a diffusion layer that serves as a source or a drain of a transistor. Then, the floating diffusion layer is formed to have an impurity concentration lower than an impurity concentration of the diffusion layer.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: October 13, 2020
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Ryosuke Nakamura, Fumihiko Koga
  • Patent number: 10804265
    Abstract: A semiconductor device includes a first active pattern extending lengthwise along a first direction and a second active pattern extending lengthwise along the first direction and spaced apart from the first active pattern in the first direction. The device also includes a field insulating film between the first active pattern and the second active pattern. An upper surface of the field insulating film is lower than or coplanar with upper surfaces of the first and second active patterns. The device further includes an element isolation structure in an isolation trench in the first active pattern and the field insulating film. An upper surface of the element isolation structure is higher than the upper surfaces of the first and second active patterns.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: October 13, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang Min Yoo, Ju Youn Kim, Hyung Joo Na, Bong Seok Suh, Joo Ho Jung, Eui Chul Hwang, Sung Moon Lee
  • Patent number: 10804155
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a first conductive wire within a first dielectric structure formed on a first surface of a first substrate. A through-substrate-via (TSV) is formed to extend though the first substrate. A second conductive wire is formed within a second dielectric structure formed on a second surface of the first substrate opposing the first surface. The TSV electrically couples the first conductive wire and the second conductive wire. The first conductive wire, the second conductive wire, and the TSV define an inductor that wraps around an axis.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: October 13, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Han Huang, Ching-Chun Wang, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu, Min-Feng Kao
  • Patent number: 10797075
    Abstract: Embodiments of staircase and contact structures of a three-dimensional (3D) memory device and fabrication method thereof are disclosed. The 3D memory device includes a semiconductor substrate and a plurality of through-substrate-trenches penetrating the semiconductor substrate. The 3D memory device also includes a film stack disposed on a first surface of the semiconductor substrate extending through the through-substrate-trenches to a second surface of the semiconductor substrate, wherein the film stack includes alternating conductive and dielectric layers. The 3D memory device also includes a staircase structure formed at an edge of the film stack.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: October 6, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventor: Li Hong Xiao
  • Patent number: 10797070
    Abstract: An alternating stack of insulating layers and spacer material layers is formed over a source-level sacrificial layer overlying a substrate. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory stack structures including a respective vertical semiconductor channel and a respective memory film are formed through the alternating stack. A source-level cavity is formed by removing the source-level sacrificial layer. Semiconductor pillar structures may be used to provide mechanical support to the alternating stack during formation of the source-level cavity. A source-level semiconductor material layer can be formed in the source-level cavity. The source-level semiconductor material layer adjoins bottom end portions of the vertical semiconductor channels and laterally surrounds the semiconductor pillar structures.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: October 6, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Mitsuteru Mushiga, Kenji Sugiura, Akio Nishida
  • Patent number: 10796986
    Abstract: A semiconductor device includes a leadframe, a semiconductor die attached to the leadframe, and an encapsulation material encapsulating the semiconductor die and a portion of the leadframe. The leadframe includes a first main face and a second main face opposite to the first main face. The leadframe includes leads wherein each lead includes a fully plated end face extending between an unplated first sidewall and an unplated second sidewall opposite to the first sidewall. The end face and the first and second sidewalls of each lead are perpendicular to the first and second main faces.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: October 6, 2020
    Assignee: Infineon Technologies AG
    Inventors: Stefan Macheiner, Markus Dinkel
  • Patent number: 10797171
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a laterally diffused MOSFET (LDMOS) and methods of manufacture. The structure includes: a gate structure having a drain region and a source region; and an oxidation extending from the gate structure to the drain region of the gate structure, the oxidation comprising a thinner oxide portion and a thicker oxide portion.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: October 6, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventor: Guowei Zhang
  • Patent number: 10797207
    Abstract: Light emitting devices (LEDs) are described. An LED includes a light emitting semiconductor structure that includes a light emitting active layer disposed between an n-layer and a p-layer. A wavelength converting material may be disposed adjacent the light emitting semiconductor structure. The wavelength converting material includes multiple pores, at least one of which contains a second material. An absolute value of a ratio of a coefficient of thermal expansion of the second material to a coefficient of thermal expansion of the wavelength converting material is at least two in an embodiment, at least ten in another embodiment, at least 100 in another embodiment, and at least 1,000 in yet another embodiment.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: October 6, 2020
    Assignee: LUMILEDS LLC
    Inventors: Daniel Estrada, Marcel Rene Bohmer, Jacobus Johannes Francisus Gerardus Heuts, Kentaro Shimizu, Michael David Camras
  • Patent number: 10797143
    Abstract: Semiconductor devices and methods of forming the same are provided. Semiconductor devices may include a plurality of gate electrodes that are stacked on a substrate and are spaced apart from each other in a vertical direction and a channel region extending through the plurality of gate electrodes in the vertical direction. Each of the plurality of gate electrodes may include a first conductive layer defining a recess recessed toward the channel region, and a second conductive layer in the recess defined by the first conductive layer. A first concentration of impurities in the second conductive layer may be higher than a second concentration of the impurities in the first conductive layer, and the impurities may include nitrogen (N).
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: October 6, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Keun Lee, Jeong Gil Lee, Do Hyung Kim, Ki Hyun Yoon, Hyun Seok Lim
  • Patent number: 10790447
    Abstract: A mask for thin film deposition of a display apparatus having both end portions coupleable to a frame in a state of tension in a lengthwise direction thereof, the mask including: a first portion having a first thickness and a plurality of pattern holes through which a deposition material may pass; a second portion comprising a welding portion having a second thickness configured to be coupled to a frame; and a third portion connecting the first portion and the third portion, wherein the first thickness is less than the second thickness, and the third portion includes an inclined surface connecting the first portion and the second portion.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: September 29, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Youngmin Moon, Sungsoon Im, Jeongkuk Kim, Minho Moon, Kyuhwan Hwang
  • Patent number: 10790339
    Abstract: Provided are an OLED array substrate and a manufacturing method thereof, and a display device. The OLED array substrate includes a substrate and a plurality of pixel units provided thereon. The plurality of pixel units are arranged into a plurality of rows extending in a first direction and a plurality of columns extending in a second direction. Each pixel unit includes a plurality of subpixels emitting light of different colors. At least two subpixels emitting light of the same color are adjacent to each other in at least one of the first direction and the second direction.
    Type: Grant
    Filed: February 24, 2018
    Date of Patent: September 29, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Zhongying Yang, Jianpeng Wu, Yinan Liang
  • Patent number: 10790467
    Abstract: A display device includes a base substrate, a first transistor, a second transistor, an organic light emitting diode, and a capacitor electrically connected to the first thin film transistor. The first transistor includes a first semiconductor pattern below a first interlayer insulation layer and a first control electrode above the first interlayer insulation layer and below a second interlayer insulation layer. The second transistor includes a second control electrode above the first interlayer insulation layer and below the second interlayer insulation layer. A second semiconductor pattern is above the second interlayer insulation layer.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: September 29, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jaybum Kim, Eoksu Kim, Kyoungseok Son, Junhyung Lim, Jihun Lim
  • Patent number: 10790267
    Abstract: A light emitting element is disclosed. The light emitting element includes: a mount substrate on which a first electrode pad, a second electrode pad, a third electrode pad, and a fourth electrode pad are disposed; a first vertical LED chip mounted on the mount substrate such that the bottom portion of the first vertical LED chip is connected to the first electrode pad; a second vertical LED chip mounted on the mount substrate such that the bottom portion of the second vertical LED chip is connected to the second electrode pad; a third vertical LED chip mounted on the mount substrate such that the bottom portion of the third vertical LED chip is connected to the third electrode pad; a light-transmitting conductive plate electrically connected to the top portions of the first vertical LED chip, the second vertical LED chip, and the third vertical LED chip; and a conductor connecting the light-transmitting conductive plate to the fourth electrode pad.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: September 29, 2020
    Assignee: LUMENS CO., LTD.
    Inventors: Taekyung Yoo, Seunghyun Oh, Sungsik Jo, Minpyo Kim, Jiyu Shin, Daewon Kim
  • Patent number: 10790194
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first plurality of conductive interconnect layers arranged within a first inter-level dielectric (ILD) structure disposed on a first surface of a first substrate. A second plurality of conductive interconnect layers are arranged within a second ILD structure disposed on a first surface of a second substrate. The second substrate is separated from the first substrate by the first ILD structure. The first plurality of conductive interconnect layers and the second plurality of conductive interconnect layers define an inductor having one or more turns.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: September 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Han Huang, Ching-Chun Wang, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu, Min-Feng Kao