Patents Examined by Zandra V. Smith
  • Patent number: 10354977
    Abstract: A device includes a wiring substrate. A first semiconductor-chip has a first face, a second face, and a first side face between an outer edge of the first face and an outer edge of the second face, where the first side face is a first condition plane. The first semiconductor-chip is located above the wiring substrate. A second semiconductor-chip has a third face, a fourth face, a second side face between an outer edge of the third face and an outer edge of the fourth face, and a through electrode passing through at least a semiconductor substrate between the third face and the fourth face. The second side face is the first condition plane and a second condition plane having more irregularities than the first condition plane. The second semiconductor-chip is located between the wiring substrate and the first semiconductor-chip. The resin is located around the first and second semiconductor-chips.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: July 16, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Soichi Homma, Masatoshi Fukuda
  • Patent number: 10355039
    Abstract: To improve the joining strength between semiconductor chips. In a semiconductor device, a first semiconductor chip includes a first joining surface including a first insulating layer, a plurality of first pads to which a first inner layer circuit insulated by the first insulating layer is electrically connected, and a linear first metal layer arranged on an outside of the plurality of first pads. A second semiconductor chip includes a second joining surface joined to the first joining surface, the second joining surface including a second insulating layer, a plurality of second pads that are arranged in positions facing the first pads and to which a second inner layer circuit insulated by the second insulating layer is electrically connected, and a linear second metal layer arranged in a position facing the first metal layer.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: July 16, 2019
    Assignee: Sony Corporation
    Inventors: Kengo Kotoo, Kaoru Koike
  • Patent number: 10354877
    Abstract: Ion implantation processes and systems are described, in which carbon dopant source materials are utilized to effect carbon doping. Various gas mixtures are described, including a carbon dopant source material, as well as co-flow combinations of gases for such carbon doping. Provision of in situ cleaning agents in the carbon dopant source material is described, as well as specific combinations of carbon dopant source gases, hydride gases, fluoride gases, noble gases, oxide gases and other gases.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: July 16, 2019
    Assignee: Entegris, Inc.
    Inventors: Oleg Byl, Edward A. Sturm, Ying Tang, Sharad N. Yedave, Joseph D. Sweeney, Steven G. Sergi, Barry Lewis Chambers
  • Patent number: 10355169
    Abstract: Disclosed is a substrate structure and a method for forming the same, in which a high-quality nitride semiconductor layer may be formed with a reduced stress applied to the nitride semiconductor layer at the growth of the nitride semiconductor layer and also be easily separated from the substrate, and a semiconductor lamination structure using the same and a method for forming the same, and a method for manufacturing a nitride semiconductor using the same. The substrate structure includes a single-crystal substrate heterogeneous from a nitride semiconductor, and a crystallized inorganic thin film having a leg portion configured to contact the substrate to define an integrated cavity between the leg portion and the substrate and an upper surface extending from the leg portion and parallel to the substrate, the crystallized inorganic thin film having the same crystal structure as the substrate.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: July 16, 2019
    Assignee: Hexasolution Co., Ltd.
    Inventors: Duk-Kyu Bae, Young-Boo Moon, Yongjo Park
  • Patent number: 10355174
    Abstract: A component includes a carrier and a semiconductor body arranged on the carrier, wherein the semiconductor body has an active layer arranged between the first and second semiconductor layers and is configured to generate, during operation of the component, an electromagnetic radiation that can be coupled out from the component through a first main surface, the first main surface of the component has an electrical contact layer configured to electrically contact a first semiconductor layer and in a plan view the carrier covers the first main surface in places, and in direct vicinity of the electrical contact layer the component includes a shielding structure configured to prevent electromagnetic radiation generated by the active layer from impinging onto the contact layer.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: July 16, 2019
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Markus Maute, Lutz Höppel, Jürgen Moosburger, Thomas Schwarz, Matthias Sabathil, Ralph Wirth, Alexander Linkov, Johannes Baur
  • Patent number: 10354878
    Abstract: A doping method for a semiconductor device including the following steps is provided. A substrate is provided. The substrate has a channel region. The channel region includes a first edge region, a second edge region and a center region in a channel width direction substantially perpendicular to a channel length direction, and the center region is located between the first edge region and the second edge region. A first doping process is performed on the first edge region, the second edge region and the center region by using a first conductive type dopant. A second doping process is performed on the center region by using a second conductive type dopant.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: July 16, 2019
    Assignee: United Microelectronics Corp.
    Inventors: Kai-Kuen Chang, Shih-Yin Hsiao
  • Patent number: 10354913
    Abstract: A method of forming a semiconductor device includes forming a conductive feature in a first dielectric layer, forming one or more dielectric layers over the first dielectric layer, and forming a via opening in the one or more dielectric layers, a bottom of the via opening exposing the conductive feature. The method further includes cleaning the via opening using a chemical mixture, and rinsing the via opening using basic-ion doped water after cleaning the via opening.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: July 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Nai-Chia Chen, Chun-Li Chou, Yen-Chiu Kuo, Chun-Hung Chao, Yu-Li Cheng
  • Patent number: 10347735
    Abstract: A semiconductor device includes a semiconductor substrate, a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a first semiconductor region of the first conductivity type, a second semiconductor region of the second conductivity type, a gate insulating film, and a gate electrode. The semiconductor device further includes, in a region of the first semiconductor layer across or adjacent to a p-n junction therein that does not overlap the second semiconductor region in a plan view except lateral edges thereof, a lifetime killer region having lifetime killers implanted therein.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: July 9, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Keishirou Kumada, Yuichi Hashizume, Yasuyuki Hoshi
  • Patent number: 10347741
    Abstract: Embodiments disclosed herein relate generally to forming a gate layer in high aspect ratio trenches using a cyclic deposition-etch process. In an embodiment, a method for semiconductor processing is provided. The method includes performing a cyclic deposition-etch process to form a conformal film over a bottom surface and along sidewall surfaces of a feature on a substrate. The method includes reflowing the conformal film. The method includes forming a cap layer on the reflowed film. The method includes depositing a crystalline film on the cap layer. The method includes crystallizing the reflowed film and the cap layer after depositing the crystalline film.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: July 9, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Pin-Ju Liang, De-Wei Yu, Yi-Cheng Li, Chien-Hao Chen
  • Patent number: 10347467
    Abstract: In some examples, a method including depositing a functional layer over a substrate; depositing a granular layer over the functional layer, the granular layer including a first material defining a plurality of grains separated by a second material defining grain boundaries of the plurality of grains; removing the second material from the granular layer such that the plurality of grains of the granular layer define a hard mask layer on the functional layer; and removing, via reactive ion etching with a carrier gas, portions of the functional layer not masked by the hard mask layer, wherein the carrier gas comprises a gas with an atomic number less than an atomic number of argon.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: July 9, 2019
    Assignee: Regents of the University of Minnesota
    Inventors: Jian-Ping Wang, Patrick Quarterman, Jianxin Zhu
  • Patent number: 10347534
    Abstract: Embodiments are provided herein for separating integrated circuit (IC) device die of a wafer, the wafer having a front side with an active device region and a back side, the active device region having a plurality of active devices arranged in rows and columns and separated by cutting lanes, the method including: attaching the front side of the wafer onto a first dicing tape; forming a modification zone within each cutting lane through the back side of the wafer, wherein each modification zone has a first thickness near a corner of each active device and a second thickness near a center point of each active device, wherein the second thickness is less than the first thickness; and propagating cracks through each cutting lane to separate the plurality of active devices.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: July 9, 2019
    Assignee: NXP B.V.
    Inventors: Martin Lapke, Hartmut Buenning, Sascha Moeller, Guido Albermann, Michael Zernack, Leo M. Higgins, III
  • Patent number: 10347714
    Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type, an impurity region of a second conductivity type formed in a surface layer portion of the semiconductor layer, a terminal region of the second conductivity type that is formed in the surface layer portion of the semiconductor layer along a peripheral edge of the impurity region and that has a second conductivity type impurity concentration higher than a second conductivity type impurity concentration of the impurity region, and a surface electrode that is formed on the semiconductor layer and that has a connection portion connected to the impurity region and to the terminal region.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: July 9, 2019
    Assignee: ROHM CO., LTD.
    Inventor: Jun Takaoka
  • Patent number: 10347653
    Abstract: Provided herein a semiconductor device including a stack including conductive layers and insulating layers that are alternately stacked, and a slit insulating layer passing through the stack in a stacking direction, the slit 5 insulating layer including a first main pattern extending in a first direction, and a first protruding pattern protruding in a second direction crossing the first direction at an end of the first main pattern.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: July 9, 2019
    Assignee: SK hynix Inc.
    Inventors: Ki Hong Lee, Seung Ho Pyi, Seok Min Jeon
  • Patent number: 10340472
    Abstract: A display device includes a base substrate, a first transistor, a second transistor, an organic light emitting diode, and a capacitor electrically connected to the first thin film transistor. The first transistor includes a first semiconductor pattern below a first interlayer insulation layer and a first control electrode above the first interlayer insulation layer and below a second interlayer insulation layer. The second transistor includes a second control electrode above the first interlayer insulation layer and below the second interlayer insulation layer. A second semiconductor pattern is above the second interlayer insulation layer.
    Type: Grant
    Filed: July 24, 2017
    Date of Patent: July 2, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jaybum Kim, Eoksu Kim, Kyoungseok Son, Junhyung Lim, Jihun Lim
  • Patent number: 10340177
    Abstract: Intermediate semiconductor devices and methods of reducing damage during back end of the line (BEOL) metallization and metal one (M1) layer integration scheme are provided. One method includes, for instance: obtaining a wafer having at least one contact region; depositing on the wafer a thin film stack having at least one layer of amorphous silicon (a-Si); performing lithography to pattern at least one opening; performing lithography to pattern at least one via opening and at least one trench opening; and removing the at least one a-Si layer. One intermediate semiconductor device includes, for instance: a wafer having at least one contact region; at least one first dielectric layer on the device; at least one second dielectric layer on the at least one first dielectric layer; and at least one a-Si layer on the at least one second dielectric layer.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: July 2, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ashwini Chandrashekar, Anbu Selvam Km Mahalingam, Craig Michael Child, Jr.
  • Patent number: 10332995
    Abstract: Semiconductor devices and methods of forming the same include forming semiconductor fins on a semiconductor substrate. A bottom source/drain region is formed in the semiconductor substrate. First charged dielectric spacers are formed on sidewalls of the semiconductor fins. A gate stack is formed over the bottom source/drain region. Second charged dielectric spacers are formed on sidewalls of the fin above the gate stack. The fins are recessed to a height below a top level of the second charged dielectric spacers. A top source/drain region is grown from the recessed fins.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: June 25, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Peng Xu, Chun W. Yeung, Chen Zhang
  • Patent number: 10329657
    Abstract: The invention to which this application relates is improvements to the provision of Molybdenum and/or Tungsten containing coatings of the type which can be used to improve certain characteristics of the surface of a substrate to which the coating is applied. In one embodiment the coating also includes Ti to provide the advantages of high adhesion, high humidity and wear resistance of the coating and TiB2 to promote the formation of a relatively uniform, dense, coating, so strengthening the coating which is formed and improving the high temperature performance of the coatings.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: June 25, 2019
    Assignee: Teer Coatings Limited
    Inventors: Xiaoling Zhang, Kevin Cooke
  • Patent number: 10332956
    Abstract: A semiconductor structure that includes a resistor that is located within an interconnect dielectric material layer of an interconnect level is provided. The resistor includes a diffusion barrier material that is present at a bottom of a feature that is located in the interconnect dielectric material layer. In some embodiments, the resistor has a topmost surface that is located entirely beneath a topmost surface of the interconnect dielectric material layer. In such an embodiment, the resistor is provided by removing sidewall portions of a diffusion barrier liner that surrounds a metal-containing structure. The removal of the sidewall portions of the diffusion barrier liner reduces the parasitic noise that is contributed to the sidewall portions of a resistor that includes such a diffusion barrier liner. Improved precision can also be obtained since sidewall portions may have a high thickness variation which may adversely affect the resistor's precision.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: June 25, 2019
    Assignee: International Business Machines Corporation
    Inventors: Baozhen Li, Kirk Peterson, John Sheets, Lawrence A. Clevenger, Junli Wang, Chih-Chao Yang
  • Patent number: 10325775
    Abstract: A semiconductor memory device includes a semiconductor layer including a memory cell region; a memory cell array including a plurality of first gate electrode layers stacked over the semiconductor layer, and disposed in the memory cell region; and a capacitor circuit disposed over the semiconductor layer outside the memory cell region. The capacitor circuit includes a plurality of gate structural bodies each including second gate electrode layers stacked over the semiconductor layer, and arranged along a first direction; a plurality of electrodes disposed between the gate structural bodies; and dielectric layers interposed between the gate structural bodies and the electrodes.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: June 18, 2019
    Assignee: SK hynix Inc.
    Inventors: Sang-Hyun Sung, Jeong-Hwan Kim, Jin-Ho Kim
  • Patent number: 10326057
    Abstract: A light emitting device package includes a package frame in which a recessed portion is defined in a center thereof, the package frame including, an interior wall surrounding the recessed portion, a step portion contacting the interior wall and a bottom surface of the recessed portion, a light source disposed inside the recessed portion and emitting first light, a substrate disposed on the light source, and fixed on an upper surface of the step portion and spaced apart from the light source, a light conversion layer disposed on the substrate and including quantum dots that absorbs the first light and emits second light having a different wavelength from the first light, and barrier layer at least covering the light conversion layer, where barrier layer includes a first inorganic barrier layer and a first organic barrier layer.
    Type: Grant
    Filed: January 6, 2018
    Date of Patent: June 18, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tae Hyung Kim, Chul Hee Yoo, Hyun A Kang, Jung Woo Lee, Jeong Hee Lee, Eun Joo Jang