Patents Examined by Zeev Kitov
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Patent number: 7327549Abstract: An apparatus for impact with a target includes electrodes deployed after contact is made between the apparatus and the target. Spacing of deployed electrodes may be more accurate and/or more repeatable for more effective delivery of an immobilizing stimulus signal.Type: GrantFiled: July 12, 2006Date of Patent: February 5, 2008Assignee: TASER International, Inc.Inventors: Patrick W. Smith, Magne H. Nerheim
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Patent number: 7319574Abstract: A non-invasive underground arc fault detection apparatus is for an underground electrical conductor. The apparatus includes an electric circuit having an opening for admitting the electrical conductor therethrough. The electric circuit includes one or two transducers adapted to output a first signal representative of current flowing in the electrical conductor and a second signal. An arc fault detection circuit cooperates with the electric circuit to output a third signal derived from the first signal. The third signal is representative of an arc fault of the electrical conductor. An audible annunciator cooperates with the arc fault detection circuit to annunciate the third signal. A power supply cooperates with the electric circuit and is adapted to power the arc fault detection circuit and the annunciator from the second signal.Type: GrantFiled: May 23, 2005Date of Patent: January 15, 2008Assignee: Eaton CorporationInventor: Joseph C. Engel
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Patent number: 7312972Abstract: An actuator driving circuit for driving an electromagnetic actuator, includes a boosting circuit which boosts a source voltage, and a boosted voltage controller which is connected to an output terminal of the boosting circuit, i.e., the downstream of the boosting circuit, to control a boosted voltage generated by the boosting circuit.Type: GrantFiled: April 25, 2005Date of Patent: December 25, 2007Assignee: Keihin CorporationInventors: Yasuharu Hourai, Kenichi Yoshimura
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Patent number: 7295412Abstract: A collector voltage of a power management semiconductor device is detected by a first comparator, and when the detected collector voltage exceeds a first reference voltage, the first comparator outputs a first detection signal. Furthermore, a gate voltage of the power management semiconductor device is detected by a second comparator, and when the detected gate voltage exceeds a second reference voltage, the second comparator outputs a second detection signal. The second reference voltage is a minimum gate voltage for feeding a rated power to the power management semiconductor device or over, and less than a line power voltage of a drive circuit of the power management semiconductor device. When both the first detection signal and second detection signal are being outputted, the gate voltage is reduced by a gate voltage reduction means so as to protect the power management semiconductor device from overcurrent and overvoltage.Type: GrantFiled: February 9, 2004Date of Patent: November 13, 2007Assignee: Hitachi, Ltd.Inventors: Masataka Sasaki, Katsumi Ishikawa, Ryuichi Saito, Koichi Suda, Katsuaki Takahashi
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Patent number: 7292421Abstract: Methods and circuits are disclosed for providing distributed ESD protection switchable between a capacitive decoupling state and an ESD protection state. The invention provides electronic circuitry with a selectable capacitive decoupling path and an ESD shunting path responsive to the detection of the presence or absence of an electrostatic discharge event. Circuits of the invention include one or more control circuits, electrostatic discharge devices, and control nodes operably coupled to responsively switch the circuit from a decoupling state to an electrostatic discharge state.Type: GrantFiled: November 12, 2004Date of Patent: November 6, 2007Assignee: Texas Instruments IncorporatedInventor: Jeremy Charles Smith
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Patent number: 7280340Abstract: Systems and methods for immobilizing a target such as a human or animal with a stimulus signal coupled to the target via electrodes provide the stimulus signal in accordance with a strike stage, a hold stage, and a rest stage. Systems include a launch device and separate projectile, where the projectile includes a battery, a waveform generator, and electrodes. The strike stage and hold stage may include pulses at a pulse repetition rate, for example, from 10 to 20 pulses per second, each pulse delivering a predetermined amount of charge, for example, about 100 microcoulombs at less than about 500 volts peak. The hold stage may continue immobilization at a lesser expenditure of energy compared to the strike stage. Because the strike stage and hold stage may immobilize by interfering with skeletal muscle control by the target's nervous system, a rest stage may allow the target to take a breath.Type: GrantFiled: December 31, 2003Date of Patent: October 9, 2007Assignee: TASER International, Inc.Inventors: Patrick W. Smith, Magne H. Nerheim
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Patent number: 7280327Abstract: A mechanism for preventing ESD damage and LCD panel utilizing the same. The mechanism for preventing ESD damage is configured to make ESD protection devices. The provided ESD protection devices corresponding to the longest fan-out signal lines of an integrated circuit have longer equivalent channel widths than those of the other ESD protection devices or smaller equivalent impedances than those of the other ESD protection devices, thereby discharging the electrostatic charge efficiently.Type: GrantFiled: February 20, 2004Date of Patent: October 9, 2007Assignee: Au Optronics Corp.Inventor: Han-Chung Lai
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Patent number: 7256974Abstract: A system for isolating electrical ground faults and secondary failures in an electrical system, the system comprising an AC ground isolation state machine for detecting and isolating an AC ground, a DC ground isolation state machine for detecting and isolating a DC ground, a component failure isolation state machine for detecting and isolating a change in a resistance, and a component failure early detection algorithm for determining a failure before using the state machines.Type: GrantFiled: April 11, 2006Date of Patent: August 14, 2007Assignee: General Electric CompanyInventors: Christopher Wade McNally, Ajith K. Kumar, Bret Dwayne Worden
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Patent number: 7245465Abstract: A voltage regulator has an output circuit for producing from an input voltage a predetermined output voltage to be supplied to a load, an overcurrent protection circuit for preventing overcurrent in the output circuit, a memory for storing control information fed from outside, and an adjustment circuit for adjusting the level at which the overcurrent protection circuit detects overcurrent according to the control information read from the memory. With this configuration, it is possible to accurately detect overcurrent by canceling factors such as individual variations in the characteristics of the circuit components, the influence of stress occurring when the regulator IC is packaged, and fabrication-associated variations in the load.Type: GrantFiled: December 3, 2002Date of Patent: July 17, 2007Assignee: Rohm Co., Ltd.Inventor: Takahiro Hikita
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Patent number: 7233464Abstract: A ground fault detection system is provided where one current sensor is used to calibrate a second sensor in order to provide automatic zeroing of the difference measurement. The calibration is done gradually in order to differentiate between sensor drift and a transition in current due to a differential fault.Type: GrantFiled: January 9, 2004Date of Patent: June 19, 2007Assignee: Goodrich CorporationInventor: Kevin Edward Rice
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Patent number: 7224565Abstract: A control circuit that drives an electronic actuator. The control circuit includes a direct voltage source, a chopper circuit arranged between the source and an electric actuator, and an electronic control circuit designed to apply to the chopper circuit a command signal of the PWM type, with a predefined ON/OFF switching period and a predetermined duty cycle, for a predefined activation time, to produce a flow, within the electric actuator, of a correspondingly switched current having a nominal duration corresponding to the activation time. The control circuit detects the last whole or complete switching period included within the activation time, splits, in accordance with a predefined duty cycle, the final interval including the last complete switching period and any subsequent fraction of a switching period included within the activation time, and drives the chopper circuit in this final interval.Type: GrantFiled: October 4, 2004Date of Patent: May 29, 2007Assignee: C.R.F. Societa Consortile per AzioniInventors: Eugenio Faggioli, Renato Zenzon
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Patent number: 7203046Abstract: An overcurrent detecting device for detecting an overcurrent in a load circuit, includes a DC power supply, a load, a semiconductor switch that controls ON/OFF of the load, a driver circuit that outputs a driving signal to the semiconductor switch, a reference voltage generating circuit that generates a reference voltage from the DC power supply, a voltage drop generating circuit that includes a resistor for generating a voltage drop and generates a voltage drop in the resistor for generating a voltage drop, a decision voltage generating circuit that generates, as a decision voltage, a voltage corresponding to a voltage obtained by adding a voltage drop generated when the semiconductor switch is turned ON and a voltage drop generated in the resistor for generating a voltage drop, and a comparing circuit that compares the decision voltage with the reference voltage and outputs a disconnecting command signal of the semiconductor switch to the driver circuit when the decision voltage is greater than the referencType: GrantFiled: December 28, 2005Date of Patent: April 10, 2007Assignee: Yazaki CorporationInventor: Shunzou Ohshima
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Patent number: 7203049Abstract: The over-current protection device of the present invention uses the unbalanced properties of the thermal expansion coefficients between the outer and inner sides for an upper metallic conductive sheet and a lower metallic conductive sheet to generate a torque to deform outwardly. The torque is used to pull a current-sensing element and present with at least a cracking face, so as to introduce an electrically open effect similar to a fuse. Thus, the present invention can achieve the object for preventing the danger of circuit system by the short circuit during the burning of over-current protection device.Type: GrantFiled: September 8, 2004Date of Patent: April 10, 2007Assignee: Polytronics Technology CorporationInventors: Edward Fu-Hua Chu, David Shau-Chew Wang, Yun-Ching Ma
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Patent number: 7196890Abstract: Electrostatic discharge protection circuitry includes a timing circuit operably coupled between the high supply side and low supply side of an associated circuit. The timing circuit has an RC node used for triggering a series of inverters configured to control an ESD dissipation device operably coupled to the high supply side node and the low side supply node of the circuit. A feedback transistor network and a feedback conditioning network is provided for ensuring that the ESD device is held on during an ESD event.Type: GrantFiled: November 12, 2004Date of Patent: March 27, 2007Assignee: Texas Instruments IncorporatedInventor: Jeremy Charles Smith
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Patent number: 7161780Abstract: A typical duplex GFCI receptacles has two buttons, a test button that, when pressed, shuts off power to the receptacle and down stream devices, and a reset button that, when pressed, restores power to the GFCI and down stream devices. Generally, the test button is pressed to verify that the GFCI will interrupt power to the conductive paths and the reset button is pressed to reset the GFCI. In operation, the test portion of the GFCI will automatically break electrical continuity in one or more conductive paths (i.e., open the conductive path) between line and load sides upon the detection of a fault such as a reverse wiring condition, a ground fault, an open neutral and/or a defective GFCI device. When this happens the reset button in the typical GFCI receptacle is then pressed in an to attempt to restore power. The GFCI here disclosed has only one button which is used for both the test and reset operation.Type: GrantFiled: January 20, 2004Date of Patent: January 9, 2007Assignee: Leviton Manufacturing Co., Inc.Inventors: Frantz Germain, Stephen Stewart
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Patent number: 7154719Abstract: A circuit providing protection against electrostatic discharge (ESD) for internal elements of an Integrated Circuit (IC). In one example, a protection circuit comprises a PMOSFET resistor (R) having a gate connected to a ground rail (VSS), a drain connected to an input node (ESD_RC) of an inverter (INV), a source and a bulk of the PMOSFET resistor (R) being connected to a power rail (VDD). The circuit also comprises an NMOSFET capacitor (C1) having a gate connected to the input node (ESD_RC) of the inverter (INV), a drain, a source and a bulk of the NMOSFET capacitor (C1) being connected to the ground rail (VSS). The circuit also includes a PMOSFET capacitor (C2) having a gate connected to the input node (ESD_RC) of the inverter (INV). A drain and a source of the PMOSFET capacitor (C2) being connected to the ground rail (VSS), and a bulk of the PMOSFET capacitor (C2) is connected to the power rail (VDD).Type: GrantFiled: March 22, 2002Date of Patent: December 26, 2006Assignee: Freescale Semiconductor, Inc.Inventor: Alexander Krasin
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Patent number: 7154722Abstract: The invention contemplates a technique for providing loop control on a faulted overhead or underground loop system, while preventing restored current from being fed or back fed into the fault. In particular, the invention provides a method, device, and system for restoring power to a faulted loop distribution system. The inventive method includes detecting a fault on the loop distribution system, interrupting current on the faulted part of the loop distribution system, isolating the faulted part of the loop distribution system from an unfaulted part of the loop distribution system, restoring current to the unfaulted part of the loop distribution system, and preventing the current from flowing to the faulted part of the loop distribution system. The method may further include providing the current to a load.Type: GrantFiled: September 5, 2001Date of Patent: December 26, 2006Assignee: ABB Technology AGInventors: James D. Stoupis, Marina V. Graham, Gregory J. Grote
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Patent number: 7145758Abstract: A circuit to suppress arc across contacts of a relay is provided, in which the relay is electrically coupled to a power supply and a load. The circuit includes an arc suppression circuit electrically coupled between the first and second contacts of the relay, and the arc suppression circuit includes a capacitor and a switch, both of which are electrically coupled to the first and second contacts of the relay, in which the switch is configured to turn on when the first and second contacts of the relay change state, thereby providing an alternate path for a current flow through the load.Type: GrantFiled: May 19, 2003Date of Patent: December 5, 2006Assignee: International Rectifier CorporationInventors: Ray King, Lyle Bryan
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Patent number: 7145757Abstract: A shorting system, which eliminates persistent arcing faults in power distribution equipment, includes a first shorting switch having separable contacts, an actuation input and a fuse electrically connected in series with those contacts. A second shorting switch includes an actuation input and separable contacts, which are electrically connected in parallel with the series combination of the fuse and the first shorting switch contacts. A detection circuit includes one or more arcing light sensors and an actuation circuit. The light sensors detect arcing fault light and the actuation circuit responsively outputs a first trigger signal to the first shorting switch actuation input to close its contacts. For a persistent arcing fault, which is not eliminated by the first shorting switch, a predetermined time after the first trigger signal, the actuation circuit responsively outputs a second trigger signal to the second shorting switch actuation input to close its contacts.Type: GrantFiled: January 13, 2004Date of Patent: December 5, 2006Assignee: Eaton CorporationInventors: John J. Shea, Robert N. Parry
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Patent number: 7142404Abstract: A domain power notification system detects when a power domain experiences a power condition, such as lost power and low-voltage power, and communicates that information to the domains that communicate with the problem domain. As a result, the effected domains stop communicating with the problem domain without passing erroneous information.Type: GrantFiled: June 9, 2004Date of Patent: November 28, 2006Assignee: Advanced Micro Devices, Inc.Inventors: Simon Bikulcius, Mark A. Landguth