Abstract: An example controller for use in a power supply in accordance with the present teachings includes a drive signal generator, a jitter signal generator and a compensator signal generator. The drive signal generator is coupled to output a drive signal having a switching period and a duty ratio to control switching of a switch that is to be coupled to the controller. The jitter signal generator is coupled to provide a jitter signal, where the switching period of the drive signal varies in response to the jitter signal. The compensator signal generator is coupled to provide a compensator signal responsive to the jitter signal, where the duty ratio of the drive signal is varied in response to the compensator signal.

Abstract: A resonant, bi-directional, DC to DC voltage converter with loss-less (soft) switching having regulated output and capable of converting power between two, high-potential and low-potential DC voltage sources. The converter's semiconductor and magnetic components provide both, output regulation and soft switching in both (step-down and step-up) directions of power conversion which reduces total component count, cost and volume and enhances power conversion efficiency.

Abstract: A power converter is provided, which may include_a transformer having primary and secondary windings; a primary side switching bridge arrangement including at least two switches switcheable at a switching frequency to drive the primary winding of said transformer, said primary side switching bridge arrangement including at least one decoupling capacitor; and a secondary side rectifying and filtering stage coupled to the secondary winding of said transformer, wherein said secondary side rectifying and filtering stage includes a current doubler with at least one inductor, wherein said at least one decoupling capacitor and said at least one inductor in said current doubler comprise a resonant tank circuit having a resonant frequency range encompassing said switching frequency, whereby said converter exhibits a gain defined by the position of said switching frequency within said resonant frequency range.

Abstract: Embodiments of the present invention provide novel techniques for using multiple 18-pulse rectifier circuits in parallel. In particular, each rectifier circuit may include an autotransformer having 15 inductors coupled in series, joined by 15 nodes interposed between pairs of the inductors. The inductors may be represented as a hexagon in which alternating sides of the hexagon have two and three inductors, respectively. Each rectifier circuit may also include three inputs for three-phase AC power coupled to alternating vertices of the hexagonal representation and nine outputs for AC power coupled between each node that is not a vertex of the hexagonal representation and a respective diode bridge. Outputs of the diode bridges for the rectifier circuits may be coupled to a DC bus. In addition, a means for reducing circulating current between the parallel rectifier circuits and for promoting load sharing between the parallel rectifier circuits is also provided.

Abstract: A semiconductor device providing a control circuit for controlling a switching power supply apparatus includes: an intermittent-oscillation control circuit which outputs an enable signal providing instructions to execute and suspend switching alternately; a turn-on control circuit which changes between an execution state and a suspension state of the switching according to the enable signal, and outputs, only in the execution state, a turn-on signal which turns on the switching element with a switching period; and an intermittent-oscillation frequency control circuit which causes the turn-on control circuit to delay the changing between the execution state and the suspension state so that an intermittence period including periods during which the turn-on control circuit is in the execution state and the turn-on control circuit is in the suspension state falls outside of a specific time range. Intermittent oscillation is thus operated out of a specific frequency band within an audible frequency range.

Abstract: A multiphase DC/DC converter according to the present invention includes: a plurality of DC/DC converters whose outputs are connected in common to supply electric power to a load; a load state detection portion which detects a state of the load connected to the plurality of DC/DC converters and outputs a detection result; and a control circuit which drives each of the plurality of DC/DC converters based on outputs from the plurality of DC/DC converters, and based on an output from the load state detection portion, drives the plurality of DC/DC converters with output phases of the plurality of DC/DC converters deviated from each other or with the output phases of the plurality of DC/DC converters aligned with each other.

Abstract: A method and system control the adding or dropping of phases in a multiphase voltage regulator. The regulator has an efficiency and this efficiency of the regulator is calculated for a given number of phases being activated from an output voltage, input voltage, output current, and duty cycle of the regulator. The efficiency of the regulator is also calculated if a phase is added using the derivative of the duty cycle as a function of the output current. The efficiency of the regulator is further calculated if a phase is dropped using the derivative of the duty cycle as a function of the output current. From these operations of calculating, a phase is either added, dropped, or the phase is maintained at its current value to thereby optimize the efficiency of the regulator.

Abstract: The invention relates to a circuit arrangement for producing an alternating voltage or an alternating current from a unipolar direct current source having an inverter relating to a neutral conductor. The direct current source is connected to an inverter which converts the unipolar voltage of the direct current source into a bipolar intermediate circuit voltage that is stored in a buffer circuit (C1, C2) which is connected to the inverter. The inverter comprises a clocked switch (So) and an energy converting unit which is configured as a dual coil (DR1,DR2) having two windings (W1,W2) which are closely coupled to each other.

Abstract: A power supply controller is disclosed. An example power supply controller includes an input voltage sense input coupled to sense an input voltage sense signal representative of an input voltage of a power supply. An output voltage sense input is coupled to sense an output voltage sense signal representative of an output voltage of the power supply. A current limit circuit is coupled to generate a current limit signal. The current limit signal is varied relative to a first ratio representative of a ratio of a product of the input voltage and a scaled output voltage of the power supply, to a sum of the input voltage and the scaled output voltage of the power supply. A drive signal generator is coupled to generate a drive signal in response to the current limit signal to drive the power switch of the power supply to limit an output power of the power supply in response to the input voltage.

Abstract: A digital signal processing circuit which performs average current control is disposed on a secondary side of a transformer of an isolated DC-DC converter, and a switching control signal output from the digital signal processing circuit is transmitted to a switching element included in a power factor correction converter through an isolated drive circuit. The digital signal processing circuit obtains an average value of currents supplied to an inductor in accordance with a voltage output from a bias winding of the inductor or an output from a secondary side of a current transformer which detects a drain current of the switching element. Furthermore, the average value of the currents corresponds to a waveform (full-wave rectification sine wave) of an input voltage Vi.

Abstract: A standby power supply circuit includes a pulse width modulation controller, first to fourth metal-oxide-semiconductor field effect transistors (MOSFETs), and an inductor. A gate of the first MOSFET and a gate of the second MOSFET are connected to a first and a second general purpose terminals of a power management chip, respectively. A drain of the first MOSFET is connected to a source of the third MOSFET. A gate of the fourth MOSFET is connected to a lower gate terminal of the controller. A phase terminal of the controller is grounded via the inductor and a capacitor in series. The drain of the second MOSFET is connected to a node between the inductor and the capacitor via a resistor.

Abstract: The present invention provides a method of controlling an interleaved power factor correction (PFC) circuit operating in a discontinuous conduction mode (DCM). The controller employs a normal mode of operation in which inductor currents in each PFC sub-circuit are estimated based on the monitored input voltage and monitored output voltage, and switching devices associated with each PFC sub-circuit are controlled to ensure DCM operation. As the input voltage increases, the OFF times of each PFC sub-circuit increase such that the inductor currents no longer overlap. In response, the controller activates a time-limiting mode (TLM) in which OFF time durations for each sub-circuit are based on the monitored sum of load currents as opposed to the monitored input voltage and monitored output voltage.

Abstract: According to one configuration, a multi-phase power supply adjusts a number of active phases based at least in part on a peak current supplied to a dynamic load. For example, a controller associated with the multi-phase power supply can monitor or receive a value indicative of a peak magnitude of current delivered by the multi-phase power supply to a dynamic load. The controller initiates comparison of the value to threshold information. Based at least in part on the comparison, the controller adjusts how many phases of the multi-phase power supply are activated to deliver the current delivered to the dynamic load. Thus, one embodiment herein is directed to controlling a multi-phase power supply based at least in part on a measured parameter such as peak current magnitude.

Abstract: Connection portions (225UP through 225WP) to which upper arm control terminals (320UU through 320UW) are connected are disposed at a first edge portion of a drive circuit board (22). And connection portions (225UN through 225WN to which lower arm control terminals (320LU through 320LW) are connected are disposed at a second edge portion of the drive circuit board (22). Upper arm implementation regions (227UP through 227WP), lower arm implementation regions (227UN through 227WN), and a low voltage pattern region (228) in which photo-couplers (221U through 221W) are implemented are formed in the board region between these board edge portions. And signal wiring (40U) that transmits a control signal from a photo-coupler (221U) to an implementation region (227UN) is formed in a conductor layer that is a lower layer than the conductor layer in the lower arm implementation region in which the lower arm driver circuit is implemented.

Abstract: A controller for a power supply includes a logic block and a time-to-frequency converter. The logic block is to generate a drive signal in response to a clock signal. The drive signal is to be coupled to control switching of a power switch of the power supply to regulate an output of the power supply. The time-to-frequency converter is coupled to the logic block and generates the clock signal having a frequency responsive to a time period of the drive signal.

Abstract: A power supply circuit includes a PWM controller, which is capable of providing pulse signals to the CPU, a temperature feedback circuit coupled to the PWM controller, and a temperature sensor. The temperature sensor is coupled to the temperature feedback circuit, the temperature sensor is located adjacent the CPU, and capable of detects a temperature of the CPU. The PWM controller is capable of adjusting the pulse signals to maintain the pulse signals stably when the temperature sensor detects the temperature of the CPU rising.

Abstract: A method includes generating a drive signal for a transistor in a switching regulator. The drive signal turns the transistor on and off to generate a regulated output voltage. The drive signal is generated based on a clock signal. The method also includes dynamically decreasing a frequency of the clock signal to decrease a dropout voltage of the switching regulator. Dynamically decreasing the frequency of the clock signal can increase a duration of switching periods defined by the clock signal. The dropout voltage could have a first value proportional to TOFF—MIN/TON—MAX during shorter switching periods and a second value proportional to TOFF—MIN/TON—MAX—DFC during longer switching periods. TOFF—MIN represents a minimum amount of off-time for the transistor during each switching period, TON—MAX represents a maximum amount of on-time for the transistor during shorter switching periods, and TON—MAX—DFC represent a maximum amount of on-time for the transistor during longer switching periods.

Abstract: A power adapter to receive at least one AC input power and transform to DC primary output power includes a power factor correction circuit to receive the AC input power and modulate to become a modulated power, an isolation voltage step-down circuit connecting to the power factor correction circuit to modulate the modulated power to a modulated lower voltage power, a switch voltage regulation circuit connecting to the isolation voltage step-down circuit to receive the modulated lower voltage power, and a voltage stabilization circuit connecting to the switch voltage regulation circuit. The switch voltage regulation circuit sets a determined output level and regulates the modulated lower voltage power to become a determined power at the determined output level. The voltage stabilization circuit modulates the determined power to become the primary output power and supplies the primary output power to a primary output end.

Abstract: A switch mode power supply (15) employs a rectifier (20), a converter (50) and converter driver (60). The rectifier (20) generates a rectified supply voltage (VRS) based on an in-line voltage (VLN), and the converter driver (60) generates one or more driving voltages (VDR) to facilitate a conversion by the converter (50) of the rectified supply voltage (VRS) to a DC bus voltage (VDC) based on the driving voltage(s) (VDR). The converter (50) may include a transient voltage suppression device (52) to suppress the rectified supply voltage (VRS) in response to an abnormal line condition of the switch mode power supply (15), and the converter driver (60) may include a free-oscillating suppression device (61) to suppress the one or more driving voltages (VDR) in response to a free-oscillating condition of the converter driver (60).

Abstract: A system includes an averaging module, a high pass filter module, a first estimation module, a sensing module, and a combining module. The averaging module receives an output voltage of a power supply and that generates an average output voltage. The high pass filter module receives an average switching voltage used to control switches in an output stage of the power supply and filters a difference between the average output voltage and the average switching voltage. The estimation module estimates a first filtered current through an inductor in the output stage based on an output of the high pass filter module. The sensing module senses voltage across the inductor and estimates a second current through the inductor. The low pass filter module filters the second current. The combining module combines the first filtered current and the second filtered current to generate an estimated current through the inductor.