Abstract: The present invention concerns a method for treating and/or preventing a disease in a subject comprising the step of administrating an effective amount of a compound of formula I to a subject in need thereof.

Abstract: A method for designing a photolithography mask and a light source may include designing an initial photolithography mask and an initial light source using an initial target pattern corresponding to a desired target pattern in a resist layer. The method may also include designing a new target pattern and designing a new photolithography mask and/or a new light source using the new target pattern.

Abstract: An electronic component package includes a support and heat conductor. The heat conductor has a protuberance and the support has a socket arranged to be able to receive the protuberance so that the movement of heat conductor relative to the support during the assembly process is reduced.

Abstract: A wireless unit includes a first motion sensitive device; communications circuitry for wirelessly communicating with a further wireless unit; and a processing device configured to compare at least one first motion vector received from the first motion sensitive device with at least one second motion vector received from a second motion sensitive device of the further wireless unit.

Abstract: An image sensor having improved dynamic range includes a signal that is read out for a selection of pixels which act as a calibration to govern the choice of exposure levels to be applied to the rest of the array. In this way, the sensor is operable to adapt to variations in scene intensity. The pixels in the array are vertically and horizontally addressed so as to enable accounted for small areas of intensity variation across an imaged scene.

Abstract: The disclosure relates to a method for detecting the presence of an object near a detection device, comprising: reverse biasing single photon avalanche photodiodes, at a bias voltage greater than a breakdown voltage of a PN junction of each photodiode, emitting pulses of an incident photon beam, detecting photodiodes which avalanche trigger after the reception by the photodiode of at least one photon of a reflected photon beam produced by a reflection of the incident beam on an object near the detection device, determining the object presence as a function of the existence of at least one avalanche triggering in one of the photodiodes, and selecting a number of photodiodes to be reverse biased in relation to the detection device, as a function of a load of a circuit for generating the bias voltage.

Abstract: A trench is formed in a semiconductor substrate by depositing an etch mask on the substrate having an opening, etching of the trench through the opening, and doping the walls of the trench. The etching step includes a first phase having an etch power set to etch the substrate under the etch mask, and a second phase having an etch power set smaller than the power of the first phase. Further, the doping of the walls of the trench is applied through the opening of the etch mask.

Abstract: A single-photon avalanche diode assembly, the diode including a central terminal and a peripheral terminal, the peripheral terminal being connected to an input of a comparator and to a first power supply terminal by a first resistor, the central terminal being connected by a conductive track to a second power supply terminal, a second resistor being arranged in series on said conductive track.

Abstract: A circuit includes a first n-bit communications block and a second m-bit communications block. A controller is configured to control mode of operation for the first and second communications blocks. In a first mode, the first and second communications blocks function as a single communications block for n+m bit communications. In a second mode, the first and second communications blocks operate as substantially independent communications block for n bit communications and m bit communications.

Abstract: A router includes a plurality of virtual networks, a plurality of output links, at least one decoder and arbitration circuitry. Each virtual network has a plurality of virtual network inputs and a plurality of virtual network outputs. Each virtual network output is associated with an output link. The decoder decodes a header of a data unit received on a virtual network of one of the virtual network inputs. The decoder generates a first request and a second request. The first request is for the allocation of a virtual network output of the virtual network to the virtual network input. The second request is for the allocation of an output link associated with the virtual network output to the virtual network output. The arbitration circuitry performs arbitration of the first request and arbitration of the second request in parallel.

Abstract: The present technology relates the use of a beta blocker for the manufacture of a medicament for the treatment of hemangiomas, for example of infantile hemangiomas. The beta blocker may be a non-selective beta-blocker, for example propranolol. The present technology provides an alternative to the known compounds, e.g. corticosteroids, interferon or vincristine, generally used for the treatment of hemangiomas.

Abstract: A fully differential operational amplifier includes a differential input stage, at least one output stage and a common-mode feedback circuit connected with the input stage. The differential input stage includes a differential pair of transistors and a bias circuit for the differential pair of transistors. A start-up circuit operates to detect an operating condition of the differential pair of transistors of the input stage and in response thereto turn on the bias circuit.

Abstract: A memory device includes first and second inverters cross-coupled between first and second nodes. The first inverter is configured to be supplied by a first supply voltage via a first transistor and the second inverter is configured to be supplied by the first supply voltage via a second transistor. A first control circuit is configured to control a gate node of the first transistor based on the voltage at the second node and at a gate node of the second transistor. A second control circuit is configured to control the gate node of the second transistor based on the voltage at the first node and at the gate node of the first transistor.

Abstract: The disclosure is directed to an interleaved analog-to-digital converter having: first, second and third sub-converters; a control block configured to control the first sub-converter to sample a test signal and the second sub-converter to sample an input signal during a first sampling period, and to control the second sub-converter to sample the test signal and the third sub-converter to sample the input signal during a second sampling period.

Abstract: A DMOS on SOI transistor including an elongated gate extending across the entire width of an active area; a drain region of a first conductivity type extending across the entire width of the active area; a source region of the first conductivity type extending parallel to the gate and stopping before the limit of the active area at least on one side of the transistor width, an interval existing between the limit of the source region and the limit of the active area; a bulk region of a second conductivity type extending under the gate and in said interval; a more heavily-doped region of the second conductivity type extending on a portion of said interval on the side of the limit of the active area; and an elongated source metallization extending across the entire width of the active area.

Abstract: The present disclosure includes calibration circuitry for adjusting the bandwidth of at least one sub-converter of an interleaved analog to digital converter (ADC), the at least one sub-converter having an input switch coupled to an input line of the ADC, the calibration circuitry having a control circuit adapted to adjust a bulk voltage of a transistor forming the input switch.

Abstract: A method for transmitting data on a configurable bus of z physical links, including receiving input data on an input bus at at least one of a plurality of data rates, selecting a number of physical links n, amongst the z physical links, on which data is to be transmitted, selecting a clock frequency f at which the data is to be transmitted on the configurable bus, wherein the selections of n and f are based on information concerning the at least one of the plurality of data rates, the number of links used on the input bus.

Abstract: A method for defining an insulating area in a semiconductor substrate, including a step of forming of a bonding layer on the walls and the bottom of a trench defined in the substrate. A step of passivation of the apparent surface of said bonding layer, at least close to the surface of said semiconductor substrate.

Abstract: A method for defining an insulator in a semiconductor substrate includes forming a trench in the substrate, forming in the trench an insulating material having its upper surface arranged above the surface of the substrate, and forming a diffusion barrier layer in a portion of the insulating material located above the surface of the semiconductor substrate. Such insulators can be used, for example, to insulate and delineate electronic components or portions of components formed in the substrate.

Abstract: A method for producing at least one deep trench isolation in a semiconductor substrate including silicon and having a front side may include forming at least one cavity in the semiconductor substrate from the front side. The method may include conformally depositing dopant atoms on walls of the cavity, and forming, in the vicinity of the walls of the cavity, a silicon region doped with the dopant atoms. The method may further include filling the cavity with a filler material to form the at least one deep trench isolation.