Abstract: A semiconductor chip package includes a substrate having a top surface and a bottom surface, and a semiconductor device mounted on the top surface of the substrate. A gap is provided between the semiconductor device and the top surface of the substrate. A multi-layer laminate epoxy sheet is disposed on the top surface of the substrate and around a perimeter of the semiconductor device.

Abstract: A memory device that includes a first memory cell, a second memory cell and a sense amplifier. The sense amplifier includes a first branch and a second branch and are configured to output a first voltage and a second voltage to the first memory and the second memory, respectively in a trimming operation. A first clamp device of the sense amplifier includes a first clamp transistor and a plurality of first trimming transistors that are coupled to the first clamp transistor in parallel. The gate terminals of the first clamp transistor and the plurality of first trimming transistors are biased by a fixed clamp voltage. Each of the plurality of first trimming transistors is selectively conducted to compensate a mismatch between the first voltage and the second voltage.

Abstract: A representative method for manufacturing a semiconductor device (e.g., a fin field-effect transistor) includes the steps of forming a gate structure having a first lateral width, and forming a first via opening over the gate structure. The first via opening has a lowermost portion that exposes an uppermost surface of the gate structure. The lowermost portion of the first via opening has a second lateral width. A ratio of the second lateral width to the first lateral width is less than about 1.1. A source/drain (S/D) region is disposed laterally adjacent the gate structure. A contact feature is disposed over the S/D region. A second via opening extends to and exposes an uppermost surface of the contact feature. A bottommost portion of the second via opening is disposed above a topmost portion of the gate structure.

Abstract: A low-dropout regulator including a first comparator, an edge trigger, a second comparator, a third comparator, and an output stage circuit is provided. The first comparator generates a first comparison signal according to a first reference signal and an output signal. The edge trigger outputs a trigger signal according to the first comparison signal, a second comparison signal, and a third comparison signal. The second comparator generates the second comparison signal according to the output signal and a second reference signal. The third comparator generates the third comparison signal according to the output signal and a third reference signal. The output stage circuit outputs the output signal according to the first comparison signal, the second comparison signal, and the third comparison signal. The output stage circuit includes a plurality of hysteresis controllers and a plurality of power transistors. Each hysteresis controller controls a conduction state of a corresponding power transistor.

Abstract: A semiconductor device includes a first semiconductor fin extending along a first direction. The semiconductor device includes a second semiconductor fin also extending along the first direction. The semiconductor device includes a dielectric fin disposed between the first and second semiconductor fins, wherein the dielectric fin also extends along the first direction. The semiconductor device includes a gate structure extending along a second direction perpendicular to the first direction, the gate structure comprising a first portion and a second portion. A top surface of the dielectric fin is vertically above respective top surfaces of the first and second semiconductor fins. The first portion and the second portion are electrically isolated by the dielectric fin. The first portion of the gate structure overlays an edge portion of the first semiconductor fin, and the second portion of the gate structure overlays a non-edge portion of the second semiconductor fin.

Abstract: A silica aerogel having a mean pore size less than 5 nm with a standard deviation of 3 nm. The silica aerogel may have greater than 95% solar-weighted transmittance at a thickness of 8 mm for wavelengths in the range of 250 nm to 2500 nm, and a 400° C. black-body weighted specific extinction coefficient of greater than 8 m2/kg for wavelengths of 1.5 ?m to 15 ?m. Silica aerogel synthesis methods are described. A solar thermal aerogel receiver (STAR) may include an opaque frame defining an opening, an aerogel layer disposed in the opaque frame, with at least a portion of the aerogel layer being proximate the opening, and a heat transfer fluid pipe in thermal contact with and proximate the aerogel layer. A concentrating solar energy system may include a STAR and at least one reflector to direct sunlight to an opening in the STAR.

Abstract: Systems and methods are provided for a level shifter. A level shifter includes a network of transistors configured to receive a signal at a first node in a first voltage domain and to generate a corresponding signal at a second node in a second voltage domain during a transition period of time. A self timing circuit is configured to receive an initiation signal based on the signal at the first node and to generate a voltage transition accelerator signal that is used to pull up the second node prior to the expiration of the transition period of time.

Abstract: In a method of group control and management among electronic devices, wherein the electronic devices is in communication with a control device, a projectable space instance is provided for the control device to create a workspace, wherein a control and management tool and a plurality of unified tools for driving respective electronic devices are selectively added to the projectable space instance. The projectable space instance is then parsed with a projector by the control device to automatically generate a projected workspace corresponding to the workspace to be created via the projectable space instance. The control and management tool realizes at least one status information of at least a first one of the electronic devices by way of the unified tools, and controls at least a second one of the electronic devices to execute at least one task corresponding to the at least one status information.

Abstract: A method includes: identifying a first design rule check (DRC) violation in a cluster box on an integrated circuit layout; locating a first target cell at a first original location in the cluster box, the first target cell being connected to the first DRC violation; detecting a first plurality of candidate locations for the first target cell in the cluster box; calculating resource costs associated with the first plurality of candidate locations; determining a first relocation location, among the first plurality of candidate locations, associated with a minimum resource cost for the first target cell; and relocating the first target cell from the first original location to the first relocation location.

Abstract: Memory devices and methods of forming the same are provided. A memory device of the present disclosure includes a bottom dielectric layer, a gate structure extending vertically from the bottom dielectric layer, a stack structure, and a dielectric layer extending between the gate structure and the stack structure. The stack structure includes a first silicide layer, a second silicide layer, an oxide layer extending between the first and second silicide layers, a channel region over the oxide layer and extending between the first and second silicide layers, and an isolation layer over the second silicide layer. The first and second silicide layers include cobalt, titanium, tungsten, or palladium.

Abstract: An integrated circuit includes a first nanosheet transistor and a second nanosheet transistor on a substrate. The first and second nanosheet each include gate electrodes. A gate isolation structure extends from a backside of the substrate between the gate electrodes. The gate isolation structure physically and electrically isolates the first and second gate electrodes from each other.

Abstract: Various embodiments of a battery charging apparatus are disclosed, along with methods of charging and rejuvenating a battery using the apparatus. The apparatus may include a positive electrode and a negative electrode which are configured to connect to a battery, and a charging current generator generating a charging current that charges the battery for a period of time via the positive and and negative electrodes by adding electric charge to the battery. The charging current is generated based on parameters of the battery, including a charging constant and an initial charging state. In some embodiments, a natural logarithm of a ratio of the added electric charge to the initial charging state substantially equals to a product of the charging constant and a length of the period of time and negative one.

Abstract: A headlight using an image light source is provided, which includes a laser light source and a wavelength converter. The laser light source includes multiple light-emitting units arranged in an array to provide an image beam. The wavelength converter is arranged downstream of an optical path of the laser light source. The wavelength converter is provided with a light dot matrix with the number of rows and columns greater than or equal to 40×40 to excite a part of the image beam into an excitation beam, and an unexcited part of the image beam is mixed with the excitation beam to generate a white beam.

Abstract: The present disclosure discloses a high-entropy alloy powder for laser cladding and a use method thereof. The alloy powder is CoCrFeMnNiCx, and x has a value of 0.1-0.15. The specific method includes: subjecting a 45 steel substrate to surface pretreatment, mixing the weighed CoCrFeMnNi high-entropy alloy powder with different content of a nano-C powder uniformly and pre-placed on the pre-treated substrate surface to form a prefabricated layer, then placing the prefabricated layer at 80-90° C. for constant temperature treatment for 8-12 h, and under a protective atmosphere, subjecting the cladding powder to laser cladding on the surface of the 45 steel. The method of the present disclosure prepares a CoCrFeMnNiCx high-entropy alloy coating with performance superior to the CoCrFeMnNi high-entropy alloy coating.

Abstract: A reticle pod with a spoiler structure includes a body and a cover. A reticle allocation area is centrally disposed at the body. The cover covers the body. A peripheral area of the cover and a peripheral area of the body are fitted together by a protruding portion and a dented portion. The dented portion and the protruding portion jointly form a spoiler structure surrounding the reticle allocation area. The spoiler structure includes a spoiler passage between the dented portion and the protruding portion. The body has at least one sidewall corresponding in position to the spoiler passage to form a particle-collecting space. Particles carried by external air current which enters the spoiler passage end up in the particle-collecting space and thus are denied entry into the reticle allocation area.

Abstract: A semiconductor die package is provided. The semiconductor die package includes a semiconductor die and a package substrate disposed below the semiconductor die. The semiconductor die has a corner. The package substrate includes several conductive lines, and one of the conductive lines under the corner of the semiconductor die includes a first line segment and a second line segment. The first and second line segments are connected together, and the second line segment has a smaller line width than the first line segment. The first line segment is linear and extends in a first direction. The second line segment is non-linear and has a varying extension direction.