Abstract: A method that is disclosed that includes the operations outlined below. Dies are arranged on a test fixture, and each of the dies includes first antennas and at least one via array, wherein the at least one via array is formed between at least two of the first antennas to separate the first antennas. By the first antennas of the dies, test processes are sequentially performed on an under-test device including second antennas that positionally correspond to the first antennas, according to signal transmissions between the first antennas and the second antennas.

Abstract: Examples of an integrated circuit with FinFET devices and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate, a fin extending from the substrate, a gate disposed on a first side of the fin, and a gate spacer disposed alongside the gate. The gate spacer has a first portion extending along the gate that has a first width and a second portion extending above the first gate that has a second width that is greater than the first width. In some such examples, the second portion of the gate spacer includes a gate spacer layer disposed on the gate.

Abstract: An integrated circuit is provided. The integrated circuit includes a three-dimensional memory device, a first word line driving circuit and a second word line driving circuit. The three-dimensional memory device includes stacking structures separately extending along a column direction. Each stacking structure includes a stack of word lines. The stacking structures have first staircase structures at a first side and second staircase structures at a second side. The word lines extend to steps of the first and second staircase structures. The first and second word line driving circuits lie below the three-dimensional memory device, and extend along the first and second sides, respectively. Some of the word lines in each stacking structure are routed to the first word line driving circuit from a first staircase structure, and others of the word lines in each stacking structure are routed to the second word line driving circuit from a second staircase structure.

Abstract: Test equipment for a battery management system is provided. A battery-parameter recognition module measures a standard battery to obtain the first correction input, and uses the capacity test formula and the relaxation time test formula to perform a first charge and discharge test on the battery to be tested to obtain first battery parameter. A real-time simulation module determines the battery model and the simulated battery state based on the first battery parameter and the dynamic load. Each simulator of a physical signal simulation module provides a battery physical signal indicating the battery model. A connector provides the battery physical signal to the battery management controller under test. The battery management controller under test provides a stimulated battery state based on the battery physical signal. Master equipment compares the simulated battery state with an estimated battery state to determine whether the battery management controller under test is normal.

Abstract: Methods for increasing immune therapy response and predicting likelihood of cancer metastasis by analyzing the expression of genes associated with replication stress response. In some aspects, cancers are treated with immune checkpoint inhibitors and/or MEK inhibitors. Methods for selecting patients by analyzing the expression of genes associated with a defect in replication stress response are also provided.

Abstract: A method is provided and includes several operations: arranging multiple channels extending in a first direction; arranging, in accordance with multiple weights of multiple macros, a first portion of the macro closer to a centroid of a core region of an integrated circuit than a second portion of the macros; and arranging the macros on opposite sides of the channels. The macros have multiple pins coupled to the channels interposed between the macros.

Abstract: A Video Semantic Segmentation System (VSSS) is disclosed that performs accurate and fast semantic segmentation of videos using a set of temporally distributed neural networks. The VSSS receives as input a video signal comprising a contiguous sequence of temporally-related video frames. The VSSS extracts features from the video frames in the contiguous sequence and based upon the extracted features, selects, from a set of labels, a label to be associated with each pixel of each video frame in the video signal. In certain embodiments, a set of multiple neural networks are used to extract the features to be used for video segmentation and the extraction of features is distributed among the multiple neural networks in the set. A strong feature representation representing the entirety of the features is produced for each video frame in the sequence of video frames by aggregating the output features extracted by the multiple neural networks.

Abstract: A memory device is provided. The memory device includes several sense amplifiers and at least one reference cell. Each of the sense amplifiers has a first terminal and a second terminal. The first terminals of the sense amplifiers are coupled to a memory cell block, and the second terminals of the sense amplifiers are coupled together to transmit a read current. The at least one reference cell transmits the read current to a ground terminal. The at least one reference cell has a decreased resistance value when a number N of the sense amplifiers increases.

Abstract: Some embodiment structures and methods are described. A structure includes an integrated circuit die at least laterally encapsulated by an encapsulant, and a redistribution structure on the integrated circuit die and encapsulant. The redistribution structure is electrically coupled to the integrated circuit die. The redistribution structure includes a first dielectric layer on at least the encapsulant, a metallization pattern on the first dielectric layer, a metal oxide layered structure on the metallization pattern, and a second dielectric layer on the first dielectric layer and the metallization pattern. The metal oxide layered structure includes a metal oxide layer having a ratio of metal atoms to oxygen atoms that is substantially 1:1, and a thickness of the metal oxide layered structure is at least 50 ?. The second dielectric layer is a photo-sensitive material. The metal oxide layered structure is disposed between the metallization pattern and the second dielectric layer.

Abstract: A method includes forming an interposer, which includes forming a rigid dielectric layer, and removing portions of the rigid dielectric layer. The method further includes bonding a package component to an interconnect structure, and bonding the interposer to the interconnect structure. A spacer in the interposer has a bottom surface contacting a top surface of the package component, and the spacer includes a feature selected from the group consisting of a metal feature, the rigid dielectric layer, and combinations thereof. A die-saw is performed on the interconnect structure.

Abstract: A ferroelectric semiconductor device and method are described herein. The method includes performing a diffusion anneal process to drive elements of a dopant film through an amorphous silicon layer and into a gate dielectric layer over a fin to form a doped gate dielectric layer with a gradient depth profile of dopant concentrations. The doped gate dielectric layer is crystallized during a post-cap anneal process to form a gradient depth profile of ferroelectric properties within the crystallized gate dielectric layer. A metal gate electrode is formed over the crystallized gate dielectric layer to obtain a ferroelectric transistor with multi-ferroelectric properties between the gate electrode and the channel. The ferroelectric transistor may be used in deep neural network (DNN) applications.

Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.

Abstract: A magnetoresistive random access memory (MRAM) structure includes a magnetic tunnel junction (MTJ), and a top electrode which contacts an end of the MTJ. The top electrode includes a top electrode upper portion and a top electrode lower portion. The width of the top electrode upper portion is larger than the width of the top electrode lower portion. A bottom electrode contacts another end of the MTJ. The top electrode, the MTJ and the bottom electrode form an MRAM.

Abstract: A server maintains a gallery of ephemeral messages. Each ephemeral message is posted to the gallery by a user for viewing by recipients via recipient devices. In response to a gallery view request from any of the recipient devices, the ephemeral messages in the gallery are displayed on the requesting device in automated sequence, each message being displayed for a respective display duration before display of the next message in the gallery. Each ephemeral message has an associated message availability parameter. Each ephemeral message is removed from the gallery, thus being unavailable for viewing upon request, at expiry of the corresponding message availability parameter.

Abstract: In an approach, a processor obtains an encrypted data key and a first encrypted protection key from a storage device. A processor sends the first encrypted protection key to a first device. A processor obtains a protection key from the first device, wherein the protection key is generated by the first device through decrypting the first encrypted protection key. A processor decrypts the encrypted data key using the protection key to obtain a data key.

Abstract: A user equipment (UE), a base station (BS), and a method for managing UE operation in C-DRX. The UE includes a transceiver configured to receive configurations for a drx-onDurationTimer, search space sets for reception of a PDCCH, a first set of CSI-RS resources, SS/PBCH blocks, and a PUCCH resources; and the PDCCH that provides a DCI format including a field indicating whether or not to start the drx-onDurationTimer. A processor is configured to determine an indication by the field to not start the drx-onDurationTimer, and determine reception occasions for the first set of CSI-RS resources during the ON duration. The transceiver is configured to receive the first set of CSI-RS resources or the SS/PBCH blocks during at least one of the reception occasions. The processor is also configured to determine a CSI report based on a reception occasion, which can be transmitted using the PUCCH resource during the ON duration.

Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip. The method includes forming a gate electrode over a substrate. The gate electrode is laterally separated from a dielectric by a spacer structure. A sacrificial layer is formed over a top surface of the gate electrode. A liner layer is formed along a sidewall of the spacer structure and on the sacrificial layer. The sacrificial layer is removed and a hard mask material is formed over the gate electrode. A part of the dielectric is removed to form a contact opening laterally separated from the gate electrode by the spacer structure. A conductive contact is formed within the contact opening.

Abstract: An encoding control method, a memory storage device and a memory control circuit unit are disclosed. The method includes: performing, by an encoding circuit, a first encoding operation to generate first parity data according to write data, a first sub-matrix and a second sub-matrix of a parity check matrix; performing, by the encoding circuit, a second encoding operation to generate second parity data according to the write data, the first parity data, a third sub-matrix, a fourth sub-matrix and a fifth sub-matrix of the parity check matrix; and sending a first write command sequence to instruct a storing of the write data, the first parity data and the second parity data to a rewritable non-volatile memory module.

Abstract: Provided in implementation of the present disclosure are a wireless communication method and device, configured to improve flexibility of channel transmission. The method includes: determining, by a terminal device, a plurality of time units according to a constraint condition starting from a first time unit, the plurality of time units being used for transmitting one first channel; and sending, by the terminal device, the one first channel to a network device on the plurality of time units.

Abstract: A light-emitting unit, having a substrate; a first light-emitting body formed on the substrate, and having a first longer side and a first shorter side; a second light-emitting body formed on the substrate, and having a second longer side and a second shorter side which is parallel to the first longer side; a third light-emitting body formed on the substrate, having a third longer side and a third shorter side which is parallel to the first longer side, and electrically connected to the first light-emitting body and the second light-emitting body; a first electrode covering the first light-emitting body and the second light-emitting body, and electrically connecting to the first light-emitting body; a second electrode separated from the first electrode, and covering the second light-emitting body without covering the first light-emitting body; and a transparent element enclosing the first light-emitting body, the second light-emitting body, and the third light-emitting body.