Abstract: The present disclosure provides a microfluidic chip, a box device adapted to the microfluidic chip, and a microfluidic device including the microfluidic chip and the box device. The microfluidic chip includes a first container for accommodating a first fluid, a second container for accommodating a second fluid, a delivery channel, a sorting channel and a collector. The delivery channel is shaped such that the first fluid and the second fluid merge at a confluence. The sorting channel includes a first sorting channel and a second sorting channel. The collector includes a first collector and a second collector.

Abstract: Provided herein are heterocyclic derivative compounds and pharmaceutical compositions comprising said compounds that are useful for the treatment of retinal binding protein (RBP4) related diseases, such as macular degeneration and the like.

Abstract: The application provides a display cooled by internal and external airflows circulation. The display comprises a shell, a fan module, a heat exchanger and a display module for displaying information, wherein the display module comprises a display panel, a heat dissipation plate and a module backplane. One or more internal circulation air ducts and external circulation air ducts are arranged on the heat exchanger. The fan module drives air in the shell to pass through the internal circulation air ducts and the inside of the display module, and pass through the heat dissipation plate to form internal circulation airflow. The shell is provided with an external circulation ventilation structure leading to an external circulation air duct, and the fan module drives the air inside and outside the shell to pass through the external circulation ventilation structure to form external circulation airflow.

Abstract: A fan-out type packaging structure includes a strain adjustment layer, a plurality of chips, an encapsulation layer, a redistribution layer, and a plurality of solder balls. The strain adjustment layer is made of a polymer material and has at least 95% laser absorbance. The plurality of chips are partially embedded in the strain adjustment layer and are spaced apart from each other. The encapsulation layer surrounds the chips and is connected to the strain adjustment layer. The redistribution layer covers the encapsulation layer and the chips. The plurality of solder balls are disposed on the redistribution layer and are spaced apart from each other.

Abstract: Metal insulator metal capacitors are described. In an example, a metal-insulator-metal (MIM) capacitor includes a first electrode. An insulator is over the first electrode. The insulator includes a first layer, and a second layer over the first layer. The first layer has a leakage current that is less than a leakage current of the second layer. The second layer has a dielectric constant that is greater than a dielectric constant of the first layer. A second electrode is over the insulator.

Abstract: The present invention provides an antenna packaging structure and a manufacturing method thereof. An antenna and a chip are respectively disposed on two sides of a substrate layer, antenna layers are formed by an antenna support member, a first antenna layer located above the antenna support member and a second antenna layer located below the antenna support member together, and interlayer dielectrics of the antenna support member and the antenna layers are low dielectric loss materials, so that a heterogeneous and isomerous antenna structure is formed, thereby reducing the problems such as current leakage and stray capacitance in the packaging structure caused by dielectric loss, and reducing a size of the antenna packaging structure.

Abstract: A memory device includes a semiconductor substrate having an active region, and a word line extending across the active region. The memory device also includes a first source/drain region and a second source/drain region disposed in the active region and at opposite sides of the word line, a bit line disposed over and electrically connected to the first source/drain region, and a capacitor disposed over and electrically connected to the second source/drain region. The capacitor includes a bottom electrode, a top electrode, and a capacitor dielectric structure disposed between them. The capacitor dielectric structure includes a first metal oxide layer, a second metal oxide layer disposed over the first metal oxide layer, and a third metal oxide layer disposed over the second metal oxide layer. The first, the second and the third metal oxide layer include materials that are different from each other.

Abstract: A circuit board assembly in a camera module for blocking unwanted light when images are captured includes a circuit board, a sensor, and an optical blocking body connecting the circuit board and the sensor. The circuit board includes a base board and a photomask. The photomask is arranged on a surface of the base board, the base board includes conductive circuit layers and dielectric layers, the conductive circuit layers and the dielectric layers are alternately arranged, the sensor being electronically connected to the conductive layers. The optical blocking body, the photomask, and the dielectric layers block ambient light entering the camera module other than through the lens assembly of the camera module.

Abstract: A coil structure comprises a coil and a conductive terminal part, wherein the coil is formed by a conductive wire comprising a metal wire and at least one insulating layer encapsulating the metal wire, wherein a first terminal part of the metal wire is exposed from the at least one insulating layer, wherein a first portion of the conductive terminal part encapsulates the first terminal part of the metal wire and a second portion of the conductive terminal part extends from said first portion as an electrode for electrically connecting to an external circuit.

Abstract: Provided are certain BTK inhibitors, pharmaceutical compositions thereof, and methods of use thereof.

Abstract: A method, computer system, and a computer program product for improving debugging speed by rearranging debugging priority functions. In one embodiment, runtime input may be received about a program to be debugged. Feedback information is obtained about at least one similar program previously debugged. The compiling time information and runtime information are analyzed to determine a status of functions including one or more focused functions that will be used frequently and one or more unreachable functions that may never will be executed. A priority list of debugging functions is generated based on the feedback information, the runtime input and a function status. A plurality of debugging information are rearranged and parsed on the priority list prior to said program being debugged based on said debugging information.

Abstract: The present invention provides a use of a growth factors-enriched dry powder for relieving inflammation or injury, wherein each gram of the growth factors-enriched dry powder comprises more than or equal to 9×104 pg of PDGF-BB.

Abstract: A semiconductor device and a method of manufacturing thereof are provided. The semiconductor device comprises a gate stack, source/drain regions, and a source/drain contact via. The gate stack is disposed on a substrate. The source/drain regions are disposed on the substrate and located at opposite sides of the gate stack. The source/drain contact via penetrates through the substrate and is electrically connected to a first source/drain region among the source/drain regions. The source/drain contact vias comprise a first conductor and a second conductor disposed on the first conductor. The first conductor comprises a silicide layer and a first metallic portion. The second conductor comprises a glue layer and a second metallic portion. The first metallic portion is spaced apart from the second metallic portion by the glue layer.

Abstract: A method of forming a capacitor structure includes following operations. A first electrode is formed. A hafnium-zirconium oxide (HZO) layer is formed over the first electrode under a first temperature. An interface dielectric layer is formed over the HZO layer under a second temperature greater than the first temperature. A second electrode is formed over the interface dielectric layer. The HZO layer and the interface dielectric layer are annealed.

Abstract: Embodiments relate to a coating system. A substrate includes a first coating region and a second coating region adjacent to the first coating region. The coating system includes a first gravure mechanism and a second gravure mechanism, where the first gravure mechanism is configured to apply a first functional layer onto the first coating region, and the second gravure mechanism can receive the substrate having the first functional layer and apply a second functional layer made of a material different from that of the first functional layer onto the second coating region. In the coating system, with provision of first gravure mechanism and the second gravure mechanism, when the substrate is continuously transported in a same direction, the two functional layers made of different materials can be sequentially applied onto corresponding regions of the substrate.

Abstract: Terminal device attempts to initiate a COT-u at the beginning of an FFP-u. In a case that the starting of the FFP-u collides with an IP-g, a PUSCH transmission overlapping with a period after the sensing slot and before the end of the IP-g is not scheduled. In a case that the starting of the FFP-u does not collide with the IP-g, the PUSCH transmission is scheduled and transmitted.

Abstract: Package structures and methods of forming package structures are discussed. A package structure, in accordance with some embodiments, includes a large package component, such as a CoWoS, adhered to a large package substrate, such as a printed circuit board, an underfill material disposed between the large package component and the large package substrate, and a stress-release structure with high elongation values formed from photolithography encapsulated by the underfill material. The stress-release structure helping to reduce stress in the underfill material to reduce the risk of underfill cracking caused by the difference in coefficients of thermal expansion between the large package component and the large package substrate.

Abstract: The present disclosure provides methods and techniques for evaluating and improving algorithms for autonomous driving planning and control (PNC), using one or more metrics (e.g., similarity scores) computed based on expert demonstrations. For example, the one or more metrics allow for improving PNC based on human, as opposed to or in addition to optimizing certain oversimplified properties, such as the least distance or time, as an objective. When driving in certain scenarios, such as taking a turn, people may drive in a distributed probability pattern instead of in a uniform line (e.g., different speeds and different curvatures at the same corner). As such, there can be more than one “correct” control trajectory for an autonomous vehicle to perform in the same turn. Safety, comfort, speeds, and other criteria may lead to different preferences and judgment as to how well the controlled trajectory has been computed.

Abstract: The present invention relates to a multilayer sheet comprising at least two layers (A) and (B) in adherent contact with each other, wherein layer (A) is a foamed sheet comprising a high melt strength polypropylene composition and layer (B) is a coated non-foamed layer, which comprises a polypropylene composition, a process for producing said multilayer sheet, an article comprising said multilayer sheet and the use of said multilayer sheet for the production of an article with improved water vapor transmission and oxygen transmission properties.

Abstract: A method for treating a semiconductor structure includes: forming the semiconductor structure which includes a carrier substrate, a device substrate, a semiconductor device formed on the device substrate, and a bonding layer formed to bond the semiconductor device with the carrier substrate, the device substrate having an upper surface which is faced upwardly, and which is opposite to the semiconductor device; and directing a chemical fluid to impinge the upper surface of the device substrate so as to remove an edge portion of the device substrate.