Abstract: An electromagnetic relay includes an electromagnetic unit, a magnetic moving subunit, a first conduct, a second conduct, a movable lead, and a movable contact. The movable lead has a swing portion and a resilient linkage portion. The movable contact is disposed on the swing portion. When the electromagnetic unit is energized, the magnetic moving subunit is attracted by the electromagnetic unit and pushes the resilient linkage portion of the movable lead such that the resilient linkage portion urges the swing portion to swing and that the movable contact disposed on the swing portion is urged to be in contact with one of the first contact and the second contact. When the electromagnetic unit is de-energized, the electromagnetic unit ceases to attract the magnetic moving subunit such that the movable contact is in contact with the other one of the first contact and the second contact.

Abstract: An efficiency tracking method of a controller applied to a flyback power converter includes before the controller soft starts, an original frequency variation curve setting voltage generated by the controller outputting an original frequency variation curve setting detection current to an original frequency variation curve setting detection resistor determining a frequency variation curve of the flyback power converter, and utilizing adjustment of resistance of the original frequency variation curve setting detection resistor to achieve efficiency optimization. Therefore, the controller controls an output voltage of the flyback power converter and tracks a maximum power point of the flyback power converter according to the efficiency tracking method to achieve efficiency optimization.

Abstract: A probing system includes a device-under-test, a probe device, and a die bonder. The device-under-test includes test patterns. The probe device includes tilt angle sensors. The tilt angle sensors include spikes that protrude from the probe device. The die bonder is operational to mount the device-under-test, mount the probe device facing the device-under-test, compress the probe device and the device-under-test together to causes a subset of the spikes to contact the test patterns, measure a number of connections formed between the tilt angle sensors and the test patterns, determine a first offset angle and a second offset angle between the device-under-test and the probe device based on the number of connections, adjust the spherical positioner in one or more rotational axes in response to the first offset angle and the second offset angle to change a parallelism between the device-under-test and the probe device.

Abstract: A switching regulator includes: a power stage circuit; a control circuit; and an operation clock signal generator circuit configured to generate plural test clock signals during a clock determination period and generate an operation clock signal during a normal operation period. When the switching regulator operates during the clock determination period in a discontinuous conduction mode, the control circuit alternatingly generates plural PWM signals corresponding to the test clock signals generated by the operation clock signal generator circuit and an output voltage, wherein each PWM signal corresponds to one test clock signal, so that the power stage circuit generates corresponding phase node voltages at a phase node, wherein among the plural test clock signals, the operation clock signal generator circuit selects one test clock signal corresponding to a minimum phase node voltage as the operation clock signal during the normal operation period.

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a first barrier layer on the buffer layer; forming a first hard mask on the first barrier layer; removing the first hard mask and the first barrier layer to form a recess; forming a second barrier layer in the recess; and forming a p-type semiconductor layer on the second barrier layer.

Abstract: A semiconductor device includes a fin structure, a metal gate stack, a barrier structure and an epitaxial source/drain region. The fin structure is over a substrate. The metal gate stack is across the fin structure. The barrier structure is on opposite sides of the metal gate stack. The barrier structure comprises one or more passivation layers and one or more barrier layers, and the one or more passivation layers have a material different from a material of the one or more barrier layers. The epitaxial source/drain region is over the barrier structure.

Abstract: Disclosed are a display device and a backlight control method for the display device. The display device includes a display panel, a backlight source, a first computing unit, and a second computing unit. The display panel includes a first display region and a second display region. The first light-emitting region corresponds to the first display region. The second light-emitting region corresponds to the second display region. The first computing unit calculates a first brightness distribution within a first range. The second computing unit calculates a second brightness distribution within a second range. The first light-emitting region emits light according to the first brightness distribution. The second light-emitting region emits light according to the second brightness distribution.

Abstract: A fatigue data generation method, comprising: obtaining, by the camera device, a target image; obtaining, by a processor, a target feature data from the target image, and inputting the target feature data to a fatigue analysis model which stored in a storage unit, wherein the fatigue analysis model comprises a plurality of reference physiological signals, a plurality of reference feature data, a plurality of reference fatigue data and a plurality of correlation parameters; and generating a target fatigue data according to the target feature data, the plurality of reference feature data and the plurality of correlation parameters.

Abstract: A sense amplifier includes a first pair of transistors having gate terminals respectively coupled to a first input terminal for receiving a first input signal and to a second input terminal for receiving a second input signal, source terminals coupled to a first power supply terminal, and drain terminals. The sense amplifier also includes a second pair of transistors having gate terminals coupled to a clock terminal, source terminals respectively coupled to the drain terminals of the first pair of transistors, and drain terminals. The sense amplifier also includes a third pair of transistors having gate terminals coupled to the clock terminal, drain terminals respectively coupled to the drain terminals of the second pair of transistors, and source terminals coupled to a second power supply terminal. In addition, the sense amplifier includes an output circuit coupled to the drain terminals of the second pair of transistors and having an output terminal.

Abstract: An automatic robotic arm system and a coordinating method for robotic arm and computer vision thereof are disclosed. A beam-splitting mirror splits an incident light into a visible light and a ranging light and respectively guides to an image capturing device and an optical ranging device arranged in the different reference axes. In a calibration mode, a transformation relation is computed based on a plurality of the calibration postures and corresponding calibration images. In an operation mode, a mechanical space coordinate is determined based on an operation image and the transformation relation, and the robotic arm is controlled to move based on the mechanical space coordinate.

Abstract: A method of forming an integrated circuit, including forming a n-type doped well (N-well) and a p-type doped well (P-well) disposed side by side on a semiconductor substrate, forming a first fin active region extruded from the N-well and a second fin active region extruded from the P-well, forming a first isolation feature inserted between and vertically extending through the N-well and the P-well, and forming a second isolation feature over the N-well and the P-well and laterally contacting the first and the second fin active regions.

Abstract: A backplane includes: a substrate including a circuit structure layer, a first reflective layer disposed on a bearing surface of the substrate, a plurality of light-emitting diode chips, and a plurality of optical structures. The first reflective layer includes a plurality of through holes spaced apart. A light-emitting diode chip in the plurality of light-emitting diode chips is located in one of the plurality of through holes. The plurality of light-emitting diode chips are electrically connected to the circuit structure layer. The circuit structure layer is configured to drive the plurality of light-emitting diode chips to emit light. An optical structure in the plurality of optical structures covers the light-emitting diode chip, a light incident surface of the optical structure is in contact with a light exit surface of the light-emitting diode chip, and a light exit surface of the optical structure is a curved surface.

Abstract: A system and a method for parameter optimization with adaptive search space and a user interface using the same are provided. The system includes a data acquisition unit, an adaptive adjustment unit and an optimization search unit. The data acquisition unit obtains a set of executed values of several operating parameters and a target parameter. The adaptive adjustment unit includes a parameter space transformer and a search range definer. The parameter space transformer performs a space transformation on a parameter space of the operating parameters according to the executed values. The search range definer defines a parameter search range in a transformed parameter space based on the sets of the executed values. The optimization search unit takes the parameter search range as a limiting condition and takes optimizing the target parameter as a target to search for a set of recommended values of the operating parameters.

Abstract: A self-aligned plug may be formed between deep trench isolation (DTI) etching cycles. Accordingly, etch depth in areas of a pixel sensor with large CDs (e.g., at an X-road) is reduced, which prevents trench loading. As a result, a floating diffusion (FD) region, associated with photodiodes of the pixel sensor, is not damaged during the DTI etching cycles. Reduced chances of damage to the FD region improves performance of the pixel sensor and prevents electrical shorts and failures, which increases yield and conserves time and raw materials used in forming the pixel sensor.

Abstract: A terminal device and a terminal device installation method are provided. The terminal device includes a machine body, a detachable cover with two side walls, and at least two coupling mechanisms arranged symmetrically. The machine body includes a front board, a rear board opposite to the front board, and two side boards connected between the front board and the rear board. Each coupling mechanism includes a coupling portion located at one side wall, a front track and a rear track respectively having a front opening and a rear opening opposite to the front opening and both located at one side board. As each coupling portion is coupled to each front track, the cover is assembled with the machine body and covers the front board, and as each coupling portion is coupled with each rear track, the cover is assembled to the machine body and covers the rear board.

Abstract: A light-adjusting device having first regions and second regions is provided. The light-adjusting device includes pillars that form several groups of meta structures. The groups of meta structures correspond to the first regions, and from a top view, the first regions and the second regions are arranged in a checkerboard pattern.

Abstract: An upper for an article of footwear is configured to be connected to a sole structure and is configured to receive a foot. The upper includes a knitted component having a strobel portion that is configured to be disposed underneath the foot. The strobel portion defines an interior surface and an exterior surface of the knitted component. The strobel portion defines a strobel passage between the interior surface and the exterior surface. Also, the upper includes a tensile strand that extends through the strobel passage.

Abstract: A chip package includes an application chip, a micro-electromechanical systems (MEMS) chip, a conductive element, a bonding wire, and a molding compound. The application chip has a conductive pad. The MEMS chip is located on the application chip, and includes a main body and a cap. The main body is located between the cap and the application chip. The main body has a conductive pad. The conductive element is located on the conductive pad of the main body of the MEMS chip. The bonding wire extends from the conductive element to the conductive pad of the application chip. The molding compound is located on the application chip and surrounds the MEMS chip. The conductive element and the bonding wire are located in the molding compound.

Abstract: A wireless communication method includes: categorizing a plurality of different beacon elements into a first group of elements and a second group of elements; generating a beacon frame, which is configured to carry the first group of elements, wherein the beacon frame is compliant to at least one legacy generation of Wi-Fi technology; generating a second frame, which is configured to carry the second group of elements, wherein the second frame is compliant to a non-legacy generation of Wi-Fi technology rather than the at least one legacy generation of Wi-Fi technology; and sending the beacon frame and the second frame.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a gate electrode, and a stack of dielectric layers. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The compound semiconductor layer is disposed on the barrier layer. The gate electrode is disposed on the compound semiconductor layer. The stack of dielectric layers is disposed on the gate electrode. The stack of dielectric layers includes layers having different etching rates.