Patents by Inventor A-Ming Chang

A-Ming Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11958200
    Abstract: An automatic robotic arm system and a coordinating method for robotic arm and computer vision thereof are disclosed. A beam-splitting mirror splits an incident light into a visible light and a ranging light and respectively guides to an image capturing device and an optical ranging device arranged in the different reference axes. In a calibration mode, a transformation relation is computed based on a plurality of the calibration postures and corresponding calibration images. In an operation mode, a mechanical space coordinate is determined based on an operation image and the transformation relation, and the robotic arm is controlled to move based on the mechanical space coordinate.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: April 16, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Hung-Hsin Chen, Chia-Jun Yu, Qi-Ming Huang, Chin-Lun Chang, Keng-Ning Chang
  • Patent number: 11961769
    Abstract: A method of forming an integrated circuit, including forming a n-type doped well (N-well) and a p-type doped well (P-well) disposed side by side on a semiconductor substrate, forming a first fin active region extruded from the N-well and a second fin active region extruded from the P-well, forming a first isolation feature inserted between and vertically extending through the N-well and the P-well, and forming a second isolation feature over the N-well and the P-well and laterally contacting the first and the second fin active regions.
    Type: Grant
    Filed: November 7, 2022
    Date of Patent: April 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Kuo-Hsiu Hsu, Yu-Kuan Lin, Feng-Ming Chang, Hsin-Wen Su, Lien Jung Hung, Ping-Wei Wang
  • Publication number: 20240120363
    Abstract: A self-aligned plug may be formed between deep trench isolation (DTI) etching cycles. Accordingly, etch depth in areas of a pixel sensor with large CDs (e.g., at an X-road) is reduced, which prevents trench loading. As a result, a floating diffusion (FD) region, associated with photodiodes of the pixel sensor, is not damaged during the DTI etching cycles. Reduced chances of damage to the FD region improves performance of the pixel sensor and prevents electrical shorts and failures, which increases yield and conserves time and raw materials used in forming the pixel sensor.
    Type: Application
    Filed: January 5, 2023
    Publication date: April 11, 2024
    Inventors: Ming-Chyi LIU, Jiech-Fun LU, Shih-Chang LIU, Ru-Liang LEE
  • Publication number: 20240121523
    Abstract: A light-adjusting device having first regions and second regions is provided. The light-adjusting device includes pillars that form several groups of meta structures. The groups of meta structures correspond to the first regions, and from a top view, the first regions and the second regions are arranged in a checkerboard pattern.
    Type: Application
    Filed: October 7, 2022
    Publication date: April 11, 2024
    Inventors: Kai-Hao CHANG, Chun-Yuan WANG, Shin-Hong KUO, Zong-Ru TU, Po-Hsiang WANG, Chih-Ming WANG
  • Publication number: 20240121920
    Abstract: A terminal device and a terminal device installation method are provided. The terminal device includes a machine body, a detachable cover with two side walls, and at least two coupling mechanisms arranged symmetrically. The machine body includes a front board, a rear board opposite to the front board, and two side boards connected between the front board and the rear board. Each coupling mechanism includes a coupling portion located at one side wall, a front track and a rear track respectively having a front opening and a rear opening opposite to the front opening and both located at one side board. As each coupling portion is coupled to each front track, the cover is assembled with the machine body and covers the front board, and as each coupling portion is coupled with each rear track, the cover is assembled to the machine body and covers the rear board.
    Type: Application
    Filed: October 5, 2023
    Publication date: April 11, 2024
    Inventors: Yuan-Yu CHEN, Ming-Hung HUNG, Po-Chang CHU
  • Publication number: 20240114989
    Abstract: An upper for an article of footwear is configured to be connected to a sole structure and is configured to receive a foot. The upper includes a knitted component having a strobel portion that is configured to be disposed underneath the foot. The strobel portion defines an interior surface and an exterior surface of the knitted component. The strobel portion defines a strobel passage between the interior surface and the exterior surface. Also, the upper includes a tensile strand that extends through the strobel passage.
    Type: Application
    Filed: December 15, 2023
    Publication date: April 11, 2024
    Inventors: Daniel A. Podhajny, Chung-Ming Chang, Ya-Fang Chen, Pei-Ju Su
  • Publication number: 20240121705
    Abstract: A wireless communication method includes: categorizing a plurality of different beacon elements into a first group of elements and a second group of elements; generating a beacon frame, which is configured to carry the first group of elements, wherein the beacon frame is compliant to at least one legacy generation of Wi-Fi technology; generating a second frame, which is configured to carry the second group of elements, wherein the second frame is compliant to a non-legacy generation of Wi-Fi technology rather than the at least one legacy generation of Wi-Fi technology; and sending the beacon frame and the second frame.
    Type: Application
    Filed: September 20, 2023
    Publication date: April 11, 2024
    Applicant: MEDIATEK INC.
    Inventors: Chien-Fang Hsu, Chia-Ming Chang
  • Publication number: 20240116751
    Abstract: A chip package includes an application chip, a micro-electromechanical systems (MEMS) chip, a conductive element, a bonding wire, and a molding compound. The application chip has a conductive pad. The MEMS chip is located on the application chip, and includes a main body and a cap. The main body is located between the cap and the application chip. The main body has a conductive pad. The conductive element is located on the conductive pad of the main body of the MEMS chip. The bonding wire extends from the conductive element to the conductive pad of the application chip. The molding compound is located on the application chip and surrounds the MEMS chip. The conductive element and the bonding wire are located in the molding compound.
    Type: Application
    Filed: October 3, 2023
    Publication date: April 11, 2024
    Inventors: Chia-Ming CHENG, Shu-Ming CHANG, Tsang Yu LIU
  • Patent number: 11955515
    Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure on the fin structure, forming first and second S/D regions within the superlattice structure, forming a gate structure between the first and second S/D regions, forming first and second contact structures on first surfaces of the first and second S/D regions, and forming a third contact structure, on a second surface of the first S/D region, with a work function metal (WFM) silicide layer and a dual metal liner. The second surface is opposite to the first surface of the first S/D region and the WFM silicide layer has a work function value closer to a conduction band energy than a valence band energy of a material of the first S/D region.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Chuan Chiu, Chia-Hao Chang, Cheng-Chi Chuang, Chih-Hao Wang, Huan-Chieh Su, Chun-Yuan Chen, Li-Zhen Yu, Yu-Ming Lin
  • Patent number: 11955397
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a channel layer, a barrier layer, a compound semiconductor layer, a gate electrode, and a stack of dielectric layers. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The compound semiconductor layer is disposed on the barrier layer. The gate electrode is disposed on the compound semiconductor layer. The stack of dielectric layers is disposed on the gate electrode. The stack of dielectric layers includes layers having different etching rates.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: April 9, 2024
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Shin-Cheng Lin, Cheng-Wei Chou, Ting-En Hsieh, Yi-Han Huang, Kwang-Ming Lin, Yung-Fong Lin, Cheng-Tao Chou, Chi-Fu Lee, Chia-Lin Chen, Shu-Wen Chang
  • Patent number: 11953940
    Abstract: A display apparatus includes a light-transmitting structural plate, some optical microscopic structures, an optical film, a base plate and some light emitting elements. The light-transmitting structural plate has a first side and a second side opposite to each other. The optical microscopic structures are regularly arrayed and formed on the first side or the second side. The optical microscopic structure has an inclined surface connecting at a connecting line and forming an angle ranging between 30 degrees and 150 degrees with a corresponding inclined surface of an adjacent one of the optical microscopic structures. The optical film is located on the first side. The base plate is separated from the second side by a space. The light emitting elements are located inside the space and disposed on the base plate. The light emitting elements respectively emit a light ray to the light-transmitting structural plate.
    Type: Grant
    Filed: October 7, 2020
    Date of Patent: April 9, 2024
    Assignee: DARWIN PRECISIONS CORPORATION
    Inventors: Yu-Cheng Chang, Shu-Ching Peng, Yu-Ming Huang
  • Patent number: 11953448
    Abstract: A method for defect inspection includes receiving a substrate having a plurality of patterns; obtaining a gray scale image of the substrate, wherein the gray scale image includes a plurality of regions, and each of the regions has a gray scale value; comparing the gray scale value of each region to a gray scale references to define a first group, a second group and an Nth group, wherein each of the first group, the second group and the Nth group has at least a region; performing a calculation to obtain a score; and when the score is greater than a value, the substrate is determined to have an ESD defect, and when the score is less than the value, the substrate is determined to be free of the ESD defect.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: April 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tsun-Cheng Tang, Hao-Ming Chang, Sheng-Chang Hsu, Cheng-Ming Lin
  • Patent number: 11956929
    Abstract: A server device includes a casing, an electronic assembly, a cover, and a heat dissipation device. The electronic assembly includes a circuit board and at least one heat source. The circuit board is disposed on the casing, and the heat source is disposed on the circuit board. The cover is removably disposed on the casing. The heat dissipation device includes at least one air cooling heat exchanger and at least one liquid cooling heat exchanger. The air cooling heat exchanger is fixed on and thermally coupled with the heat source. The liquid cooling heat exchanger is fixed on the cover and thermally coupled with the air cooling heat exchanger.
    Type: Grant
    Filed: September 15, 2021
    Date of Patent: April 9, 2024
    Assignees: INVENTEC (PUDONG) TECHNOLOGY CORPORATION, INVENTEC CORPORATION
    Inventors: Chun-Ming Chang, Tai-Jung Sung
  • Patent number: 11955535
    Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to one embodiment includes an active region including a channel region and a source/drain region adjacent the channel region, a gate structure over the channel region of the active region, a source/drain contact over the source/drain region, a dielectric feature over the gate structure and including a lower portion adjacent the gate structure and an upper portion away from the gate structure, and an air gap disposed between the gate structure and the source/drain contact. A first width of the upper portion of the dielectric feature along a first direction is greater than a second width of the lower portion of the dielectric feature along the first direction. The air gap is disposed below the upper portion of the dielectric feature.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: April 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Hao Chang, Lin-Yu Huang, Sheng-Tsung Wang, Cheng-Chi Chuang, Yu-Ming Lin, Chih-Hao Wang
  • Publication number: 20240111837
    Abstract: An Image Activated Cell Sorting (IACS) classification workflow includes: employing a neural network-based feature encoder (or extractor) to extract features of cell images; automatically clustering cells based on extracted cell features; identifying a cluster to pick which cluster(s) to sort based on the cell images; fine-tuning a classification network based on the cluster(s) selected; and once refined, the classification network is used to sort cells for real-time live sorting.
    Type: Application
    Filed: February 24, 2023
    Publication date: April 4, 2024
    Inventors: Ming-Chang Liu, Su-Hui Chiang, Haipeng Tang, Michael Zordan, Ko-Kai Albert Huang
  • Publication number: 20240111121
    Abstract: An imaging lens module includes a plastic lens barrel, a first optical element assembly and a second optical element assembly, wherein both of the first optical element assembly and the second optical element assembly are disposed in the plastic lens barrel. The plastic lens barrel includes a first inner annular surface and a second inner annular surface. The first inner annular surface forms a first receiving space. The second inner annular surface forms a second receiving space. The first optical element assembly is disposed in the first receiving space and includes a plurality of optical lens elements and a first retainer. The second optical element assembly is disposed in the second receiving space and includes a first light blocking sheet and a second retainer.
    Type: Application
    Filed: December 13, 2023
    Publication date: April 4, 2024
    Inventors: Chien-Hsun WU, Lin-An CHANG, Ming-Ta CHOU
  • Publication number: 20240111139
    Abstract: An imaging lens assembly module includes a lens barrel, a catadioptric lens assembly, an imaging lens assembly, a first fixing element and a second fixing element. The lens barrel has a first relying surface and a second relying surface, which face towards an object side of the imaging lens assembly module. The catadioptric lens assembly relies on the first relying surface. The imaging lens assembly is disposed on an image side of the catadioptric lens assembly, and relies on the second relying surface. The first fixing element is for fixing the catadioptric lens assembly to the lens barrel. The second fixing element is for fixing the imaging lens assembly to the lens barrel. The catadioptric lens assembly is for processing at least twice internal reflections of an image light in the imaging lens assembly module, and for providing optical refractive power.
    Type: Application
    Filed: September 26, 2023
    Publication date: April 4, 2024
    Inventors: Lin-An CHANG, Chung Hao CHEN, Wen-Yu TSAI, Ming-Ta CHOU
  • Publication number: 20240112905
    Abstract: A method of forming a semiconductor device includes forming a mask layer over a substrate and forming an opening in the mask layer. A gap-filling material is deposited in the opening. A plasma treatment is performed on the gap-filling material. The height of the gap-filling material is reduced. The mask layer is removed. The substrate is patterned using the gap-filling material as a mask.
    Type: Application
    Filed: November 30, 2023
    Publication date: April 4, 2024
    Inventors: Ching-Yu Chang, Jei Ming Chen, Tze-Liang Lee
  • Publication number: 20240113237
    Abstract: The present disclosure provides a semiconductor structure and a method of manufacturing the same. The semiconductor structure includes a sensing device, a solar cell, and an interconnecting structure. The solar cell is disposed above the sensing device and is electrically connected to the sensing device. The interconnecting structure is disposed between the sensing device and the solar cell and has a first surface facing the solar cell and a second surface facing the sensing devices. The interconnecting structure comprises a first energy storage component and a second energy storage component. The first energy storage component is disposed closer to the first surface of the interconnecting structure than the second energy storage component.
    Type: Application
    Filed: January 10, 2023
    Publication date: April 4, 2024
    Inventors: FENG-CHIEN HSIEH, YUN-WEI CHENG, KUO-CHENG LEE, CHENG-MING WU, PING KUAN CHANG
  • Publication number: 20240113254
    Abstract: A semiconductor light emitting device includes a multi-quantum-well structure, a first capping layer, a second capping layer, and an electron barrier layer stacked in order. The multi-quantum-well structure includes a plurality of alternately-stacked potential barrier layers and potential well layers. The first capping layer is a semiconductor layer, and the second capping layer is a p-doped semiconductor layer. Each of the first and second capping layers has an aluminum mole fraction larger than that of each of the potential barrier layers, and the aluminum mole fraction of the first capping layer is larger than that of at least a portion of the electron barrier layer. A method for preparing the semiconductor light emitting device is also provided.
    Type: Application
    Filed: December 15, 2023
    Publication date: April 4, 2024
    Inventors: Yung-Ling LAN, Chan-Chan LING, Chi-Ming TSAI, Chia-Hung CHANG