Patents by Inventor A. Srinivas

A. Srinivas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250117833
    Abstract: The present invention is related to data processing methods and systems thereof. According to an embodiment, the present invention provides a method of processing claim deduction documents using a machine learning model. The process begins by accessing data files and extracting information from them, which is subsequently stored. This document information, along with the machine learning model trained on various document formats, is used to classify the data files and generate tabular data. From this tabular data, data objects are created and included in an output data file. The information from the output file is then used to update the data of the machine learning model, optimizing it for improved future document processing. There are other embodiments as well.
    Type: Application
    Filed: October 4, 2023
    Publication date: April 10, 2025
    Inventors: Debashish Sahu, Souranil De, Ritwik Upadhyay, Srinivas Rapaka, Susanta Kumar Sahoo, Lohit Vankina
  • Publication number: 20250120102
    Abstract: Package substrates with components included in cavities of glass cores are disclosed. An example apparatus includes: a glass core having a first opening and a second opening spaced apart from the first opening, the second opening having a greater width than the first opening. The example apparatus further includes a conductive material adjacent a first wall of the first opening; and a dielectric material adjacent a second wall of the second opening.
    Type: Application
    Filed: December 17, 2024
    Publication date: April 10, 2025
    Applicant: Intel Corporation
    Inventors: Brandon Christian Marin, Whitney Bryks, Gang Duan, Jeremy Ecton, Jason Gamba, Haifa Hariri, Sashi Shekhar Kandanur, Joseph Peoples, Srinivas Venkata Ramanuja Pietambaram, Mohammad Mamunur Rahman, Bohan Shan, Joshua James Stacey, Hiroki Tanaka, Jacob Ryan Vehonsky
  • Publication number: 20250117232
    Abstract: Generally, the present disclosure is directed to user interface understanding. More particularly, the present disclosure relates to training and utilization of machine-learned models for user interface prediction and/or generation. A machine-learned interface prediction model can be pre-trained using a variety of pre-training tasks for eventual downstream task training and utilization (e.g., interface prediction, interface generation, etc.).
    Type: Application
    Filed: December 19, 2024
    Publication date: April 10, 2025
    Inventors: Srinivas Kumar Sunkara, Xiaoxue Zang, Ying Xu, Lijuan Liu, Nevan Holt Wichers, Gabriel Overholt Schubiner, Jindong Chen, Abhinav Kumar Rastogi, Blaise Aguera-Arcas, Zecheng He
  • Publication number: 20250119861
    Abstract: Aspects presented herein may enable a UE to measure a subset of a bandwidth of PRSs, such that the UE may measure the PRSs without retuning bandwidth. In one aspect, a UE measures at least one quality metric associated with one or more channels for one or more PRSs. The UE receives, from a base station, the one or more PRSs via the one or more channels. The UE measures the one or more PRSs using at least one measuring BW of a plurality of measuring BWs, the plurality of measuring BWs being based on at least one of the measured at least one quality metric meeting a quality metric threshold, a BW for the one or more PRSs being greater than or outside of a BW for an ABWP, or a UE system BW being greater than the BW for the one or more PRSs.
    Type: Application
    Filed: August 31, 2022
    Publication date: April 10, 2025
    Inventors: Alexandros MANOLAKOS, Mukesh KUMAR, Srinivas YERRAMALLI
  • Publication number: 20250119368
    Abstract: The disclosure provides a method for monitoring tenant workloads in a multi-cloud environment. The method generally includes determining a first new workload for a first tenant is deployed on a first data plane associated with a first cloud platform in the multi-cloud environment; configuring a monitoring stack on a second data plane associated with a second cloud platform in the multi-cloud environment to collect first metrics data for the first new workload; and creating a network policy allow list including a source internet protocol (IP) address associated with the monitoring stack, wherein the network policy allow list is to be used by an ingress controller deployed on the first data plane to control ingress traffic to the first new workload, including at least ingress traffic from the monitoring stack intended for the first new workload.
    Type: Application
    Filed: March 15, 2024
    Publication date: April 10, 2025
    Inventors: AVI SHARMA, SRINIVAS BANOTH, NILABH NIKUNJ, GYANENDRA PRATAP SINGH
  • Publication number: 20250118121
    Abstract: A lock system includes an electronic lock comprising an electronic actuator and a retainer. The electronic actuator is configured to move the retainer from a first position to a second position. The lock system also includes a mechanical lock configured to be unlocked by a key. The lock system also includes an override actuator connected to the mechanical lock and the electronic lock. The override activator is configured to move the retainer from the first position to the second position when the unlocked mechanical lock is operated.
    Type: Application
    Filed: October 4, 2024
    Publication date: April 10, 2025
    Inventors: Cheuk Chi LAU, Xuejun LI, Naga Srinivas VANKADARI, Hilary FARNSWORTH
  • Publication number: 20250117354
    Abstract: A multi-lane integrated circuit transceiver device includes first and second integrated circuit dies having respective first and second pluralities of transmit block/receive block pairs. Each respective transmit block and each respective receive block in the first plurality of block pairs on the first die and the second plurality of block pairs on the second die includes respective digital clock generation circuitry. The device further includes digital clock distribution circuitry to distribute a digital clock signal output by one respective receive block, in one of the first and second pluralities of block pairs, to the transmit blocks in both of the pluralities of block pairs, for use as a baseline clock by the respective digital clock generation circuitry in each of the transmit blocks in both of the pluralities of block pairs. Where each plurality includes N block pairs, the two dies together form a single 2N-lane device.
    Type: Application
    Filed: December 19, 2024
    Publication date: April 10, 2025
    Inventors: Michael Lewis Takefman, Arash Farhoodfar, Srinivas Swaminathan, Belal Helal
  • Publication number: 20250117407
    Abstract: A method that includes receiving a first configuration and a second configuration that define a set of rules for matching and merging a set of source data objects that are associated with a tenant and that are received from a plurality of data sources. The method may further include generating a set of merged data objects from the set of source data objects based on an identification of matching values from fields of the set of source data objects and selecting a value for each field of each merged data object having multiple values. The method may further include generating a mapping between primary keys associated with each merged data object and corresponding primary keys of the source data objects. The method may further include storing the merged data objects and the mappings in a first datastore and a second datastore that is different from the first datastore.
    Type: Application
    Filed: December 17, 2024
    Publication date: April 10, 2025
    Inventors: Srinivas Tirupati, Amit Martu Kamat, Jawad Ahmed Ibrahim Katib, Raveendrnathan Loganathan, Xun Sun, Lingyu Deng, Prasanthi Oruganti, Hyun Seung Hong
  • Publication number: 20250119862
    Abstract: Disclosed are techniques for wireless signaling. In an aspect, a user equipment (UE) transmits, to a network component, an indication of a capability to estimate a carrier frequency offset (CFO) of the UE associated with radio frequency for sensing (RF-S) operations. In another aspect, the network component estimates the CFO of the UE (e.g., based on measurement information from the UE and/or wireless node(s)). In some designs, the network component further transmits, to the UE, the CFO of the UE (e.g., for CFO compensation associated with RF-S sensing operation(s)).
    Type: Application
    Filed: October 4, 2023
    Publication date: April 10, 2025
    Inventors: Marwen ZORGUI, Weimin DUAN, Preeti KUMARI, Srinivas YERRAMALLI
  • Patent number: 12274086
    Abstract: Methods and semiconductor devices are provided. A vertical junction field effect transistor (JFET) includes a substrate, an active region having a plurality of semiconductor fins, a source metal layer on an upper surface of the fins, a source metal pad layer coupled to the semiconductor fins through the source metal layer, a gate region surrounding the semiconductor fins, and a body diode surrounding the gate region.
    Type: Grant
    Filed: March 8, 2024
    Date of Patent: April 8, 2025
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Clifford Drowley, Andrew P. Edwards, Subhash Srinivas Pidaparthi, Ray Milano
  • Patent number: 12272071
    Abstract: A method (and system) of segmenting one or more histological structures in a tissue image represented by multi-parameter cellular and sub-cellular imaging data includes receiving coarsest level image data for the tissue image, wherein the coarsest level image data corresponds to a coarsest level of a multiscale representation of first data corresponding to the multi-parameter cellular and sub-cellular imaging data. The method further includes breaking the coarsest level image data into a plurality of non-overlapping superpixels, assigning each superpixel a probability of belonging to the one or more histological structures using a number of pre-trained machine learning algorithms to create a probability map, extracting an estimate of a boundary for the: one or more histological structures by applying a contour algorithm to the probability map, and using the estimate of the boundary to generate a refined boundary for the one or more histological structures.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: April 8, 2025
    Assignee: University of Pittsburgh—Of The Commonwealth System of Higher Education
    Inventors: Srinivas C. Chennubhotla, Om Choudhary, Akif Burak Tosun, Jeffrey Fine
  • Patent number: 12273364
    Abstract: A method protects a computer asset by identifying a particular signature, which is software that causes a particular gateway to block an intrusion from reaching a particular computer asset, and installs the particular signature on the particular gateway, thus protecting the computer asset from the intrusion.
    Type: Grant
    Filed: December 12, 2023
    Date of Patent: April 8, 2025
    Assignee: International Business Machines Corporation
    Inventors: Adam Paquin, Peyton Duncan, Kevin Shen, Jonathan Bees, Srinivas Babu Tummalapenta
  • Patent number: 12271289
    Abstract: A system, e.g., a system on a chip (SoC) includes a first domain including a first processor configured to boot the system; a second domain including a processing subsystem having a second processor; and isolation circuitry between the first domain and the second domain During boot-up of the system, the first processor provides code to the second domain. When the code is executed by the second processor, it configures the processing subsystem as either a safety domain or as a general-purpose processing domain. The safety domain may an external safety domain or an internal safety domain.
    Type: Grant
    Filed: January 3, 2024
    Date of Patent: April 8, 2025
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Venkateswar Kowkutla, Raghavendra Santhanagopal, Chunhua Hu, Anthony Frederick Seely, Nishanth Menon, Rajesh Kumar Vanga, Rejitha Nair, Siva Srinivas Kothamasu, Kazunobu Shin, Jason Peck, John Apostol
  • Patent number: 12271473
    Abstract: A method for processing trust and security for leased infrastructure includes: detecting a first audit event directed to the leased infrastructure; initiating, in response to detecting the first audit event, an execution of a first trust audit; making a first determination, based on a result of the first trust audit, that the first audit event is a verified event; and transmitting, in response to the first determination and to a computing device of a user leasing the leased infrastructure, first instructions for the computing device to display a first output notifying the user that the leased infrastructure is in a trusted domain.
    Type: Grant
    Filed: September 15, 2021
    Date of Patent: April 8, 2025
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Srinivas Gowda, Shyam Iyer, Syama Poluri
  • Patent number: 12271942
    Abstract: The present invention provides, in alternative embodiments, a computer architecture and/or computer implemented methods for account opening. In some embodiments, an integrated, component-based technology platform, globally standardized, business configurable account opening processes are separate and decoupled from the user interface screens and are directly manageable by business functionality and/or personnel. In various embodiments, the invention provides pause and resume, save and retrieve, cross-channel, metrics, audit tracking, data logging, and/or straight-through processing capabilities for account opening.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: April 8, 2025
    Assignee: HSBC TECHNOLOGY & SERVICES (USA) INC.
    Inventors: Paris F. Roselli, Ronald M. Lesandro, Michael J. Sullivan, Darren P. Loveday, Michael R. Antognoli, John P. Flood, Yilu He, Darrick R. Brooks, Srinivas Lakshman, Richard Gemma, Trevor Johnson, Sonu Gupta, Martin Hayes
  • Patent number: 12270872
    Abstract: Asymmetric, single-channel radio frequency (“RF”) coils are provided for use with portable or other low-field magnetic resonance imaging (“MRI”) systems. In general, the asymmetric, single-channel RF coils make use of asymmetric, optimized winding configurations in order to reduce B1+ inhomogeneities and to reduce signal sensitivity outside of the desired imaging field-of-view (“FOV”).
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: April 8, 2025
    Assignee: The General Hospital Corporation
    Inventors: Lawrence L. Wald, Clarissa Zimmerman-Cooley, Patrick C. McDaniel, Sai Abitha Srinivas
  • Patent number: 12272654
    Abstract: A method of forming alignment marks includes providing a III-V compound substrate having a device region and an alignment mark region, forming a hardmask layer having a first set of openings on the alignment mark region exposing a first surface portion of the III-V compound substrate and a second set of openings on the device region exposing a second surface portion of the III-V compound substrate, etching the exposed surface of the III-V compound substrate using the hardmask layer as a mask to form a plurality of trenches, and epitaxially regrowing a semiconductor layer in the trenches to form the alignment marks extending to a predetermined height over the processing surface of the III-V compound substrate.
    Type: Grant
    Filed: March 12, 2024
    Date of Patent: April 8, 2025
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Clifford Drowley, Ray Milano, Robert Routh, Subhash Srinivas Pidaparthi, Andrew P. Edwards
  • Patent number: 12272484
    Abstract: An inductor can be formed in a coreless electronic substrate from magnetic materials and/or fabrication processes that do not result in the magnetic materials leaching into plating and/or etching solutions/chemistries, and results in a unique inductor structure. This may be achieved by forming the inductors from magnetic ferrites. The formation of the electronic substrates may also include process sequences that prevent exposure of the magnetic ferrites to the plating and/or etching solutions/chemistries.
    Type: Grant
    Filed: March 4, 2021
    Date of Patent: April 8, 2025
    Assignee: Intel Corporation
    Inventors: Srinivas Pietambaram, Pooya Tadayon, Kristof Darmawikarta, Tarek Ibrahim, Prithwish Chatterjee
  • Patent number: 12272656
    Abstract: Embodiments disclosed herein include electronic packages and methods of fabricating electronic packages. In an embodiment, an electronic package comprises an interposer, where a cavity passes through the interposer, and a nested component in the cavity. In an embodiment, the electronic package further comprises a die coupled to the interposer by a first interconnect and coupled to the nested component by a second interconnect. In an embodiment, the first and second interconnects comprise a first bump, a bump pad over the first bump, and a second bump over the bump pad.
    Type: Grant
    Filed: October 13, 2023
    Date of Patent: April 8, 2025
    Assignee: Intel Corporation
    Inventors: Debendra Mallik, Ravindranath Mahajan, Robert Sankman, Shawna Liff, Srinivas Pietambaram, Bharat Penmecha
  • Patent number: 12272951
    Abstract: Provided is a system and method that can safely generate and execute an outage plan for a power grid based on severe weather-driven events. In one example, the method may include receiving predicted or current operational power system state data from a power grid and weather conditions associated with the power grid, identifying one or more nodes on the power grid to de-energize based on the operational state data and the current weather conditions, determining a sequence of instructions to perform to de-energize the one or more identified nodes based on the operational state data and the current weather conditions associated with the power grid, and generating an outage plan including mitigation steps for ensuring the stability and security of the power grid which includes the determined sequence of instructions to be executed and store the outage plan in the memory.
    Type: Grant
    Filed: April 19, 2022
    Date of Patent: April 8, 2025
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Saugata Swapan Biswas, Tushar, Arvind Mallikeswaran, Pradeep Kumar Manigilla, Srinivas Musunuri