Abstract: According to an embodiment of the present disclosure, a system is provided. The system includes a processor and a non-transitory computer-readable medium storing computing instructions. The instructions, when executed on the processor, perform: receiving user search queries and product items, the product items including metadata corresponding to product types, the product types comprising an error, and the error corresponding to one of the product items having a non-compliant product type; modifying the metadata corresponding to the product types based on a product type group to mitigate a computing system from displaying non-compliant material to a user; and in response to a product type of the product type group being the non-compliant product type, performing a computer vision prediction on an image of a product corresponding to the product type to detect a misclassification in the product type group. Other embodiments are disclosed.

Abstract: An apparatus includes a first switch and a second switch connected in series between an input voltage bus and ground, a bootstrap capacitor connected between a bootstrap voltage bus, and a common node of the first switch and the second switch, and a bias power control circuit configured to function as a switched capacitor bootstrap circuit when the apparatus is configured to operate in a high impedance PFM mode, and configured to function as an active bootstrap circuit when the apparatus is configured to operate in another operating mode.

Abstract: An order automatic interception method and a system.

Abstract: A power control circuit includes an alternating current power supply module, a power module, and a controller. The power module includes a bridgeless power factor correction circuit. A sampling apparatus in the alternating current power supply module samples a current signal output by an alternating current power supply or the power module, and outputs an obtained sampled signal to the controller. The controller controls on and off of a switch element in the alternating current power supply module based on the received sampled signal, and the controller switches off the switch element when the sampled signal includes a lightning surge signal. In addition, the controller is further configured to perform current metering on the sampled signal.

Abstract: Provided is a fringe line detection and phase unwrapping method and system based on an FL-Net convolutional neural network. The method includes: constructing the FL-Net convolutional neural network; detecting fringe lines of an input image by using the FL-Net convolutional neural network to obtain an image with detected fringe lines; performing circulation integral on the detected fringe lines to repair the detected fringe lines to thereby obtain an image with repaired fringe lines; performing path integral on the repaired fringe lines to unwrap the repaired fringe lines to thereby obtain an image with unwrapped fringe lines; and identifying error points of the unwrapped fringe lines by using the FL-Net convolutional neural network; and processing the error points. Specifically, an HDC method is used to replace a down-sampling method to avoid the loss of resolution, and residual connection is used to prevent the network from being too deep.

Abstract: An image processing method is provided. The method includes the step of analyzing brightness information of a portion of a source image. The method further includes the step of calculating the luminance control value based on the brightness information of the portion of the source image. The method further includes the step of adjusting the maximum display luminance of the display apparatus based on the luminance control value.

Abstract: A multilayer polymer capacitor (MLPC), including a casing, a multilayer core, an electroplated positive terminal, a first electroplated negative terminal, and a second electroplated negative terminal. The casing includes a casing body and a cover plate. The casing body is provided with an accommodating cavity, whose bottom is provided with a through hole. The multilayer core is provided in the accommodating cavity. An anode lead-out part and a cathode lead-out part are provided at two ends of the accommodating cavity, respectively. The electroplated positive terminal and the first electroplated negative terminal are provided on outer side surfaces of two ends of the casing, respectively. The second electroplated negative terminal is provided on an outer bottom surface of the casing, and is electrically connected to the multilayer core.

Abstract: A method, a device and an electronic equipment for determining the drop depth of screen leakage light, the method comprising: obtaining a sampling data based on a vertical synchronization signal; determining a first sampling sequence, as well as a second sampling sequence and/or a third sampling sequence based on the sampling data, the first sampling sequence is the sampling sequence of the drop zone of the screen leakage light drop waveform, the second sampling sequence is the sampling sequence on the left side of the drop zone of the screen leakage light drop waveform, and the third sampling sequence is the sampling sequence on the right side of the drop zone of the screen leakage light drop waveform; determining the drop depth based on the first sampling sequence, as well as the second sampling sequence and/or the third sampling sequence.

Abstract: A federated learning contribution calculation method comprises the following steps: a plurality of participants collaboratively developing a federated aggregation model by federated learning method according to their own local datasets; excluding the participation of at least one first participant in all participants, and then the remained participants collaboratively developing a contribution model by federated learning method; and, comparing the value of the first contribution model and the value of the federated model to obtain the contribution of the at least one first participant. The method of the present invention is capable of calculating the contribution(s) of single participant or multiple participants in the federated learning by few additional information and few additional calculations, so as to achieve the fair profit sharing according to the contributions.

Abstract: Disclosed are systems and techniques for training machine learning models. The techniques include generating, using a first automatic speech recognition (ASR) model, a first text output based on a vector representation of a first speech data and generating, using a second ASR model, a second text output, wherein the second ASR model adds noise to a vector representation of the first text output to obtain a noisy vector representation of the first text output and is trained to remove the noise from the noisy vector representation of the first text output. The techniques include calculating a first loss of the second ASR model based at least on a comparison between the second text output and the first text output and modifying learnable parameters of the second ASR model to improve an accuracy of the second ASR model.

Abstract: A method is proposed for machine learning (ML) model alignment. In the method, a first number of samples is generated by a target ML model based on samples selected from a set of samples. A sample comprises a question-answer pair. The set of samples is updated by adding at least a portion of the first number of samples to the set of samples. The target ML model is trained with at least a portion of the updated set of samples. In this way, the ML model self-generalization ability is unlocked to perform alignment with near-zero human supervision.

Abstract: The present disclosure relates to the technical field of semiconductors, and particularly discloses a preparation method of a chip package structure and a package structure. The preparation method of a chip package structure includes the following steps: providing a wafer and producing conductive structures on the wafer based on chip distribution; performing wafer dicing based on the chip distribution to obtain chip monomers; producing plastic package bodies including a plurality of chip monomers based on the chip monomers; and producing electric connection structures on the plastic package bodies. The preparation method of a chip package structure omits the processes of laser drilling and later metal layer covering, eliminates a deviation caused by laser drilling, and improves the processing precision of the package structure, thereby improving the yield of products, simplifying the whole chip packaging process, and effectively improving the packaging efficiency.

Abstract: Provided are semiconductor devices and methods for fabricating such devices. An exemplary method includes forming a fin structure over a semiconductor material; forming a sacrificial layer over the semiconductor material; removing a portion of the fin structure and an overlying portion of the sacrificial layer located over the portion of the fin structure to form a trench; forming an insulation structure in the trench, wherein an adjacent portion of the sacrificial layer is adjacent an end wall of the insulation structure; removing the adjacent portion to form a cavity partially defined by the end wall; lining the cavity with a liner, wherein an end portion of the liner is located on the end wall of the insulation structure; filling the cavity with a fill material; removing the end portion of the liner to form an opening; and forming an end isolation structure in the opening.

Abstract: A method includes forming a first semiconductor channel region and a second semiconductor channel region, with the second semiconductor channel region overlapping the first semiconductor channel region, forming a first gate dielectric on the first semiconductor channel region, and forming a second gate dielectric on the second semiconductor channel region. A dipole dopant is incorporated into a first one of the first gate dielectric and the second gate dielectric to a higher atomic percentage, and a second one of the first gate dielectric and the second gate dielectric has a lower atomic percentage of the dipole dopant. A gate electrode is formed on both of the first gate dielectric and the second gate dielectric. The gate electrode and the first gate dielectric form parts of a first transistor, and the gate electrode and the second gate dielectric form parts of a second transistor.

Abstract: A method of forming a chip package is provided. The method may include: arranging an elastic thermal interface material over a semiconductor chip, the elastic thermal interface material being configured to transfer heat from the chip to an outside; arranging a mold around the elastic thermal interface material and at least partially around the semiconductor chip, thereby compressing the elastic thermal interface material with the mold; and filling the mold with a packaging material.

Abstract: An antenna device including an antenna structure, a base, an elastic bracket, a restriction unit, and a fastener is provided. The base is connected to the antenna structure. The base includes a plurality of grooves. The elastic bracket includes a plurality of elastic legs. Each of the elastic legs includes a free end. The free end is guided by the corresponding groove. The elastic legs abut the restriction unit. The fastener affix the restriction unit to the base. At least a portion of the elastic bracket is disposed between the restriction unit and the base.

Abstract: A flexible display device includes a substrate which is bendable or rollable based on an axis, a plurality of display elements on the substrate, and a plurality of thin-film encapsulation patterns which covers the plurality of display elements, where the plurality of thin-film encapsulation patterns includes a first thin-film encapsulation pattern and a second thin-film encapsulation pattern, which are apart from each other in a direction crossing the axis, and each of the first thin-film encapsulation pattern and the second thin-film encapsulation pattern extends in parallel to the axis of the flexible display device.

Abstract: This application discloses an ultra-wideband antenna array and an electronic device. The antenna array includes a first antenna unit, a second antenna unit, and a third antenna unit, where a first distance and a second distance are less than a third distance. The first distance is a distance between the first antenna unit and the third antenna unit, the second distance is a distance between the second antenna unit and the third antenna unit, and the third distance is a distance between the first antenna unit and the second antenna unit. Phase centers of the first antenna unit, the second antenna unit, and the third antenna unit are deviated from geometric centers.

Abstract: A head-mounted device may have an inner display that displays images for a user and an outer display that informs nearby people of the status of the user and inner display. For example, the outer display may display an image of a face, an abstract layer, or both, depending on whether the inner display is operating in passthrough mode, mixed reality mode, or virtual reality mode. An ambient light sensor in the head-mounted device may be used to measure the brightness and color of ambient light. The white point of the face layer on the outer display may be adapted to the color of ambient light, whereas the white point of the abstract layer on the outer display may remain fixed. The white point of a display may be a correlated color temperature setting (e.g., measured in degrees Kelvin) that determines the warmth or coolness of displayed colors.

Abstract: Disclosed herein is an improved low-profile rotary light switch for controlling a lighting apparatus. In some embodiments, the rotary light switch can comprise a rotary potentiometer mounted to a PCB and comprising a keyed shaft protruding through the opening of a top switch enclosure. The rotary light switch can further comprise a button chassis comprising a keyhole passage defined therethrough. At least part of the keyed shaft can protrude into the keyhole passage when the button chassis is coupled to the keyed shaft by the fastener. The rotary switch can also comprise a button top configured to be non-detachably coupled to the button chassis when the button top is pressed onto the button chassis. Rotating the button top can rotate the button chassis and keyed shaft such that the brightness or intensity of the lighting load is controllable via rotation of the button top.