Abstract: The present invention is directed toward a texture combine circuit for generating fragment graphics data for a pixel in a graphics processing system. The texture combine circuit includes at least one texture combine unit and is coupled to receive graphics data, such as a plurality of texture graphics data, and perform user selected graphics combine operations on a set of input data selected from the plurality of texture graphics data to produce the fragment graphics data for the pixel. The texture combine circuit may include several texture combine units in a cascade connection, where each texture combine unit is coupled to receive the plurality of texture graphics data and the resultant output value of the previous texture combine units in the cascade.

Abstract: A graphics processing system including a cache memory circuit coupled to the graphics processor and the address and data busses for storing graphics data according to a respective address. The cache memory includes first and second memories coupled together by a plurality of activation lines. The first memory has a corresponding plurality of address detection units to store addresses and provide activation signals in response to receiving a matching address. The second memory includes a corresponding plurality of data storage locations. Each data storage location is coupled to a respective one of the plurality of address storage locations by a respective activation line to provide graphics data in response to receiving an activation signal from the respective address storage location.

Abstract: A cache for a graphics system storing both an address tag and an identification number for each block of data stored in the data cache. An address and identification number of a requested block of data is provided to the cache, and is checked against all of the address and identification number entries present. A block of data is provided if both the address and the identification number of the requested data matches an entry in the cache. However, if the address of the requested data is not present, or if the address matches an entry but the associated identification number does not match, a cache miss occurs, and the requested graphics data must be retrieved from a system memory. The address and identification number are updated, and the requested data replaces the former graphics data in the data cache. As a result, a block of data stored in the cache having the same address as the requested data, but having data that is invalid, can be invalidated without invalidating the entire cache.

Abstract: A cache for a graphics system storing both an address tag and an identification number for each block of data stored in the data cache. An address and identification number of a requested block of data is provided to the cache, and is checked against all of the address and identification number entries present. A block of data is provided if both the address and the identification number of the requested data matches an entry in the cache. However, if the address of the requested data is not present, or if the address matches an entry but the associated identification number does not match, a cache miss occurs, and the requested graphics data must be retrieved from a system memory. The address and identification number are updated, and the requested data replaces the former graphics data in the data cache. As a result, a block of data stored in the cache having the same address as the requested data, but having data that is invalid, can be invalidated without invalidating the entire cache.

Abstract: A direct memory access (DMA) controller for controlling memory access operations in a memory. During a memory access operation, the DMA controller executes a chain of DMA commands stored in a memory and having a respective address. The DMA controller can enter a self-linking mode where additional DMA commands can be appended to the end of the command chain without terminating the memory access operation, regardless of whether the last DMA command of the command chain has been executed by the DMA controller. The self-linking mode is entered when a link-address provided by the last DMA command matches a code. The code to cause the DMA controller to enter the self-linking mode may be a link address which points to the last executed DMA command, or alternatively, a predetermined bit pattern. The DMA controller exits the self-linking command and continues the memory access operation upon detecting a new link address for a new DMA command that is to be appended to the command chain.

Abstract: A computer graphics method and apparatus allows designer control over the rendering of objects and scenes, in a rendering system using ray tracing for example. A modeling system is adapted to accept rules for controlling how certain objects affect the appearance of certain other objects. In a ray tracing implementation, rules are specified by ray type and can be specified as either “including” all but certain objects or “excluding” specific objects for any given object. A rendering system extracts these rules from a bytestream or other input including other graphics data and instructions, and populates lists for internal use by other components of the rendering system. A ray tracer in the rendering system is adapted to consult the list when performing ray tracing, so as to enforce the rendering control specified by the content creator when the objects and scene are rendered.

Abstract: The number of computations performed in rendering graphics is reduced by computing certain terms only at the beginning of each scanline. A scanline gradient is calculated once at the beginning of each scanline for each of two texture values with respect to the x-coordinate of the scanline. Following the scanline gradient calculations at the beginning of each scanline, a pixel gradient is calculated for each pixel of the scanline with respect to the y-coordinate of the scanline. The sum of the squares of the scanline gradients and the pixel gradients are compared, and the larger of the two quantities is selected to be a maximum Rho constant term for the corresponding pixel, wherein the maximum Rho constant is used to select a texture map for rendering the corresponding pixel. Furthermore, at the beginning of each scanline, a pixel gradient may be calculated for each of two texture values for a first pixel of the scanline with respect to the y-coordinate of the scanline.

Abstract: A method and system for providing surface texture in a graphics image rendered by a graphics processing system. Color values of a pixel having a normal vector normal to a surface in which the pixel is located are calculated based on a perturbed normal vector. The perturbed normal vector is displaced from the normal vector by a displacement equal to the sum of a first vector tangent to the surface at the location of the pixel scaled by a first scale factor and a first displacement value, and a second vector tangent to the surface at the location of the pixel and scaled by a second scale factor and a second displacement value, the second vector perpendicular to the first vector. The displacement values are representative of partial derivatives of a function defining a texture applied to the surface and the scale factors are used to scale the magnitude of the resulting perturbed normal. The color value for the pixel being rendered will be based on the perturbed normal vector instead of the normal vector.

Abstract: Graphics display performance is significantly improved by compressing pixel information, by aligning the 8, 16 or 32 bit pixels transferred over a 32-bit Peripheral Component Interface (PCI) bus with the pixels in the display memory, and by avoiding moves of pixel data within display memory. Compression is achieved by not transferring data for pixels that are not modified by the transfer. Rather, a count of unmodified pixel bytes to skip precedes each set of pixel data for contiguous pixels that are modified. Alignment is achieved by ensuring that the boundaries between words within the pixel set transferred matches those within the corresponding target pixels in the display memory. This alignment significantly speeds up modifying pixel data within the display memory. The burden of ensuring this alignment is placed on the applications software that initiates the transfer.