Abstract: A superconductor junction includes a normal metal layer having a first side and a second side, an insulating layer overlying the second side of the normal metal layer, and a first superconductor layer formed of a first superconductor material that overlies a side of the insulating layer opposite the side that overlies the normal metal layer. The superconductor junction further includes a second superconductor layer formed of a second superconductor material with a first side overlying a side of the first superconductor material opposite the side that overlies the insulating layer. The second superconductor material has a higher diffusion coefficient than the first superconductor material and/or the second superconductor material has a lower recombination coefficient than the first superconductor metal layer. A normal metal layer quasiparticle trap is coupled to a second side of the second superconductor layer.

Abstract: A solid state cooler device is disclosed that comprises a first normal metal pad, a first aluminum layer and a second aluminum layer disposed on the first normal metal pad and separated from one another by a gap, a first aluminum oxide layer formed on the first aluminum layer, and a second aluminum oxide layer formed on the second aluminum layer, and a first superconductor pad disposed on the first aluminum oxide layer and a second superconductor pad disposed on the second aluminum oxide layer. The device further comprises a first conductive pad coupled to the first superconductor pad, and a second conductive pad coupled to the second superconductor pad, wherein hot electrons are removed from the first normal metal pad when a bias voltage is applied between the first conductive pad and the second conductive pad.

Abstract: A superconductor junction includes a normal metal layer having a first side and a second side, an insulating layer overlying the second side of the normal metal layer, and a first superconductor layer formed of a first superconductor material that overlies a side of the insulating layer opposite the side that overlies the normal metal layer. The superconductor junction further includes a second superconductor layer formed of a second superconductor material with a first side overlying a side of the first superconductor material opposite the side that overlies the insulating layer. The second superconductor material has a higher diffusion coefficent than the first superconductor material and/or the second superconductor material has a lower recombination coefficent than the first superconductor metal layer. A normal metal layer quasiparticle trap is coupled to a second side of the second superconductor layer.

Abstract: A solid state cooler device is disclosed that comprises a first normal metal pad, a first aluminum layer and a second aluminum layer disposed on the first normal metal pad and separated from one another by a gap, a first aluminum oxide layer formed on the first aluminum layer, and a second aluminum oxide layer formed on the second aluminum layer, and a first superconductor pad disposed on the first aluminum oxide layer and a second superconductor pad disposed on the second aluminum oxide layer. The device further comprises a first conductive pad coupled to the first superconductor pad, and a second conductive pad coupled to the second superconductor pad, wherein hot electrons are removed from the first normal metal pad when a bias voltage is applied between the first conductive pad and the second conductive pad.

Abstract: A solid state cooler device is disclosed that comprises a first normal metal pad, a first aluminum layer and a second aluminum layer disposed on the first normal metal pad and separated from one another by a gap, a first aluminum oxide layer formed on the first aluminum layer, and a second aluminum oxide layer formed on the second aluminum layer, and a first superconductor pad disposed on the first aluminum oxide layer and a second superconductor pad disposed on the second aluminum oxide layer. The device further comprises a first conductive pad coupled to the first superconductor pad, and a second conductive pad coupled to the second superconductor pad, wherein hot electrons are removed from the first normal metal pad when a bias voltage is applied between the first conductive pad and the second conductive pad.

Abstract: A solid state cooler device is provided that includes a substrate, a first and second conductive pad disposed on the substrate, a first and second superconductor pad each having a side with a plurality of conductive pad contact interfaces spaced apart from one another and being in contact with a surface of respective first and second conductive pads, and a first and second insulating layer disposed between respective first and second superconductor pads, and respective ends of a normal metal layer. A bias voltage is applied between one of a first conductive pad or first superconductor pad and one of the second conductive pad or the second superconductor pad to remove hot electrons from the normal metal layer, and the contact area of the plurality of first and second conductive pad contact interfaces inhibits the transfer of heat back to the first and second superconductor pads.

Abstract: An integrated circuit is provided that comprises a first thermal sink layer, a first ground plane associated with a first set of circuits that have a first operational temperature requirement, a first thermally conductive via that couples the first ground plane to the first thermal sink layer, a second thermal sink layer, a second ground plane associated with a second set of circuits that have a second operational temperature requirement that is higher than the first operational temperature requirement, and a second thermally conductive via that couples the second ground plane to the second thermal sink layer. The first thermal sink layer is cooled at a first temperature to maintain the first set of circuits at the first operational temperature requirement and the second thermal sink layer is cooled at a second temperature to maintain the second set of circuits at the second operational temperature requirement.

Abstract: A solid state cooler device is disclosed that comprises a first normal metal pad, a first aluminum layer and a second aluminum layer disposed on the first normal metal pad and separated from one another by a gap, a first aluminum oxide layer formed on the first aluminum layer, and a second aluminum oxide layer formed on the second aluminum layer, and a first superconductor pad disposed on the first aluminum oxide layer and a second superconductor pad disposed on the second aluminum oxide layer. The device further comprises a first conductive pad coupled to the first superconductor pad, and a second conductive pad coupled to the second superconductor pad, wherein hot electrons are removed from the first normal metal pad when a bias voltage is applied between the first conductive pad and the second conductive pad.

Abstract: An integrated circuit is provided that comprises a first thermal sink layer, a first ground plane associated with a first set of circuits that have a first operational temperature requirement, a first thermally conductive via that couples the first ground plane to the first thermal sink layer, a second thermal sink layer, a second ground plane associated with a second set of circuits that have a second operational temperature requirement that is higher than the first operational temperature requirement, and a second thermally conductive via that couples the second ground plane to the second thermal sink layer. The first thermal sink layer is cooled at a first temperature to maintain the first set of circuits at the first operational temperature requirement and the second thermal sink layer is cooled at a second temperature to maintain the second set of circuits at the second operational temperature requirement.

Abstract: A solid state cooler device is disclosed that includes a first superconductor shunt, a first normal metal pad disposed on the first superconductor shunt, and a first insulator layer and a second insulator layer disposed on the normal metal pad and separated from one another by a gap. The solid state cooler device also includes a first superconductor pad disposed on the first insulator layer and a second superconductor pad disposed on the second insulator layer, a first conductive pad coupled to the first superconductor pad, and a second conductive pad coupled to the second superconductor pad. Hot electrons are removed from the first normal metal pad when a bias voltage is applied between the first conductive pad and the second conductive pad, wherein the first superconductor shunt facilitates even current distribution through the device.

Abstract: A solid state cooler device is provided that includes a substrate, a first and second conductive pad disposed on the substrate, a first and second superconductor pad each having a side with a plurality of conductive pad contact interfaces spaced apart from one another and being in contact with a surface of respective first and second conductive pads, and a first and second insulating layer disposed between respective first and second superconductor pads, and respective ends of a normal metal layer. A bias voltage is applied between one of a first conductive pad or first superconductor pad and one of the second conductive pad or the second superconductor pad to remove hot electrons from the normal metal layer, and the contact area of the plurality of first and second conductive pad contact interfaces inhibits the transfer of heat back to the first and second superconductor pads.

Abstract: An integrated circuit is provided that comprises a thermal sink layer, a first ground plane associated with a first set of circuits that have a first operational temperature requirement, and a first thermally conductive via that couples the first ground plane to the thermal sink layer. The circuit further comprises a second ground plane associated with a second set of circuits that have a second operational temperature requirement that is higher than the first operational temperature requirement, and a second thermally conductive via that couples the second ground plane to the thermal sink layer, wherein the first thermally conductive via has a greater volume of thermal conductive material than the second thermally conductive via to remove heat from the first set of circuits with less gradient than the second set of circuits.

Abstract: An integrated circuit is provided that comprises a first thermal sink layer, a first ground plane associated with a first set of circuits that have a first operational temperature requirement, a first thermally conductive via that couples the first ground plane to the first thermal sink layer, a second thermal sink layer, a second ground plane associated with a second set of circuits that have a second operational temperature requirement that is higher than the first operational temperature requirement, and a second thermally conductive via that couples the second ground plane to the second thermal sink layer. The first thermal sink layer is cooled at a first temperature to maintain the first set of circuits at the first operational temperature requirement and the second thermal sink layer is cooled at a second temperature to maintain the second set of circuits at the second operational temperature requirement.

Abstract: A superconducting structure is provided that comprises a first superconducting device coupled to a second superconducting device employing a plurality of superconducting bump bond structures. Each of the plurality of superconducting bump bond structures comprise a first normal metal layer disposed on the top surface of a given one of a plurality of first contact pads, a second normal metal layer disposed on the top surface of a given one of a plurality of second contact pads, and a superconducting metal layer disposed between the first normal metal layer and the second normal metal layer. The metal thicknesses of each of the first normal metal layer, the second normal metal layer, and the specific material of the superconducting metal and normal metal are selected to inhibit the transfer of heat between the first superconducting device and the second superconducting device.

Abstract: An integrated circuit is provided that comprises a first ground plane associated with a first set of circuits that have a first operational temperature requirement, and a second ground plane associated with a second set of circuits that have a second operational temperature requirement that is higher than the first operational temperature requirement. The second ground plane is substantially thermally isolated from the first ground plane. A superconducting coupler electrically couples the first ground plane and the second ground plane while maintaining relative thermal isolation between the first ground plane and the second ground plane.

Abstract: An integrated circuit is provided that comprises a thermal sink layer, a first ground plane associated with a first set of circuits that have a first operational temperature requirement, and a first thermally conductive via that couples the first ground plane to the thermal sink layer. The circuit further comprises a second ground plane associated with a second set of circuits that have a second operational temperature requirement that is higher than the first operational temperature requirement, and a second thermally conductive via that couples the second ground plane to the thermal sink layer, wherein the first thermally conductive via has a greater volume of thermal conductive material than the second thermally conductive via to remove heat from the first set of circuits with less gradient than the second set of circuits.

Abstract: An integrated circuit is provided that comprises a first ground plane associated with a first set of circuits that have a first operational temperature requirement, and a second ground plane associated with a second set of circuits that have a second operational temperature requirement that is higher than the first operational temperature requirement. The second ground plane is substantially thermally isolated from the first ground plane. A superconducting coupler electrically couples the first ground plane and the second ground plane while maintaining relative thermal isolation between the first ground plane and the second ground plane.

Abstract: An integrated circuit is provided that comprises a thermal sink layer, a first ground plane associated with a first set of circuits that have a first operational temperature requirement, and a first thermally conductive via that couples the first ground plane to the thermal sink layer. The circuit further comprises a second ground plane associated with a second set of circuits that have a second operational temperature requirement that is higher than the first operational temperature requirement, and a second thermally conductive via that couples the second ground plane to the thermal sink layer, wherein the first thermally conductive via has a greater volume of thermal conductive material than the second thermally conductive via to remove heat from the first set of circuits with less gradient than the second set of circuits.

Abstract: An integrated circuit is provided that comprises a thermal sink layer, a first ground plane associated with a first set of circuits that have a first operational temperature requirement, and a first thermally conductive via that couples the first ground plane to the thermal sink layer. The circuit further comprises a second ground plane associated with a second set of circuits that have a second operational temperature requirement that is higher than the first operational temperature requirement, and a second thermally conductive via that couples the second ground plane to the thermal sink layer, wherein the first thermally conductive via has a greater volume of thermal conductive material than the second thermally conductive via to remove heat from the first set of circuits with less gradient than the second set of circuits.

Abstract: One example includes a device that is comprised of a plurality of printed circuit boards, a plurality of vias, and a plurality of castellations. The plurality of printed circuit boards are laminated together, at least some of the plurality of printed circuit boards including a dielectric panel and a plurality of conductor pads. The plurality of vias, through the plurality of conductor pads, include a conductive material to respectively electrically couple the plurality of conductor pads with each other. The plurality of castellations, on at least one side of the plurality of printed circuit boards, to electrically couple each of a plurality of contact pins of an integrated circuit socket with respective contact pads of the plurality of conductor pads.