Abstract: An electrophoretic display having a plurality of display pixels, each of the plurality of display pixels may include a pixel electrode for driving the display pixel, a single thin film transistor (TFT) coupled to the pixel electrode for transmitting waveforms to the pixel electrode, a front plane laminate (FPL) coupled to the single thin film transistor, and a storage capacitor coupled to the pixel electrode and placed in parallel with the FPL, where the storage capacitor is configured to be sufficiently ohmically conductive to allow the discharge of remnant voltages from the FPL through the storage capacitor.

Abstract: Methods, apparatus, and systems related to light detection and ranging (LIDAR) are described. In one example aspect, a LIDAR apparatus includes a light emitter configured to generate, according to a first electrical pulse signal, a pulse light signal. The first electrical pulse signal comprises a first set of non-uniformly spaced pulses. The apparatus includes a receiver configured to convert returned light signals from the object into electrical signals and a filtering subsystem in communication with the receiver, configured to receive the electrical signals from the receiver and remove a point from a set of points representing at least a partial surface of the object as noise by determining whether there is a coherence between the point and corresponding neighboring points of the point along at least a first direction and a second direction of the set of points.

Abstract: Methods and systems for combining return signals from multiple channels of a LIDAR measurement system are described herein. In one aspect, the outputs of multiple receive channels are electrically coupled before input to a single channel of an analog to digital converter. In another aspect, a DC offset voltage is provided at the output of each transimpedance amplifier of each receive channel to improve measured signal quality. In another aspect, a bias voltage supplied to each photodetector of each receive channel is adjusted based on measured temperature to save power and improve measurement consistency. In another aspect, a bias voltage supplied to each illumination source of each transmit channel is adjusted based on measured temperature. In another aspect, a multiplexer is employed to multiplex multiple sets of output signals of corresponding sets of receive channels before analog to digital conversion.

Abstract: The present invention provides a method for removing cysteine caps from antibodies and re-capping the antibodies with cysteine molecules. The methods include, inter alia, culturing a host cell comprising a protein molecule having at least one capped engineered cysteine residue, and contacting the cell culture with cystine. Dissolved oxygen levels can be manipulated in the cell culture to further enhance the removal and re-capping process.

Abstract: Methods and systems for combining return signals from multiple channels of a LIDAR measurement system are described herein. In one aspect, the outputs of multiple receive channels are electrically coupled before input to a single channel of an analog to digital converter. In another aspect, a DC offset voltage is provided at the output of each transimpedance amplifier of each receive channel to improve measured signal quality. In another aspect, a bias voltage supplied to each photodetector of each receive channel is adjusted based on measured temperature to save power and improve measurement consistency. In another aspect, a bias voltage supplied to each illumination source of each transmit channel is adjusted based on measured temperature. In another aspect, a multiplexer is employed to multiplex multiple sets of output signals of corresponding sets of receive channels before analog to digital conversion.

Abstract: Methods, apparatus, and systems related to light detection and ranging (LIDAR) are described. In one example aspect, a LIDAR apparatus includes a light emitter configured to generate, according to a first electrical pulse signal, a pulse light signal. The first electrical pulse signal comprises a first set of non-uniformly spaced pulses. The apparatus includes a receiver configured to convert returned light signals from the object into electrical signals and a filtering subsystem in communication with the receiver, configured to receive the electrical signals from the receiver and remove a point from a set of points representing at least a partial surface of the object as noise by determining whether there is a coherence between the point and corresponding neighboring points of the point along at least a first direction and a second direction of the set of points.

Abstract: The present invention provides a method for removing cysteine caps from antibodies and re-capping the antibodies with cysteine molecules. The methods include, inter alia, culturing a host cell comprising a protein molecule having at least one capped engineered cysteine residue, and contacting the cell culture with cystine. Dissolved oxygen levels can be manipulated in the cell culture to further enhance the removal and re-capping process.

Abstract: Methods and systems for combining return signals from multiple channels of a LIDAR measurement system are described herein. In one aspect, the outputs of multiple receive channels are electrically coupled before input to a single channel of an analog to digital converter. In another aspect, a DC offset voltage is provided at the output of each transimpedance amplifier of each receive channel to improve measured signal quality. In another aspect, a bias voltage supplied to each photodetector of each receive channel is adjusted based on measured temperature to save power and improve measurement consistency. In another aspect, a bias voltage supplied to each illumination source of each transmit channel is adjusted based on measured temperature. In another aspect, a multiplexer is employed to multiplex multiple sets of output signals of corresponding sets of receive channels before analog to digital conversion.

Abstract: A semiconductor device with split gate flash memory cell structure includes a substrate having a first area and a second area, at least a first cell formed in the first area and at least a second cell formed in the second area. The first cell includes a first dielectric layer formed on the substrate, a floating gate (FG), a word line and an erase gate (EG) formed on the first dielectric layer, an interlayer dielectric (ILD) layer, an inter-gate dielectric layer and a control gate (CG). The FG is positioned between the word line and the EG, and the ILD layer is formed on the word line and the EG, wherein the ILD layer has a trench exposing the FG. The inter-gate dielectric layer is formed in the trench as a liner, and the CG formed in the trench is surrounded by the inter-gate dielectric layer.

Abstract: A semiconductor device with split gate flash memory cell structure includes a substrate having a first area and a second area, at least a first cell formed in the first area and at least a second cell formed in the second area. The first cell includes a first dielectric layer formed on the substrate, a floating gate (FG), a word line and an erase gate (EG) formed on the first dielectric layer, an interlayer dielectric (ILD) layer, an inter-gate dielectric layer and a control gate (CG). The FG is positioned between the word line and the EG, and the ILD layer is formed on the word line and the EG, wherein the ILD layer has a trench exposing the FG. The inter-gate dielectric layer is formed in the trench as a liner, and the CG formed in the trench is surrounded by the inter-gate dielectric layer.

Abstract: A flash cell includes a gate and an erase gate. The gate is disposed on a substrate, wherein the gate includes a control gate on the substrate and a floating gate having a tip between the substrate and the control gate. The erase gate is disposed beside the gate, wherein the tip points toward the erase gate. The present invention also provides a flash cell forming process including the following steps. A gate is formed on a substrate, wherein the gate includes a floating gate on the substrate. An implantation process is performed on a side part of the floating gate, thereby forming a first doped region in the side part. At least a part of the first doped region is oxidized, thereby forming a floating gate having a tip.

Abstract: A flash cell includes a gate and an erase gate. The gate is disposed on a substrate, wherein the gate includes a control gate on the substrate and a floating gate having a tip between the substrate and the control gate. The erase gate is disposed beside the gate, wherein the tip points toward the erase gate. The present invention also provides a flash cell forming process including the following steps. A gate is formed on a substrate, wherein the gate includes a floating gate on the substrate. An implantation process is performed on a side part of the floating gate, thereby forming a first doped region in the side part. At least a part of the first doped region is oxidized, thereby forming a floating gate having a tip.

Abstract: A non-volatile memory cell includes a substrate, an erase gate disposed on the substrate and having a top plane, two floating gates disposed respectively at both sides of the erase gate, two control gates disposed respectively on two floating gates, and two select gates disposed respectively at outer sides of the two floating gates, where the two select gates have tilted top planes which are symmetric to each other.

Abstract: Semiconductor devices and methods for forming a semiconductor device are presented. The method includes providing a substrate having a device component with a contact region. A contact dielectric layer is formed on the substrate, covering the substrate and device component. The contact dielectric layer includes a lower contact dielectric layer, an intermediate contact dielectric etch stop layer formed on the lower contact dielectric layer, and an upper contact dielectric layer formed on the intermediate contact dielectric etch stop layer. A contact opening is formed through the contact dielectric layer. The contact opening has an upper contact sidewall profile in the upper contact dielectric layer and a lower tapered contact sidewall profile in the lower contact dielectric layer. The tapered sidewall profile prevents shorting with the device component.

Abstract: Integrated circuits with dummy contacts and methods for fabricating such integrated circuits are provided. The method includes forming an interlayer dielectric overlying an electronic component and a substrate, wherein the interlayer dielectric has an interlayer dielectric top surface. An active contact is formed through the interlayer dielectric and forms an electrical connection with the electronic component. A dummy contact is formed within the interlayer dielectric where the dummy contact extends to a dummy contact termination point between the interlayer dielectric top surface and the substrate such that an insulator is positioned between the dummy contact termination point and the electronic component.

Abstract: Semiconductor devices and methods for forming a semiconductor device are presented. The method includes providing a substrate having a device component with a contact region. A contact dielectric layer is formed on the substrate, covering the substrate and device component. The contact dielectric layer includes a lower contact dielectric layer, an intermediate contact dielectric etch stop layer formed on the lower contact dielectric layer, and an upper contact dielectric layer formed on the intermediate contact dielectric etch stop layer. A contact opening is formed through the contact dielectric layer. The contact opening has an upper contact sidewall profile in the upper contact dielectric layer and a lower tapered contact sidewall profile in the lower contact dielectric layer. The tapered sidewall profile prevents shorting with the device component.

Abstract: Provided are methods of preparing a textured surface on a thermoplastic material that include treating the material with a plasma and subsequently shrinking the substrate to induce formation of textures.

Abstract: Provided are methods of preparing a textured surface on a thermoplastic material that include treating the material with a plasma and subsequently shrinking the substrate to induce formation of textures.

Abstract: A pulse transformer includes a core unit and a coil unit. The core unit includes an annular core part, and an annular choke part that is disposed in contact with the annular corepart. The coil unit includes a plurality of coils, each of which is wound around both of the annular core part and the annular choke part.

Abstract: A pulse transformer includes a core unit and a coil unit. The core unit includes an annular core part, and an annular choke part that is disposed in contact with the annular core part. The coil unit includes a plurality of coils, each of which is wound around both of the annular core part and the annular choke part.