Abstract: Methods, systems, and computer products are presented herein for generating a clock signal using an on-chip ultra-low power (ULP) RC oscillator. An on-chip ultra-low power (ULP) RC oscillator comprises a first comparator, a second comparator, and a flip flop. The first comparator comprises a first input electrically coupled to a first bias voltage generation circuit and a second input electrically coupled to a first capacitor circuit. Each of the first bias voltage and the second bias voltage directly varies with a thermal voltage. A flip-flop is electrically coupled to the first comparator and the second comparator. The flip-flop is configured to generate a clock signal based on the first and the second comparator output signals.

Abstract: Methods, systems, and computer products are presented herein for determining temperature using ultra-low power temperature sensing systems. An ultra-low power (ULP) temperature sensing system comprises a proportional to absolute temperature (PTAT) current source, a switched-capacitor converter electrically coupled to the PTAT current source, and a ULP analog-to-digital converter (ADC) electrically coupled to the PTAT current source and the switched-capacitor converter. The PTAT current source is configured to generate a PTAT current that varies with an operating temperature. The switched-capacitor converter is configured to generate an analog voltage signal based on the PTAT current. The ULP ADC is configured to output a digital voltage value corresponding to the analog voltage signal.

Abstract: Methods, systems, and computer program products are presented herein for circuit timing using ultra-low power (ULP) timing circuit systems. A ULP timing circuit system comprises a receiver circuit, phase lock loop (PLL) circuit, crystal oscillator (XO) circuit, temperature sensing and calibration circuit, and temperature compensation circuit. The receiver circuit is configured to receive a reference clock signal. The XO circuit is configured to produce an output clock signal. The PLL circuit is configured to produce a control signal based on the reference clock signal and output clock signal. The temperature compensation circuit is configured to produce a compensation signal based on an operating temperature. The temperature sensing and calibration circuit is configured to sense the operating temperature and to calibrate the XO circuit based on the operating temperature, control signal, and compensation signal to lock a frequency of the output clock signal to the reference clock signal.

Abstract: Methods, systems, and computer program products are presented herein for obfuscating analog circuits using switched phase circuits. In particular, methods, systems, and computer program products using a Switch Mode Time Domain Locking (SMDL) scheme, presented herein, may be used to protect analog circuits. A first input signal to an analog circuit is generated. The first input signal comprises a reference phase. The analog circuit is adapted to perform a predetermined function. A second input signal to the analog circuit is generated. The second input signal comprises a provided phase. Enablement of the predetermined function of the analog circuit is toggled based on alignment of the reference phase and the provided phase.

Abstract: Wireless power transfer (WPT) efficiency is enhanced using an ultra-low power (ULP) distributed beamforming technique. A phase and frequency offset correction technique is used for beam-forming optimization, a backscattering communication technique is used to reduce power over-head, and a new rectifier and MPT method is used for high efficiency RF-to-DC conversion.

Abstract: Side channel attacks (SCA) such as correlation power analysis (CPA) have been demonstrated to be very effective in breaking cryptographic engines. The inherent dependence of the power consumption on the secret key can be exploited by statistical analysis to retrieve the key. Various embodiments disclosed herein relate to a new power obfuscation switched capacitor (POSC) DC-DC converter design, which can conceal the leakage of information through power consumption. It works by adding an extra phase to the conventional two-phase switched capacitor (SC) converter, during which a part of the charge from the flying capacitor is extracted and stored on a storage capacitor. This guarantees that the same amount of charge is drawn from the input power supply in each cycle. The design was successfully evaluated by analyzing the power supply to an Advanced Encryption Standard (AES) unit powered by the converter.

Abstract: Wireless power transfer (WPT) efficiency is enhanced using an ultra-low power (ULP) distributed beamforming technique. A phase and frequency offset correction technique is used for beam-forming optimization, a backscattering communication technique is used to reduce power over-head, and a new rectifier and MPT method is used for high efficiency RF-to-DC conversion.

Abstract: A radio frequency (RF) signal strength detection technique is disclosed with a received signal strength indicator (RSSI) circuit, which can be deployed in an internet-of-things (IoT) network. The RSSI circuit is based on a direct conversion of RF to digital code indicating the signal strength. The direct conversion is achieved by the repeated switching of a rectifier's output voltage using an ultra-low power comparator. A 5-bit programmable feedback circuit can be used to correct detection inaccuracies. The RSSI circuit can be implemented in a 65-nm CMOS process and consumes 15 nW power. It can have a linear dynamic range of 26 dB and exhibit an error of ±0.5 dB with a wide bandwidth of 500 MHz. The technique has been verified with simulation and measurement results. The high detection accuracy with ultra-low power consumption of the proposed RSSI circuit is favorable for IoT applications including, e.g., biomedical, localization, and other low-power applications.

Abstract: A cognitive radio (CR) based transceiver system including a receiver configured to sense a predetermined frequency band for a CR signal, wherein the CR signal includes phase noise, a transmitter configured to select a channel for CR signal transmission based on the predetermined frequency band, and generate a carrier frequency for the selected channel, and a trained machine learning model configured to correct the phase noise included in the CR signal.

Abstract: An analog computing method includes the steps of: (a) generating a biasing current (IWi) using a constant gm bias circuit operating in the subthreshold region for ultra-low power consumption, wherein gm is generated by PMOS or NMOS transistors, the circuit including a switched capacitor resistor; and (b) multiplying the biasing current by an input voltage using a differential amplifier multiplication circuit to generate an analog voltage output (VOi). In one or more embodiments, the method is used in a vision application, where the biasing current represents a weight in a convolution filter and the input voltage represents a pixel voltage of an acquired image.

Abstract: Wireless power transfer (WPT) efficiency is enhanced using an ultra-low power (ULP) distributed beamforming technique. A phase and frequency offset correction technique is used for beam-forming optimization, a backscattering communication technique is used to reduce power over-head, and a new rectifier and MPT method is used for high efficiency RF-to-DC conversion.

Abstract: Side channel attacks (SCA) such as correlation power analysis (CPA) have been demonstrated to be very effective in breaking cryptographic engines. The inherent dependence of the power consumption on the secret key can be exploited by statistical analysis to retrieve the key. Various embodiments disclosed herein relate to a new power obfuscation switched capacitor (POSC) DC-DC converter design, which can conceal the leakage of information through power consumption. It works by adding an extra phase to the conventional two-phase switched capacitor (SC) converter, during which a part of the charge from the flying capacitor is extracted and stored on a storage capacitor. This guarantees that the same amount of charge is drawn from the input power supply in each cycle. The design was successfully evaluated by analyzing the power supply to an Advanced Encryption Standard (AES) unit powered by the converter.

Abstract: An ultra-low power sub-threshold gm stage is disclosed where transconductance is very stable with process, temperature, and voltage variations. This technique can be implemented in a differential amplifier with constant gain and a second order biquad filter with constant cut off frequency. The amplifier gain can achieve a small temperature coefficient of 48.6 ppm/° C. and exhibits small sigma of 75 mdB with process. The second order biquad can achieve temperature stability of 69 ppm/° C. and a voltage coefficient of only 49 ppm/mV.

Abstract: An analog computing method includes the steps of: (a) generating a biasing current (IWi) using a constant gm bias circuit operating in the subthreshold region for ultra-low power consumption, wherein gm is generated by PMOS or NMOS transistors, the circuit including a switched capacitor resistor; and (b) multiplying the biasing current by an input voltage using a differential amplifier multiplication circuit to generate an analog voltage output (VOi). In one or more embodiments, the method is used in a vision application, where the biasing current represents a weight in a convolution filter and the input voltage represents a pixel voltage of an acquired image.

Abstract: An ultra-low power sub-threshold gm stage is disclosed where transconductance is very stable with process, temperature, and voltage variations. This technique can be implemented in a differential amplifier with constant gain and a second order biquad filter with constant cut off frequency. The amplifier gain can achieve a small temperature coefficient of 48.6 ppm/° C. and exhibits small sigma of 75 mdB with process. The second order biquad can achieve temperature stability of 69 ppm/° C. and a voltage coefficient of only 49 ppm/mV.

Abstract: In some embodiments, an apparatus includes a single-inductor multiple-output (SIMO) direct current (DC-DC) converter circuit, with the SIMO DC-DC converter circuit having a set of output nodes. The apparatus also includes a panoptic dynamic voltage scaling (PDVS) circuit operatively coupled to the SIMO DC-DC converter circuit, where the PDVS circuit has a set of operational blocks with each operational block from the set of operational blocks drawing power from one supply voltage rail from a set of supply voltage rails. Additionally, each output node from the set of output nodes is uniquely associated with a supply voltage rail from the set of supply voltage rails.

Abstract: In some embodiments, an apparatus includes a bandgap reference circuit having a first bipolar junction transistor (BJT) that can receive a current from a node having a terminal voltage and can output a base emitter voltage. The apparatus also includes a second bipolar junction transistor (BJT) having a device width greater than a device width of the first BJT. The second BJT can receive a current from a node having a terminal voltage and output a base emitter voltage. In such embodiments, the apparatus also includes a reference generation circuit operatively coupled to the first BJT and the second BJT, where the reference generation circuit can generate a bandgap reference voltage based on the base emitter voltage of the first BJT and the base emitter voltage of the second BJT.

Abstract: An ultra-low power clock source includes a compensated oscillator and an uncompensated oscillator coupled by a comparator circuit. In an example, the compensated oscillator is more stable than the uncompensated oscillator with respect to changes in one or more of temperature, voltage, age, or other environmental parameters. The uncompensated oscillator includes a configuration input configured to adjust an operating characteristic of the uncompensated oscillator. In an example, the uncompensated oscillator is adjusted using information from the comparator circuit about a comparison of output signals from the compensated oscillator and the uncompensated oscillator.

Abstract: A low voltage crystal oscillator (XTAL) driver with feedback controlled duty cycling for ultra low power biases an amplifier for an XTAL in the sub-threshold operating regime. A feedback control scheme can be used to bias the amplifier for an XTAL biased in the sub-threshold operating regime. The amplifier of a XTAL oscillator can be duty cycled to save power, e.g., the XTAL driver can be turned off to save power when the amplitude of the XTAL oscillation reaches a maximum value in range; but be turned back on when the amplitude of the XTAL oscillation starts to decay, to maintain the oscillation before it stops. In addition or alternatively, a feedback control scheme to duty cycle the amplifier of a XTAL oscillator can be used to monitor the amplitude of the oscillation.

Abstract: The low input voltage boost converter with peak inductor current control and offset compensated zero detection provide a boost converter scheme to harvest energy from sources with small output voltages. Some embodiments described herein includes a thermoelectric boost converter that combines an IPEAK control scheme with offset compensation and duty cycled comparators to enable energy harvesting from TEG inputs as low as 5 mV to 10 mV, and the peak inductor current is independent to first order of the input voltage and output voltage. A control circuit can be configured to sample the input voltage (VIN) and then generate a pulse with a duration inversely proportional to VIN so as to control the boost converter switches such that a substantially constant peak inductor current is generated.