Abstract: A system comprising an ambient energy source, a power supply, and a power storage device. The ambient energy source is coupled to a first terminal end of an inductor. The power supply is also coupled to the first terminal end of the inductor. The power storage device is coupled to a second terminal end of the inductor. The ambient energy source provides power through the inductor in a first direction to the power storage device. The power storage device provides power through the inductor to the power supply in a second direction opposite the first direction.

Abstract: Integrated Circuits (ICs) comprising circuits configured to generate a power on reset (POR) pulse are disclosed. An IC comprises a power supply sense circuit configured to generate a sense signal in response to a transition of a power supply signal from a first level to a second level, and a pulse generation circuit coupled with the power supply sense circuit. The pulse generation circuit is configured to generate a power on reset (POR) pulse of a threshold duration based on the sense signal. The IC further includes a reset generation circuit coupled with the pulse generation circuit to receive the POR pulse. The reset generation circuit is configured to generate a reset pulse based on the POR signal and of at least one control signal, where the reset pulse is configured to be utilized to perform a reset of one or more elements of the integrated circuit.

Abstract: Integrated Circuits (ICs) comprising circuits configured to generate a power on reset (POR) pulse are disclosed. An IC comprises a power supply sense circuit configured to generate a sense signal in response to a transition of a power supply signal from a first level to a second level, and a pulse generation circuit coupled with the power supply sense circuit. The pulse generation circuit is configured to generate a power on reset (POR) pulse of a threshold duration based on the sense signal. The IC further includes a reset generation circuit coupled with the pulse generation circuit to receive the POR pulse. The reset generation circuit is configured to generate a reset pulse based on the POR signal and of at least one control signal, where the reset pulse is configured to be utilized to perform a reset of one or more elements of the integrated circuit.

Abstract: An exemplary fast start-up crystal oscillator with reduced start-up time. The exemplary oscillator reduces the start-up time (i.e., the time taken to attain sustained stable oscillations after the power is turned on) by increasing the negative resistance of a circuit. Increasing the negative resistance increases the rate of growth of the oscillations, thereby reducing start-up time. The exemplary crystal oscillator includes a gain stage with negative resistance. A crystal with shunt capacitance is placed in the feedback loop of the gain stage. A buffer is coupled to the gain stage such that it blocks the crystal shunt capacitance from loading the gain stage, effectively increasing the negative resistance of the gain stage. Further, an oscillation detection and control circuit is coupled between the crystal and the gain stage. The oscillation detection and control circuit connects the buffer during start-up, and disconnects the buffer once an oscillation signal attains sustained stable oscillations.

Abstract: An output buffer receives an input signal and generates an output signal at an output node. The output buffer contains a driver circuit. The driver circuit includes two pairs of cascoded transistors connected at a junction node. Each of the cascoded pairs receives a corresponding level-shifted signal representing the input signal, and generates corresponding driver signals on driver nodes which are coupled to the output node. The driver circuit includes a capacitor connected between one of the driver nodes and the junction node. The capacitor enables the corresponding driver signal to be generated to reach a desired voltage quickly. The output impedance of the output buffer with which the output signal is launched is reduced and more closely matched the impedance of the path on which the output signal is provided. Signal quality of the output signal is thereby improved.

Abstract: An exemplary fast start-up crystal oscillator with reduced start-up time. The exemplary oscillator reduces the start-up time (i.e., the time taken to attain sustained stable oscillations after the power is turned on) by increasing the negative resistance of a circuit. Increasing the negative resistance increases the rate of growth of the oscillations, thereby reducing start-up time. The exemplary crystal oscillator includes a gain stage with negative resistance. A crystal with shunt capacitance is placed in the feedback loop of the gain stage. A buffer is coupled to the gain stage such that it blocks the crystal shunt capacitance from loading the gain stage, effectively increasing the negative resistance of the gain stage. Further, an oscillation detection and control circuit is coupled between the crystal and the gain stage. The oscillation detection and control circuit connects the buffer during start-up, and disconnects the buffer once an oscillation signal attains sustained stable oscillations.