Abstract: A CMOS DPS image sensor architecture for improving SNR and dynamic range is presented. The CMOS DPS architecture includes self-reset digital pixels capable of collecting more charge than the physical well capacity. A method for improving SNR without reducing dynamic range in a CMOS video sensor system under low illumination is described, wherein the CMOS video sensor system employing self-reset DPS architecture includes pixel level A/D conversion and wherein each DPS pixels is capable of resetting itself whenever a corresponding diode reaches saturation during integration time.

Abstract: An analog-to-digital conversion scheme allows the conversion of a small dynamic range analog signal into a floating-point, digital representation with a larger dynamic range. A montonically changing analog signal is reset to a reference value at time t=0. The analog signal is then sub-converted by an analog-to-digital converter with maximum input signal level Ss to corresponding digital representations at several sub-conversion times t=T2>T1, t=T3>T2, . . . t=TM>TM−1, where TM≦T. These digital representations are then suitably combined to produce a cumulative, floating-point digital representation which accurately represents the analog signal even if the analog signal has a value greater than Ss at time t=T.

Abstract: An analog-to-digital conversion scheme allows the conversion of a small dynamic range analog signal into a floating-point, digital representation with a larger dynamic range. A montonically changing analog signal is reset to a reference value at time t=0. The analog signal is then sub-converted by an analog-to-digital converter with maximum input signal level Ss to corresponding digital representations at several sub-conversion times t=T2>T1, t=T3>T2, . . . t=TM>TM−1, where TM≦T. These digital representations are then suitably combined to produce a cumulative, floating-point digital representation which accurately represents the analog signal even if the analog signal has a value greater than Ss at time t=T.

Abstract: An analog-to-digital conversion scheme allows the conversion of a small dynamic range analog signal into a floating-point, digital representation with a larger dynamic range. A montonically changing analog signal is reset to a reference value at time t=0. The analog signal is then sub-converted by an analog-to-digital converter with maximum input signal level Ss to corresponding digital representations at several sub-conversion times t=T2>T1t=T3>T2, . . . t=TM>TM−1, where TM≦T. These digital representations are then suitably combined to produce a cumulative, floating-point digital representation which accurately represents the analog signal even if the analog signal has a value greater than Ss at time t=T.

Abstract: A method of simultaneously providing A/D conversion and multiplication in a Bit-Serial ADCs and single slope ADCs. A bit serial ADC uses a RAMP signal and a BITX signal input to a comparator and 1-bit latch, respectively. When RAMP exceeds an analog input value, the comparator triggers the latch to output the value of BITX. The bits are output serially. The RAMP signal has a staircase shape with voltage levels and voltage steps. In the present invention, multiplication by two coefficients is possible. One coefficient is determined by properly designing RAMP, and the other coefficient is determined by properly designing BITX. Multiplication via RAMP is accomplished by changing the voltage levels by a factor of 1/X, where X is the multiplying coefficient (i.e., multiplication by a factor of 0.5 is accomplished by doubling the voltage of the voltage levels). Multiplication via BITX is accomplished by slowing the frequency of BITX by a factor of X.

Abstract: A method for optimizing an integrated circuit uses a dominant time constant of a transition of the circuit. A physical layout of the circuit is characterized in terms of design parameters. The circuit is modeled by a conductance matrix G and a capacitance matrix C, wherein G and C are affine functions of the design parameters. The optimization method comprises the step of finding the values of the design parameters that optimize a property of the circuit while simultaneously enforcing a constraint that the dominant time constant must be less than a maximum value tmax. Mathematically, the constraint on the dominant time constant can be written: tmax G−C≧0. The optimization method can be used when the circuit has a non-tree topology. Furthermore, when the design parameters comprise variables that relate to sizes of elements of the circuit, a topology of the circuit is optimized by the optimization method.

Abstract: A customizable ASIC routing architecture is provided. The architecture utilizes the uppermost metal layers of an ASIC composed of an array of function blocks for routing among function blocks while lower layers are used for local interconnections within the function blocks. The second-to-uppermost metal layer is fixed and generally includes a plurality of parallel segmented conductors extending in a first direction. The uppermost metal layer is customizable in a predesignated manner. Metal in the uppermost metal layer is selectively placed in tracks, which are substantially perpendicular to the segmented conductors in the layer below. Vias are provided between the two uppermost layers. One embodiment of the invention permits one-mask customization of an ASIC.

Abstract: A user-programmable interconnect architecture, which may be used for logic arrays for digital and analog system design, is disclosed. In one embodiment, a plurality of logic cells or modules in a matrix are connected by vertical and horizontal wiring channels. The wiring channels may in turn be programmed by the user to interconnect the various logic cells to implement the required logic function. The wiring channels comprise wiring segments connected by normally open programmable. Elements situated at the intersection of any two segments to be connected.

Abstract: A gate array in accordance with the invention includes a matrix of function blocks capable of being configured to implement combinational, sequential, and memory modes of operation, as well as providing tri-state drivers and buffers in useful numbers. The function block includes a logic circuit with a first bit storage unit, which is selectively configurable to behave as combinational logic or to store a first bit, and a second bit storage unit, which is also selectively configurable to behave as combinational logic or to store a second bit. The matrix of function blocks in accordance with the invention is also useful to properly distribute clocks throughout the gate array.

Abstract: A method for simultaneously performing bit serial analog to digital conversion (ADC) for a potentially very large number of signals is described. The method is ideally suited for performing on chip ADC in area image sensors. In one embodiment, to achieve N-bit precision, the method employs a one-bit comparator per channel (or set of multiplexed channels) and an N-bit DAC. To achieve N bits of precision, 2.sup.N -1 comparisons are sequentially performed. Each comparison is performed by first setting the DAC output to the desired value and then simultaneously comparing each of the pixel values to that value. If a pixel value is greater than the DAC output value, its comparator outputs a one, otherwise it outputs a zero. By appropriately choosing the sequence of comparison values, the pixel values are sequentially generated. In another embodiment, the DAC is omitted and a continuous ramp signal is generated for comparison with the analog input.

Abstract: A logic module includes first and second multiplexers each having two data inputs and a select input. Both select inputs are connected to the output of a two-input logic gate of a first type. The inputs to the first and second multiplexers comprise data signals from a first group. One input of each logic gate comprises a data signal of a second group and the other input of each logic gate comprises a data signal of a third group. A third multiplexer has first and second data inputs connected the outputs of the first and second multiplexers, respectively, and a select input connected to the output of a two-input logic gate of a second type. Its output is connected to a first data input of a fourth multiplexer having a HOLD1 input coupled to its select input. Its output and a CLEAR input are presented to an AND gate whose output is connected to the second data input of the fourth multiplexer and to the first data input of a fifth multiplexer. The fifth multiplexer select input comprises a HOLD2 input.

Abstract: Using the present invention, only a single design and development process needs to be conducted for ICs fabricated using a number of different fabrication processes. In one embodiment of this process, the IC is first designed on a CAD system using a generic Cell Based Architecture (CBA) library. This generic CBA library represents several libraries for different process technologies. The resulting generic design is then simulated and verified using best and worst case timing delays and other parameters which are derived from a combination of the various technologies. Hence, only one design need be created and simulated. Generic design rule and parasitic parameters are then used to optimize the placement and routing of the generic design. The post-layout generic design is then simulated and verified using performance characteristics determined by a combination of the technologies.

Abstract: A logic module includes first and second multiplexers each having two data inputs and a select input. Both select inputs are connected to the output of a two-input logic gate of a first type. The inputs to the first and second multiplexers comprise data signals from a first group. One input of each logic gate comprises a data signal of n second group and the other input of each logic gate comprises a data signal of a third group. A third multiplexer has first and second data inputs connected the outputs of the first and second multiplexers, respectively, and a select input connected to the output of a two-input logic gate of a second type. Its output is connected to a first data input of a fourth-multiplexer having a HOLD1 input coupled to its select input. Its output and a CLEAR input are presented to an AND gate whose output is connected to the second data input of the fourth multiplexer and to the first data input of a fifth multiplexer. The fifth multiplexer select input comprises a HOLD2 input.

Abstract: A user-programmable interconnect architecture, which may be used for logic arrays for digital and analog system design, is disclosed. In one embodiment, a plurality of logic cells or modules in a matrix are connected by vertical and horizontal wiring channels. The wiring channels may in turn be programmed by the user to interconnect the various logic cells to implement the required logic function. The wiring channels comprise wiring segments connected by normally open programmable. Elements situated at the intersection of any two segments to be connected.

Abstract: A user-programmable interconnect architecture, which may be used for logic arrays for digital and analog system design, is disclosed. In one embodiment, a plurality of logic cells or modules in a matrix are connected by vertical and horizontal wiring channels. The wiring channels may in turn be programmed by the user to interconnect the various logic cells to implement the required logic function. The wiring channels comprise wiring segments connected by normally open reconfigurable programmable elements situated at the intersection of any two segments to be connected.

Abstract: An image sensor formed using a CMOS process is described herein which includes a pixel array core of phototransistors whose conductivities are related to the magnitude of light impinging upon the phototransistors. The analog signals generated by the phototransistors are converted to a serial bit stream by an A/D converter connected at the output of each phototransistor and formed in the immediate area of each phototransistor within the array core. Thus, a separate digital stream for each pixel element is output from the array core, and parasitic effects and distortion are minimized. In one embodiment, a filter circuit is connected to an output of the array core for converting the individual digital streams from each pixel element to multi-bit values corresponding to the intensity of light impinging on the phototransistor.

Abstract: A logic module includes a first and a second two-input multiplexer each having first and second data inputs. Both the first and second multiplexer include a select input, both of which are connected to the output of a two-input logic gate of a first type having first and second data inputs. The inputs to the first and second two-input multiplexers are sourced with data signals from a first group. One input of each of the logic gates is sourced from a data signal of a second group and the other input of each of the logic gates is sourced from a data signal of a third group. A third two-input multiplexer has its first and second data inputs connected the outputs of the first and second multiplexers, respectively. A select input of the third two-input multiplexer is connected to the output of a two input logic gate of a second type having first and second data inputs.

Abstract: A user-programmable inter-chip interconnect architecture, which may be used for providing programmable interconnections among a plurality of integrated circuits, is disclosed. A plurality of main circuitry in the core region of an integrated circuit is connected through connection nodes to a programmable peripheral switch network in the frame region of the integrated circuit. The peripheral switch network may be programmed by the user to obtain the desired signal-propagating paths between said connection nodes and bonding pads of the peripheral switch network, or among bonding pads of the peripheral switch network. The peripheral switch network has intersecting wiring channels attached to the bonding pads and the connection nodes. Programmable junctions may be present at the intersections of the wiring channels. A substantial number of desired interconnections may be achieved that have only one such programmable junction in the signal-propagating path.

Abstract: A user-programmable interconnect architecture, which may be used for logic arrays for digital and analog system design, is disclosed. In one embodiment, a plurality of logic cells or modules in a matrix are connected by vertical and horizontal wiring channels. The wiring channels may in turn be programmed by the user to interconnect the various logic cells to implement the required logic function. The wiring channels comprise wiring segments connected by normally open programmable. Elements situated at the intersection of any two segments to be connected.

Abstract: An improved cell for use in a mask programmable gate array is disclosed herein. The preferred cell comprises two compute sections, each comprising two pairs of medium size P and N-channel transistors, two small N-channel transistors, and a single small P-channel transistor. Each cell also comprises a high efficiency drive section containing a single bipolar pull-up transistor, a large N-channel pull-down transistor, and a small P-channel transistor. By using this cell, an extremely high compute capability per die area is achieved.